diff options
Diffstat (limited to 'include/asm-arm/arch-at91')
-rw-r--r-- | include/asm-arm/arch-at91/at91_dbgu.h | 13 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/at91_shdwc.h | 4 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/at91_wdt.h | 2 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/at91x40.h | 55 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/cpu.h | 5 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/hardware.h | 17 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/timex.h | 5 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/uncompress.h | 4 |
8 files changed, 98 insertions, 7 deletions
diff --git a/include/asm-arm/arch-at91/at91_dbgu.h b/include/asm-arm/arch-at91/at91_dbgu.h index b0369e176f7..8019ffd0ad3 100644 --- a/include/asm-arm/arch-at91/at91_dbgu.h +++ b/include/asm-arm/arch-at91/at91_dbgu.h @@ -16,6 +16,7 @@ #ifndef AT91_DBGU_H #define AT91_DBGU_H +#ifdef AT91_DBGU #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ @@ -30,6 +31,15 @@ #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ +#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ +#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ + +#endif /* AT91_DBGU */ + +/* + * Some AT91 parts that don't have full DEBUG units still support the ID + * and extensions register. + */ #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ @@ -53,7 +63,4 @@ #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ -#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ -#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ - #endif diff --git a/include/asm-arm/arch-at91/at91_shdwc.h b/include/asm-arm/arch-at91/at91_shdwc.h index 795fcc26622..01b433de227 100644 --- a/include/asm-arm/arch-at91/at91_shdwc.h +++ b/include/asm-arm/arch-at91/at91_shdwc.h @@ -14,8 +14,8 @@ #define AT91_SHDWC_H #define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ -#define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */ -#define AT91_SHDW_KEY (0xff << 24) /* KEY Password */ +#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */ +#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ #define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h index 7251a344c74..1014e9bf181 100644 --- a/include/asm-arm/arch-at91/at91_wdt.h +++ b/include/asm-arm/arch-at91/at91_wdt.h @@ -15,7 +15,7 @@ #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ -#define AT91_WDT_KEY (0xff << 24) /* KEY Password */ +#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ diff --git a/include/asm-arm/arch-at91/at91x40.h b/include/asm-arm/arch-at91/at91x40.h new file mode 100644 index 00000000000..612203e0177 --- /dev/null +++ b/include/asm-arm/arch-at91/at91x40.h @@ -0,0 +1,55 @@ +/* + * include/asm-arm/arch-at91/at91x40.h + * + * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91X40_H +#define AT91X40_H + +/* + * IRQ list. + */ +#define AT91_ID_FIQ 0 /* FIQ */ +#define AT91_ID_SYS 1 /* System Peripheral */ +#define AT91X40_ID_USART0 2 /* USART port 0 */ +#define AT91X40_ID_USART1 3 /* USART port 1 */ +#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */ +#define AT91X40_ID_TC1 5 /* Timer/Counter 1*/ +#define AT91X40_ID_TC2 6 /* Timer/Counter 2*/ +#define AT91X40_ID_WD 7 /* Watchdog? */ +#define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */ + +#define AT91X40_ID_IRQ0 16 /* External IRQ 0 */ +#define AT91X40_ID_IRQ1 17 /* External IRQ 1 */ +#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */ + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_BASE_SYS 0xffc00000 + +#define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */ +#define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */ +#define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */ +#define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */ +#define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */ +#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */ +#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */ +#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */ +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ + +/* + * The AT91x40 series doesn't have a debug unit like the other AT91 parts. + * But it does have a chip identify register and extension ID, so define at + * least these here. + */ +#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */ +#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */ + +#endif /* AT91X40_H */ diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h index ef93c30a9c5..080cbb401a8 100644 --- a/include/asm-arm/arch-at91/cpu.h +++ b/include/asm-arm/arch-at91/cpu.h @@ -28,6 +28,11 @@ #define ARCH_ID_AT91SAM9RL64 0x019b03a0 +#define ARCH_ID_AT91M40800 0x14080044 +#define ARCH_ID_AT91R40807 0x44080746 +#define ARCH_ID_AT91M40807 0x14080745 +#define ARCH_ID_AT91R40008 0x44000840 + static inline unsigned long at91_cpu_identify(void) { return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 46835e945ae..8f1cdd38a96 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -26,18 +26,29 @@ #include <asm/arch/at91sam9263.h> #elif defined(CONFIG_ARCH_AT91SAM9RL) #include <asm/arch/at91sam9rl.h> +#elif defined(CONFIG_ARCH_AT91X40) +#include <asm/arch/at91x40.h> #else #error "Unsupported AT91 processor" #endif +#ifdef CONFIG_MMU /* * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF * to 0xFEF78000 .. 0xFF000000. (544Kb) */ #define AT91_IO_PHYS_BASE 0xFFF78000 -#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) #define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) +#else +/* + * Identity mapping for the non MMU case. + */ +#define AT91_IO_PHYS_BASE AT91_BASE_SYS +#define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE +#endif + +#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) /* Convert a physical IO address to virtual IO address */ #define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) @@ -66,7 +77,11 @@ #define AT91_CHIPSELECT_7 0x80000000 /* SDRAM */ +#ifdef CONFIG_DRAM_BASE +#define AT91_SDRAM_BASE CONFIG_DRAM_BASE +#else #define AT91_SDRAM_BASE AT91_CHIPSELECT_1 +#endif /* Clocks */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h index 2df1ee12dfb..a310698fb4d 100644 --- a/include/asm-arm/arch-at91/timex.h +++ b/include/asm-arm/arch-at91/timex.h @@ -42,6 +42,11 @@ #define AT91SAM9_MASTER_CLOCK 100000000 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) +#elif defined(CONFIG_ARCH_AT91X40) + +#define AT91X40_MASTER_CLOCK 40000000 +#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) + #endif #endif diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index 30ac587b3b4..272a7e0dc6c 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h @@ -33,20 +33,24 @@ */ static void putc(int c) { +#ifdef AT91_DBGU void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) barrier(); __raw_writel(c, sys + AT91_DBGU_THR); +#endif } static inline void flush(void) { +#ifdef AT91_DBGU void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ /* wait for transmission to complete */ while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) barrier(); +#endif } #define arch_decomp_setup() |