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-rw-r--r--include/asm-arm/arch-at91/at91_lcdc.h148
-rw-r--r--include/asm-arm/arch-at91/at91_pmc.h9
-rw-r--r--include/asm-arm/arch-at91/at91_rtt.h8
-rw-r--r--include/asm-arm/arch-at91/at91_twi.h11
-rw-r--r--include/asm-arm/arch-at91/at91cap9.h121
-rw-r--r--include/asm-arm/arch-at91/at91cap9_matrix.h132
-rw-r--r--include/asm-arm/arch-at91/at91sam9260_matrix.h2
-rw-r--r--include/asm-arm/arch-at91/at91sam9263_matrix.h2
-rw-r--r--include/asm-arm/arch-at91/at91sam9rl_matrix.h2
-rw-r--r--include/asm-arm/arch-at91/board.h38
-rw-r--r--include/asm-arm/arch-at91/cpu.h9
-rw-r--r--include/asm-arm/arch-at91/entry-macro.S2
-rw-r--r--include/asm-arm/arch-at91/hardware.h2
-rw-r--r--include/asm-arm/arch-at91/timex.h5
-rw-r--r--include/asm-arm/arch-ep93xx/gpio.h58
-rw-r--r--include/asm-arm/arch-ep93xx/irqs.h6
-rw-r--r--include/asm-arm/arch-ixp4xx/io.h16
-rw-r--r--include/asm-arm/arch-ixp4xx/platform.h11
-rw-r--r--include/asm-arm/arch-ks8695/regs-gpio.h2
-rw-r--r--include/asm-arm/arch-msm/board.h37
-rw-r--r--include/asm-arm/arch-msm/debug-macro.S40
-rw-r--r--include/asm-arm/arch-msm/dma.h151
-rw-r--r--include/asm-arm/arch-msm/entry-macro.S38
-rw-r--r--include/asm-arm/arch-msm/hardware.h18
-rw-r--r--include/asm-arm/arch-msm/io.h33
-rw-r--r--include/asm-arm/arch-msm/irqs.h89
-rw-r--r--include/asm-arm/arch-msm/memory.h27
-rw-r--r--include/asm-arm/arch-msm/msm_iomap.h104
-rw-r--r--include/asm-arm/arch-msm/system.h23
-rw-r--r--include/asm-arm/arch-msm/timex.h20
-rw-r--r--include/asm-arm/arch-msm/uncompress.h36
-rw-r--r--include/asm-arm/arch-msm/vmalloc.h22
-rw-r--r--include/asm-arm/arch-omap/tps65010.h156
-rw-r--r--include/asm-arm/arch-orion/debug-macro.S17
-rw-r--r--include/asm-arm/arch-orion/dma.h1
-rw-r--r--include/asm-arm/arch-orion/entry-macro.S31
-rw-r--r--include/asm-arm/arch-orion/gpio.h28
-rw-r--r--include/asm-arm/arch-orion/hardware.h24
-rw-r--r--include/asm-arm/arch-orion/io.h27
-rw-r--r--include/asm-arm/arch-orion/irqs.h61
-rw-r--r--include/asm-arm/arch-orion/memory.h15
-rw-r--r--include/asm-arm/arch-orion/orion.h143
-rw-r--r--include/asm-arm/arch-orion/platform.h25
-rw-r--r--include/asm-arm/arch-orion/system.h31
-rw-r--r--include/asm-arm/arch-orion/timex.h12
-rw-r--r--include/asm-arm/arch-orion/uncompress.h44
-rw-r--r--include/asm-arm/arch-orion/vmalloc.h5
-rw-r--r--include/asm-arm/arch-pxa/i2c.h6
-rw-r--r--include/asm-arm/arch-s3c2410/debug-macro.S2
-rw-r--r--include/asm-arm/arch-s3c2410/dma.h1
-rw-r--r--include/asm-arm/arch-s3c2410/hardware.h28
-rw-r--r--include/asm-arm/arch-s3c2410/irqs.h3
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h2
-rw-r--r--include/asm-arm/arch-s3c2410/regs-dsc.h2
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h6
-rw-r--r--include/asm-arm/arch-s3c2410/regs-mem.h6
-rw-r--r--include/asm-arm/arch-s3c2410/regs-power.h3
-rw-r--r--include/asm-arm/arch-s3c2410/system.h20
-rw-r--r--include/asm-arm/cacheflush.h8
-rw-r--r--include/asm-arm/fpstate.h9
-rw-r--r--include/asm-arm/kprobes.h79
-rw-r--r--include/asm-arm/plat-s3c24xx/dma.h5
-rw-r--r--include/asm-arm/plat-s3c24xx/irq.h2
-rw-r--r--include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h72
-rw-r--r--include/asm-arm/plat-s3c24xx/regs-spi.h32
-rw-r--r--include/asm-arm/proc-fns.h8
-rw-r--r--include/asm-arm/traps.h9
-rw-r--r--include/asm-arm/vfp.h34
-rw-r--r--include/asm-arm/vfpmacros.h18
69 files changed, 1813 insertions, 384 deletions
diff --git a/include/asm-arm/arch-at91/at91_lcdc.h b/include/asm-arm/arch-at91/at91_lcdc.h
deleted file mode 100644
index ab040a40d37..00000000000
--- a/include/asm-arm/arch-at91/at91_lcdc.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_lcdc.h
- *
- * LCD Controller (LCDC).
- * Based on AT91SAM9261 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_LCDC_H
-#define AT91_LCDC_H
-
-#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */
-#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */
-#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */
-#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */
-#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */
-#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */
-
-#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */
-#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */
-#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */
-
-#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */
-#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */
-#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */
-#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */
-
-#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */
-#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */
-#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */
-#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */
-
-#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */
-#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */
-#define AT91_LCDC_DISTYPE_STNMONO (0 << 0)
-#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0)
-#define AT91_LCDC_DISTYPE_TFT (2 << 0)
-#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */
-#define AT91_LCDC_SCANMOD_SINGLE (0 << 2)
-#define AT91_LCDC_SCANMOD_DUAL (1 << 2)
-#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */
-#define AT91_LCDC_IFWIDTH_4 (0 << 3)
-#define AT91_LCDC_IFWIDTH_8 (1 << 3)
-#define AT91_LCDC_IFWIDTH_16 (2 << 3)
-#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */
-#define AT91_LCDC_PIXELSIZE_1 (0 << 5)
-#define AT91_LCDC_PIXELSIZE_2 (1 << 5)
-#define AT91_LCDC_PIXELSIZE_4 (2 << 5)
-#define AT91_LCDC_PIXELSIZE_8 (3 << 5)
-#define AT91_LCDC_PIXELSIZE_16 (4 << 5)
-#define AT91_LCDC_PIXELSIZE_24 (5 << 5)
-#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */
-#define AT91_LCDC_INVVD_NORMAL (0 << 8)
-#define AT91_LCDC_INVVD_INVERTED (1 << 8)
-#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */
-#define AT91_LCDC_INVFRAME_NORMAL (0 << 9)
-#define AT91_LCDC_INVFRAME_INVERTED (1 << 9)
-#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */
-#define AT91_LCDC_INVLINE_NORMAL (0 << 10)
-#define AT91_LCDC_INVLINE_INVERTED (1 << 10)
-#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */
-#define AT91_LCDC_INVCLK_NORMAL (0 << 11)
-#define AT91_LCDC_INVCLK_INVERTED (1 << 11)
-#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */
-#define AT91_LCDC_INVDVAL_NORMAL (0 << 12)
-#define AT91_LCDC_INVDVAL_INVERTED (1 << 12)
-#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */
-#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
-#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
-#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */
-#define AT91_LCDC_MEMOR_BIG (0 << 31)
-#define AT91_LCDC_MEMOR_LITTLE (1 << 31)
-
-#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */
-#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */
-#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */
-#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */
-#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */
-
-#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */
-#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */
-#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */
-#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */
-
-#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */
-#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */
-#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */
-
-#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */
-#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */
-
-#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */
-#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */
-#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */
-#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */
-#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */
-#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */
-#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */
-#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */
-#define AT91_LCDC_DP1_2_VAL (0xff)
-#define AT91_LCDC_DP4_7_VAL (0xfffffff)
-#define AT91_LCDC_DP3_5_VAL (0xfffff)
-#define AT91_LCDC_DP2_3_VAL (0xfff)
-#define AT91_LCDC_DP5_7_VAL (0xfffffff)
-#define AT91_LCDC_DP3_4_VAL (0xffff)
-#define AT91_LCDC_DP4_5_VAL (0xfffff)
-#define AT91_LCDC_DP6_7_VAL (0xfffffff)
-
-#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */
-#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */
-#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */
-#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */
-
-#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */
-#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */
-#define AT91_LCDC_PS_DIV1 (0 << 0)
-#define AT91_LCDC_PS_DIV2 (1 << 0)
-#define AT91_LCDC_PS_DIV4 (2 << 0)
-#define AT91_LCDC_PS_DIV8 (3 << 0)
-#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */
-#define AT91_LCDC_POL_NEGATIVE (0 << 2)
-#define AT91_LCDC_POL_POSITIVE (1 << 2)
-#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */
-#define AT91_LCDC_ENA_PWMDISABLE (0 << 3)
-#define AT91_LCDC_ENA_PWMENABLE (1 << 3)
-
-#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */
-#define AT91_LCDC_CVAL (0xff) /* PWM compare value */
-
-#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */
-#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */
-#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */
-#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */
-#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */
-#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */
-#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */
-#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */
-#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */
-#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */
-#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */
-
-#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 33ff5b6798e..52cd8e5dabc 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -25,6 +25,7 @@
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
+#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
@@ -37,7 +38,9 @@
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
-#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
+#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
+
+#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
@@ -52,6 +55,10 @@
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
+#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
+#define AT91_PMC_USBDIV_1 (0 << 28)
+#define AT91_PMC_USBDIV_2 (1 << 28)
+#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
diff --git a/include/asm-arm/arch-at91/at91_rtt.h b/include/asm-arm/arch-at91/at91_rtt.h
index bae1103fbbb..39a32633b27 100644
--- a/include/asm-arm/arch-at91/at91_rtt.h
+++ b/include/asm-arm/arch-at91/at91_rtt.h
@@ -13,19 +13,19 @@
#ifndef AT91_RTT_H
#define AT91_RTT_H
-#define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */
+#define AT91_RTT_MR 0x00 /* Real-time Mode Register */
#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
-#define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */
+#define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
-#define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */
+#define AT91_RTT_VR 0x08 /* Real-time Value Register */
#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
-#define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */
+#define AT91_RTT_SR 0x0c /* Real-time Status Register */
#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h
index ca9a9073345..f9f2e3cd95c 100644
--- a/include/asm-arm/arch-at91/at91_twi.h
+++ b/include/asm-arm/arch-at91/at91_twi.h
@@ -21,6 +21,8 @@
#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
+#define AT91_TWI_SVEN (1 << 4) /* Slave Transfer Enable [SAM9260 only] */
+#define AT91_TWI_SVDIS (1 << 5) /* Slave Transfer Disable [SAM9260 only] */
#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
#define AT91_TWI_MMR 0x04 /* Master Mode Register */
@@ -32,6 +34,9 @@
#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
+#define AT91_TWI_SMR 0x08 /* Slave Mode Register [SAM9260 only] */
+#define AT91_TWI_SADR (0x7f << 16) /* Slave Address */
+
#define AT91_TWI_IADR 0x0c /* Internal Address Register */
#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
@@ -43,9 +48,15 @@
#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
+#define AT91_TWI_SVREAD (1 << 3) /* Slave Read [SAM9260 only] */
+#define AT91_TWI_SVACC (1 << 4) /* Slave Access [SAM9260 only] */
+#define AT91_TWI_GACC (1 << 5) /* General Call Access [SAM9260 only] */
#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
+#define AT91_TWI_ARBLST (1 << 9) /* Arbitration Lost [SAM9260 only] */
+#define AT91_TWI_SCLWS (1 << 10) /* Clock Wait State [SAM9260 only] */
+#define AT91_TWI_EOSACC (1 << 11) /* End of Slave Address [SAM9260 only] */
#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
new file mode 100644
index 00000000000..73e1fcf4a0a
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -0,0 +1,121 @@
+/*
+ * include/asm-arm/arch-at91/at91cap9.h
+ *
+ * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91CAP9 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91CAP9_H
+#define AT91CAP9_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS 1 /* System Peripherals */
+#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
+#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
+#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
+#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
+#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
+#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
+#define AT91CAP9_ID_US0 8 /* USART 0 */
+#define AT91CAP9_ID_US1 9 /* USART 1 */
+#define AT91CAP9_ID_US2 10 /* USART 2 */
+#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
+#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
+#define AT91CAP9_ID_CAN 13 /* CAN */
+#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
+#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
+#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
+#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
+#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
+#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
+#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
+#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
+#define AT91CAP9_ID_EMAC 22 /* Ethernet */
+#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
+#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
+#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
+#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
+#define AT91CAP9_ID_DMA 27 /* DMA Controller */
+#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
+#define AT91CAP9_ID_UHP 29 /* USB Host Port */
+#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
+#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91CAP9_BASE_UDPHS 0xfff78000
+#define AT91CAP9_BASE_TCB0 0xfff7c000
+#define AT91CAP9_BASE_TC0 0xfff7c000
+#define AT91CAP9_BASE_TC1 0xfff7c040
+#define AT91CAP9_BASE_TC2 0xfff7c080
+#define AT91CAP9_BASE_MCI0 0xfff80000
+#define AT91CAP9_BASE_MCI1 0xfff84000
+#define AT91CAP9_BASE_TWI 0xfff88000
+#define AT91CAP9_BASE_US0 0xfff8c000
+#define AT91CAP9_BASE_US1 0xfff90000
+#define AT91CAP9_BASE_US2 0xfff94000
+#define AT91CAP9_BASE_SSC0 0xfff98000
+#define AT91CAP9_BASE_SSC1 0xfff9c000
+#define AT91CAP9_BASE_AC97C 0xfffa0000
+#define AT91CAP9_BASE_SPI0 0xfffa4000
+#define AT91CAP9_BASE_SPI1 0xfffa8000
+#define AT91CAP9_BASE_CAN 0xfffac000
+#define AT91CAP9_BASE_PWMC 0xfffb8000
+#define AT91CAP9_BASE_EMAC 0xfffbc000
+#define AT91CAP9_BASE_ADC 0xfffc0000
+#define AT91CAP9_BASE_ISI 0xfffc4000
+#define AT91_BASE_SYS 0xffffe200
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
+#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
+#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
+#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
+#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
+#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
+#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
+#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
+#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDC (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
+
+/*
+ * Internal Memory.
+ */
+#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
+#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
+
+#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
+#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
+
+#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
+#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
+#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
+
+#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h
new file mode 100644
index 00000000000..a641686b6c3
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9_matrix.h
@@ -0,0 +1,132 @@
+/*
+ * include/asm-arm/arch-at91/at91cap9_matrix.h
+ *
+ * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2006 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91CAP9 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91CAP9_MATRIX_H
+#define AT91CAP9_MATRIX_H
+
+#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
+#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+
+#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
+#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
+#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
+#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
+#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
+#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
+#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
+#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
+#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
+#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
+#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
+#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
+
+#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
+#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91_MATRIX_RCB2 (1 << 2)
+#define AT91_MATRIX_RCB3 (1 << 3)
+#define AT91_MATRIX_RCB4 (1 << 4)
+#define AT91_MATRIX_RCB5 (1 << 5)
+#define AT91_MATRIX_RCB6 (1 << 6)
+#define AT91_MATRIX_RCB7 (1 << 7)
+#define AT91_MATRIX_RCB8 (1 << 8)
+#define AT91_MATRIX_RCB9 (1 << 9)
+#define AT91_MATRIX_RCB10 (1 << 10)
+#define AT91_MATRIX_RCB11 (1 << 11)
+
+#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
+#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
+
+#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
+#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
+#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
+#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
+#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
+
+#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
+#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
+#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h
index aacb1e97642..a8e9fec6c73 100644
--- a/include/asm-arm/arch-at91/at91sam9260_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9260_matrix.h
@@ -67,7 +67,7 @@
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_CS4A_SMC (0 << 4)
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */
+#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_CS5A_SMC (0 << 5)
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h
index 6fc6e4be624..72f6e668e41 100644
--- a/include/asm-arm/arch-at91/at91sam9263_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9263_matrix.h
@@ -44,7 +44,7 @@
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
+#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
index b15f11b7c08..84224174e6a 100644
--- a/include/asm-arm/arch-at91/at91sam9rl_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
@@ -38,7 +38,7 @@
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
+#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index 79054965baa..55b07bd5316 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -34,6 +34,7 @@
#include <linux/mtd/partitions.h>
#include <linux/device.h>
#include <linux/i2c.h>
+#include <linux/leds.h>
#include <linux/spi/spi.h>
/* USB Device */
@@ -71,7 +72,7 @@ struct at91_eth_data {
};
extern void __init at91_add_device_eth(struct at91_eth_data *data);
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263)
+#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
#define eth_platform_data at91_eth_data
#endif
@@ -101,13 +102,23 @@ extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_de
extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
/* Serial */
+#define ATMEL_UART_CTS 0x01
+#define ATMEL_UART_RTS 0x02
+#define ATMEL_UART_DSR 0x04
+#define ATMEL_UART_DTR 0x08
+#define ATMEL_UART_DCD 0x10
+#define ATMEL_UART_RI 0x20
+
+extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
+extern void __init at91_set_serial_console(unsigned portnr);
+
struct at91_uart_config {
unsigned short console_tty; /* tty number of serial console */
unsigned short nr_tty; /* number of serial tty's */
short tty_map[]; /* map UART to tty number */
};
extern struct platform_device *atmel_default_console_device;
-extern void __init at91_init_serial(struct at91_uart_config *config);
+extern void __init __deprecated at91_init_serial(struct at91_uart_config *config);
struct atmel_uart_data {
short use_dma_tx; /* use transmit DMA? */
@@ -116,6 +127,23 @@ struct atmel_uart_data {
};
extern void __init at91_add_device_serial(void);
+/*
+ * SSC -- accessed through ssc_request(id). Drivers don't bind to SSC
+ * platform devices. Their SSC ID is part of their configuration data,
+ * along with information about which SSC signals they should use.
+ */
+#define ATMEL_SSC_TK 0x01
+#define ATMEL_SSC_TF 0x02
+#define ATMEL_SSC_TD 0x04
+#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
+
+#define ATMEL_SSC_RK 0x10
+#define ATMEL_SSC_RF 0x20
+#define ATMEL_SSC_RD 0x40
+#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
+
+extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
+
/* LCD Controller */
struct atmel_lcdfb_info;
extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
@@ -126,10 +154,12 @@ struct atmel_ac97_data {
};
extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
+ /* ISI */
+extern void __init at91_add_device_isi(void);
+
/* LEDs */
-extern u8 at91_leds_cpu;
-extern u8 at91_leds_timer;
extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
+extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
/* FIXME: this needs a better location, but gets stuff building again */
extern int at91_suspend_entering_slow_clock(void);
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 080cbb401a8..7145166826a 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -21,13 +21,13 @@
#define ARCH_ID_AT91SAM9260 0x019803a0
#define ARCH_ID_AT91SAM9261 0x019703a0
#define ARCH_ID_AT91SAM9263 0x019607a0
+#define ARCH_ID_AT91SAM9RL64 0x019b03a0
+#define ARCH_ID_AT91CAP9 0x039A03A0
#define ARCH_ID_AT91SAM9XE128 0x329973a0
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
-#define ARCH_ID_AT91SAM9RL64 0x019b03a0
-
#define ARCH_ID_AT91M40800 0x14080044
#define ARCH_ID_AT91R40807 0x44080746
#define ARCH_ID_AT91M40807 0x14080745
@@ -81,6 +81,11 @@ static inline unsigned long at91_arch_identify(void)
#define cpu_is_at91sam9rl() (0)
#endif
+#ifdef CONFIG_ARCH_AT91CAP9
+#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
+#else
+#define cpu_is_at91cap9() (0)
+#endif
/*
* Since this is ARM, we will never run on any AVR32 CPU. But these
diff --git a/include/asm-arm/arch-at91/entry-macro.S b/include/asm-arm/arch-at91/entry-macro.S
index cc1d850a078..1005eee6219 100644
--- a/include/asm-arm/arch-at91/entry-macro.S
+++ b/include/asm-arm/arch-at91/entry-macro.S
@@ -17,13 +17,13 @@
.endm
.macro get_irqnr_preamble, base, tmp
+ ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number
teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 8f1cdd38a96..2c826d8247a 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -26,6 +26,8 @@
#include <asm/arch/at91sam9263.h>
#elif defined(CONFIG_ARCH_AT91SAM9RL)
#include <asm/arch/at91sam9rl.h>
+#elif defined(CONFIG_ARCH_AT91CAP9)
+#include <asm/arch/at91cap9.h>
#elif defined(CONFIG_ARCH_AT91X40)
#include <asm/arch/at91x40.h>
#else
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index a310698fb4d..f1933b0fa43 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -42,6 +42,11 @@
#define AT91SAM9_MASTER_CLOCK 100000000
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
+#elif defined(CONFIG_ARCH_AT91CAP9)
+
+#define AT91CAP9_MASTER_CLOCK 100000000
+#define CLOCK_TICK_RATE (AT91CAP9_MASTER_CLOCK/16)
+
#elif defined(CONFIG_ARCH_AT91X40)
#define AT91X40_MASTER_CLOCK 40000000
diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h
index 1ee14a14cba..9b1864bbd9a 100644
--- a/include/asm-arm/arch-ep93xx/gpio.h
+++ b/include/asm-arm/arch-ep93xx/gpio.h
@@ -5,16 +5,6 @@
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
-#define GPIO_IN 0
-#define GPIO_OUT 1
-
-#define EP93XX_GPIO_LOW 0
-#define EP93XX_GPIO_HIGH 1
-
-extern void gpio_line_config(int line, int direction);
-extern int gpio_line_get(int line);
-extern void gpio_line_set(int line, int value);
-
/* GPIO port A. */
#define EP93XX_GPIO_LINE_A(x) ((x) + 0)
#define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0)
@@ -38,7 +28,7 @@ extern void gpio_line_set(int line, int value);
#define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7)
/* GPIO port C. */
-#define EP93XX_GPIO_LINE_C(x) ((x) + 16)
+#define EP93XX_GPIO_LINE_C(x) ((x) + 40)
#define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0)
#define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1)
#define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2)
@@ -71,7 +61,7 @@ extern void gpio_line_set(int line, int value);
#define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7)
/* GPIO port F. */
-#define EP93XX_GPIO_LINE_F(x) ((x) + 40)
+#define EP93XX_GPIO_LINE_F(x) ((x) + 16)
#define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0)
#define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1)
#define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2)
@@ -103,5 +93,49 @@ extern void gpio_line_set(int line, int value);
#define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6)
#define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7)
+/* maximum value for gpio line identifiers */
+#define EP93XX_GPIO_LINE_MAX EP93XX_GPIO_LINE_H(7)
+
+/* maximum value for irq capable line identifiers */
+#define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7)
+
+/* new generic GPIO API - see Documentation/gpio.txt */
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+ if (gpio > EP93XX_GPIO_LINE_MAX)
+ return -EINVAL;
+ return 0;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+}
+
+int gpio_direction_input(unsigned gpio);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_value(unsigned gpio, int value);
+
+#include <asm-generic/gpio.h> /* cansleep wrappers */
+
+/*
+ * Map GPIO A0..A7 (0..7) to irq 64..71,
+ * B0..B7 (7..15) to irq 72..79, and
+ * F0..F7 (16..24) to irq 80..87.
+ */
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+ if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ)
+ return 64 + gpio;
+
+ return -EINVAL;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+ return irq - gpio_to_irq(0);
+}
#endif
diff --git a/include/asm-arm/arch-ep93xx/irqs.h b/include/asm-arm/arch-ep93xx/irqs.h
index 2a8c63638c5..53d4a68bfc8 100644
--- a/include/asm-arm/arch-ep93xx/irqs.h
+++ b/include/asm-arm/arch-ep93xx/irqs.h
@@ -67,12 +67,6 @@
#define IRQ_EP93XX_SAI 60
#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff
-/*
- * Map GPIO A0..A7 to irq 64..71, B0..B7 to 72..79, and
- * F0..F7 to 80..87.
- */
-#define IRQ_EP93XX_GPIO(x) (64 + (((x) + (((x) >> 2) & 8)) & 0x1f))
-
#define NR_EP93XX_IRQS (64 + 24)
#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x))
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index eeeea90cd5a..9c5d2357aff 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -61,13 +61,13 @@ __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
return __arm_ioremap(addr, size, mtype);
- return (void *)addr;
+ return (void __iomem *)addr;
}
static inline void
__ixp4xx_iounmap(void __iomem *addr)
{
- if ((u32)addr >= VMALLOC_START)
+ if ((__force u32)addr >= VMALLOC_START)
__iounmap(addr);
}
@@ -141,9 +141,9 @@ __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
static inline void
__ixp4xx_writel(u32 value, volatile void __iomem *p)
{
- u32 addr = (u32)p;
+ u32 addr = (__force u32)p;
if (addr >= VMALLOC_START) {
- __raw_writel(value, addr);
+ __raw_writel(value, p);
return;
}
@@ -208,11 +208,11 @@ __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
static inline unsigned long
__ixp4xx_readl(const volatile void __iomem *p)
{
- u32 addr = (u32)p;
+ u32 addr = (__force u32)p;
u32 data;
if (addr >= VMALLOC_START)
- return __raw_readl(addr);
+ return __raw_readl(p);
if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
return 0xffffffff;
@@ -438,7 +438,7 @@ __ixp4xx_ioread32(const void __iomem *addr)
return (unsigned int)__ixp4xx_inl(port & PIO_MASK);
else {
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
- return le32_to_cpu(__raw_readl((u32)port));
+ return le32_to_cpu((__force __le32)__raw_readl(addr));
#else
return (unsigned int)__ixp4xx_readl(addr);
#endif
@@ -523,7 +523,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr)
__ixp4xx_outl(value, port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
- __raw_writel(cpu_to_le32(value), port);
+ __raw_writel((u32 __force)cpu_to_le32(value), addr);
#else
__ixp4xx_writel(value, addr);
#endif
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index 2a44d3d6798..2ce28e3fd32 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -76,17 +76,6 @@ extern unsigned long ixp4xx_exp_bus_size;
#define IXP4XX_UART_XTAL 14745600
/*
- * The IXP4xx chips do not have an I2C unit, so GPIO lines are just
- * used to
- * Used as platform_data to provide GPIO pin information to the ixp42x
- * I2C driver.
- */
-struct ixp4xx_i2c_pins {
- unsigned long sda_pin;
- unsigned long scl_pin;
-};
-
-/*
* This structure provide a means for the board setup code
* to give information to th pata_ixp4xx driver. It is
* passed as platform_data.
diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h
index 57fcf9fc82e..6b95d77aea1 100644
--- a/include/asm-arm/arch-ks8695/regs-gpio.h
+++ b/include/asm-arm/arch-ks8695/regs-gpio.h
@@ -49,5 +49,7 @@
#define IOPC_TM_FALLING (4) /* Falling Edge Detection */
#define IOPC_TM_EDGE (6) /* Both Edge Detection */
+/* Port Data Register */
+#define IOPD_(x) (1 << (x)) /* Signal Level of GPIO Pin x */
#endif
diff --git a/include/asm-arm/arch-msm/board.h b/include/asm-arm/arch-msm/board.h
new file mode 100644
index 00000000000..763051f8ba1
--- /dev/null
+++ b/include/asm-arm/arch-msm/board.h
@@ -0,0 +1,37 @@
+/* linux/include/asm-arm/arch-msm/board.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_BOARD_H
+#define __ASM_ARCH_MSM_BOARD_H
+
+#include <linux/types.h>
+
+/* platform device data structures */
+
+struct msm_mddi_platform_data
+{
+ void (*panel_power)(int on);
+ unsigned has_vsync_irq:1;
+};
+
+/* common init routines for use by arch/arm/mach-msm/board-*.c */
+
+void __init msm_add_devices(void);
+void __init msm_map_common_io(void);
+void __init msm_init_irq(void);
+void __init msm_init_gpio(void);
+
+#endif
diff --git a/include/asm-arm/arch-msm/debug-macro.S b/include/asm-arm/arch-msm/debug-macro.S
new file mode 100644
index 00000000000..393d5272e50
--- /dev/null
+++ b/include/asm-arm/arch-msm/debug-macro.S
@@ -0,0 +1,40 @@
+/* include/asm-arm/arch-msm7200/debug-macro.S
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/hardware.h>
+#include <asm/arch/msm_iomap.h>
+
+ .macro addruart,rx
+ @ see if the MMU is enabled and select appropriate base address
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1
+ ldreq \rx, =MSM_UART1_PHYS
+ ldrne \rx, =MSM_UART1_BASE
+ .endm
+
+ .macro senduart,rd,rx
+ str \rd, [\rx, #0x0C]
+ .endm
+
+ .macro waituart,rd,rx
+ @ wait for TX_READY
+1: ldr \rd, [\rx, #0x08]
+ tst \rd, #0x04
+ beq 1b
+ .endm
+
+ .macro busyuart,rd,rx
+ .endm
diff --git a/include/asm-arm/arch-msm/dma.h b/include/asm-arm/arch-msm/dma.h
new file mode 100644
index 00000000000..e4b565b27b3
--- /dev/null
+++ b/include/asm-arm/arch-msm/dma.h
@@ -0,0 +1,151 @@
+/* linux/include/asm-arm/arch-msm/dma.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_DMA_H
+
+#include <linux/list.h>
+#include <asm/arch/msm_iomap.h>
+
+struct msm_dmov_cmd {
+ struct list_head list;
+ unsigned int cmdptr;
+ void (*complete_func)(struct msm_dmov_cmd *cmd, unsigned int result);
+/* void (*user_result_func)(struct msm_dmov_cmd *cmd); */
+};
+
+void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
+void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd);
+int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
+/* int msm_dmov_exec_cmd_etc(unsigned id, unsigned int cmdptr, int timeout, int interruptible); */
+
+
+
+#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
+#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
+#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
+#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
+
+/* only security domain 3 is available to the ARM11
+ * SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM
+ */
+
+#define DMOV_CMD_PTR(ch) DMOV_SD3(0x000, ch)
+#define DMOV_CMD_LIST (0 << 29) /* does not work */
+#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
+#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
+#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
+#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
+
+#define DMOV_RSLT(ch) DMOV_SD3(0x040, ch)
+#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
+#define DMOV_RSLT_ERROR (1 << 3)
+#define DMOV_RSLT_FLUSH (1 << 2)
+#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
+#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
+
+#define DMOV_FLUSH0(ch) DMOV_SD3(0x080, ch)
+#define DMOV_FLUSH1(ch) DMOV_SD3(0x0C0, ch)
+#define DMOV_FLUSH2(ch) DMOV_SD3(0x100, ch)
+#define DMOV_FLUSH3(ch) DMOV_SD3(0x140, ch)
+#define DMOV_FLUSH4(ch) DMOV_SD3(0x180, ch)
+#define DMOV_FLUSH5(ch) DMOV_SD3(0x1C0, ch)
+
+#define DMOV_STATUS(ch) DMOV_SD3(0x200, ch)
+#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
+#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
+#define DMOV_STATUS_RSLT_VALID (1 << 1)
+#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
+
+#define DMOV_ISR DMOV_SD3(0x380, 0)
+
+#define DMOV_CONFIG(ch) DMOV_SD3(0x300, ch)
+#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
+#define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1)
+#define DMOV_CONFIG_IRQ_EN (1 << 0)
+
+/* channel assignments */
+
+#define DMOV_NAND_CHAN 7
+#define DMOV_NAND_CRCI_CMD 5
+#define DMOV_NAND_CRCI_DATA 4
+
+#define DMOV_SDC1_CHAN 8
+#define DMOV_SDC1_CRCI 6
+
+#define DMOV_SDC2_CHAN 8
+#define DMOV_SDC2_CRCI 7
+
+#define DMOV_TSIF_CHAN 10
+#define DMOV_TSIF_CRCI 10
+
+#define DMOV_USB_CHAN 11
+
+/* no client rate control ifc (eg, ram) */
+#define DMOV_NONE_CRCI 0
+
+
+/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
+ * is going to walk a list of 32bit pointers as described below. Each
+ * pointer points to a *array* of dmov_s, etc structs. The last pointer
+ * in the list is marked with CMD_PTR_LP. The last struct in each array
+ * is marked with CMD_LC (see below).
+ */
+#define CMD_PTR_ADDR(addr) ((addr) >> 3)
+#define CMD_PTR_LP (1 << 31) /* last pointer */
+#define CMD_PTR_PT (3 << 29) /* ? */
+
+/* Single Item Mode */
+typedef struct {
+ unsigned cmd;
+ unsigned src;
+ unsigned dst;
+ unsigned len;
+} dmov_s;
+
+/* Scatter/Gather Mode */
+typedef struct {
+ unsigned cmd;
+ unsigned src_dscr;
+ unsigned dst_dscr;
+ unsigned _reserved;
+} dmov_sg;
+
+/* bits for the cmd field of the above structures */
+
+#define CMD_LC (1 << 31) /* last command */
+#define CMD_FR (1 << 22) /* force result -- does not work? */
+#define CMD_OCU (1 << 21) /* other channel unblock */
+#define CMD_OCB (1 << 20) /* other channel block */
+#define CMD_TCB (1 << 19) /* ? */
+#define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/
+#define CMD_SAH (1 << 17) /* source address hold -- does not work? */
+
+#define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */
+#define CMD_MODE_SG (1 << 0) /* untested */
+#define CMD_MODE_IND_SG (2 << 0) /* untested */
+#define CMD_MODE_BOX (3 << 0) /* untested */
+
+#define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */
+#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
+#define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */
+
+#define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */
+#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
+#define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */
+
+#define CMD_DST_CRCI(n) (((n) & 15) << 7)
+#define CMD_SRC_CRCI(n) (((n) & 15) << 3)
+
+#endif
diff --git a/include/asm-arm/arch-msm/entry-macro.S b/include/asm-arm/arch-msm/entry-macro.S
new file mode 100644
index 00000000000..ee24aece4cb
--- /dev/null
+++ b/include/asm-arm/arch-msm/entry-macro.S
@@ -0,0 +1,38 @@
+/* include/asm-arm/arch-msm7200/entry-macro.S
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/arch/msm_iomap.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ @ enable imprecise aborts
+ cpsie a
+ mov \base, #MSM_VIC_BASE
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ @ 0xD0 has irq# or old irq# if the irq has been handled
+ @ 0xD4 has irq# or -1 if none pending *but* if you just
+ @ read 0xD4 you never get the first irq for some reason
+ ldr \irqnr, [\base, #0xD0]
+ ldr \irqnr, [\base, #0xD4]
+ cmp \irqnr, #0xffffffff
+ .endm
diff --git a/include/asm-arm/arch-msm/hardware.h b/include/asm-arm/arch-msm/hardware.h
new file mode 100644
index 00000000000..89af2b70182
--- /dev/null
+++ b/include/asm-arm/arch-msm/hardware.h
@@ -0,0 +1,18 @@
+/* linux/include/asm-arm/arch-msm/hardware.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_HARDWARE_H
+
+#endif
diff --git a/include/asm-arm/arch-msm/io.h b/include/asm-arm/arch-msm/io.h
new file mode 100644
index 00000000000..4645ae26b62
--- /dev/null
+++ b/include/asm-arm/arch-msm/io.h
@@ -0,0 +1,33 @@
+/* include/asm-arm/arch-msm/io.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __arch_ioremap __msm_ioremap
+#define __arch_iounmap __iounmap
+
+void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
+
+static inline void __iomem *__io(unsigned long addr)
+{
+ return (void __iomem *)addr;
+}
+#define __io(a) __io(a)
+#define __mem_pci(a) (a)
+
+#endif
diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h
new file mode 100644
index 00000000000..565430cfaa7
--- /dev/null
+++ b/include/asm-arm/arch-msm/irqs.h
@@ -0,0 +1,89 @@
+/* linux/include/asm-arm/arch-msm/irqs.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_H
+
+/* MSM ARM11 Interrupt Numbers */
+/* See 80-VE113-1 A, pp219-221 */
+
+#define INT_A9_M2A_0 0
+#define INT_A9_M2A_1 1
+#define INT_A9_M2A_2 2
+#define INT_A9_M2A_3 3
+#define INT_A9_M2A_4 4
+#define INT_A9_M2A_5 5
+#define INT_A9_M2A_6 6
+#define INT_GP_TIMER_EXP 7
+#define INT_DEBUG_TIMER_EXP 8
+#define INT_UART1 9
+#define INT_UART2 10
+#define INT_UART3 11
+#define INT_UART1_RX 12
+#define INT_UART2_RX 13
+#define INT_UART3_RX 14
+#define INT_USB_OTG 15
+#define INT_MDDI_PRI 16
+#define INT_MDDI_EXT 17
+#define INT_MDDI_CLIENT 18
+#define INT_MDP 19
+#define INT_GRAPHICS 20
+#define INT_ADM_AARM 21
+#define INT_ADSP_A11 22
+#define INT_ADSP_A9_A11 23
+#define INT_SDC1_0 24
+#define INT_SDC1_1 25
+#define INT_SDC2_0 26
+#define INT_SDC2_1 27
+#define INT_KEYSENSE 28
+#define INT_TCHSCRN_SSBI 29
+#define INT_TCHSCRN1 30
+#define INT_TCHSCRN2 31
+
+#define INT_GPIO_GROUP1 (32 + 0)
+#define INT_GPIO_GROUP2 (32 + 1)
+#define INT_PWB_I2C (32 + 2)
+#define INT_SOFTRESET (32 + 3)
+#define INT_NAND_WR_ER_DONE (32 + 4)
+#define INT_NAND_OP_DONE (32 + 5)
+#define INT_PBUS_ARM11 (32 + 6)
+#define INT_AXI_MPU_SMI (32 + 7)
+#define INT_AXI_MPU_EBI1 (32 + 8)
+#define INT_AD_HSSD (32 + 9)
+#define INT_ARM11_PMU (32 + 10)
+#define INT_ARM11_DMA (32 + 11)
+#define INT_TSIF_IRQ (32 + 12)
+#define INT_UART1DM_IRQ (32 + 13)
+#define INT_UART1DM_RX (32 + 14)
+#define INT_USB_HS (32 + 15)
+#define INT_SDC3_0 (32 + 16)
+#define INT_SDC3_1 (32 + 17)
+#define INT_SDC4_0 (32 + 18)
+#define INT_SDC4_1 (32 + 19)
+#define INT_UART2DM_RX (32 + 20)
+#define INT_UART2DM_IRQ (32 + 21)
+
+/* 22-31 are reserved */
+
+#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
+
+#define NR_MSM_IRQS 64
+#define NR_GPIO_IRQS 122
+#define NR_BOARD_IRQS 64
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
+
+#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
+
+#endif
diff --git a/include/asm-arm/arch-msm/memory.h b/include/asm-arm/arch-msm/memory.h
new file mode 100644
index 00000000000..b5ce0e9ac86
--- /dev/null
+++ b/include/asm-arm/arch-msm/memory.h
@@ -0,0 +1,27 @@
+/* linux/include/asm-arm/arch-msm/memory.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/* physical offset of RAM */
+#define PHYS_OFFSET UL(0x10000000)
+
+/* bus address and physical addresses are identical */
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
+
diff --git a/include/asm-arm/arch-msm/msm_iomap.h b/include/asm-arm/arch-msm/msm_iomap.h
new file mode 100644
index 00000000000..b8955cc26fe
--- /dev/null
+++ b/include/asm-arm/arch-msm/msm_iomap.h
@@ -0,0 +1,104 @@
+/* linux/include/asm-arm/arch-msm/msm_iomap.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough. Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_H
+#define __ASM_ARCH_MSM_IOMAP_H
+
+#include <asm/sizes.h>
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * MSM_VIC_BASE must be an value that can be loaded via a "mov"
+ * instruction, otherwise entry-macro.S will not compile.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+#define MSM_VIC_BASE 0xE0000000
+#define MSM_VIC_PHYS 0xC0000000
+#define MSM_VIC_SIZE SZ_4K
+
+#define MSM_CSR_BASE 0xE0001000
+#define MSM_CSR_PHYS 0xC0100000
+#define MSM_CSR_SIZE SZ_4K
+
+#define MSM_GPT_PHYS MSM_CSR_PHYS
+#define MSM_GPT_BASE MSM_CSR_BASE
+#define MSM_GPT_SIZE SZ_4K
+
+#define MSM_DMOV_BASE 0xE0002000
+#define MSM_DMOV_PHYS 0xA9700000
+#define MSM_DMOV_SIZE SZ_4K
+
+#define MSM_UART1_BASE 0xE0003000
+#define MSM_UART1_PHYS 0xA9A00000
+#define MSM_UART1_SIZE SZ_4K
+
+#define MSM_UART2_BASE 0xE0004000
+#define MSM_UART2_PHYS 0xA9B00000
+#define MSM_UART2_SIZE SZ_4K
+
+#define MSM_UART3_BASE 0xE0005000
+#define MSM_UART3_PHYS 0xA9C00000
+#define MSM_UART3_SIZE SZ_4K
+
+#define MSM_I2C_BASE 0xE0006000
+#define MSM_I2C_PHYS 0xA9900000
+#define MSM_I2C_SIZE SZ_4K
+
+#define MSM_GPIO1_BASE 0xE0007000
+#define MSM_GPIO1_PHYS 0xA9200000
+#define MSM_GPIO1_SIZE SZ_4K
+
+#define MSM_GPIO2_BASE 0xE0008000
+#define MSM_GPIO2_PHYS 0xA9300000
+#define MSM_GPIO2_SIZE SZ_4K
+
+#define MSM_HSUSB_BASE 0xE0009000
+#define MSM_HSUSB_PHYS 0xA0800000
+#define MSM_HSUSB_SIZE SZ_4K
+
+#define MSM_CLK_CTL_BASE 0xE000A000
+#define MSM_CLK_CTL_PHYS 0xA8600000
+#define MSM_CLK_CTL_SIZE SZ_4K
+
+#define MSM_PMDH_BASE 0xE000B000
+#define MSM_PMDH_PHYS 0xAA600000
+#define MSM_PMDH_SIZE SZ_4K
+
+#define MSM_EMDH_BASE 0xE000C000
+#define MSM_EMDH_PHYS 0xAA700000
+#define MSM_EMDH_SIZE SZ_4K
+
+#define MSM_MDP_BASE 0xE0010000
+#define MSM_MDP_PHYS 0xAA200000
+#define MSM_MDP_SIZE 0x000F0000
+
+#define MSM_SHARED_RAM_BASE 0xE0100000
+#define MSM_SHARED_RAM_PHYS 0x01F00000
+#define MSM_SHARED_RAM_SIZE SZ_1M
+
+#endif
diff --git a/include/asm-arm/arch-msm/system.h b/include/asm-arm/arch-msm/system.h
new file mode 100644
index 00000000000..7c5544bdd0c
--- /dev/null
+++ b/include/asm-arm/arch-msm/system.h
@@ -0,0 +1,23 @@
+/* linux/include/asm-arm/arch-msm/system.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/hardware.h>
+
+void arch_idle(void);
+
+static inline void arch_reset(char mode)
+{
+ for (;;) ; /* depends on IPC w/ other core */
+}
diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h
new file mode 100644
index 00000000000..154b23fb359
--- /dev/null
+++ b/include/asm-arm/arch-msm/timex.h
@@ -0,0 +1,20 @@
+/* linux/include/asm-arm/arch-msm/timex.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_TIMEX_H
+
+#define CLOCK_TICK_RATE 1000000
+
+#endif
diff --git a/include/asm-arm/arch-msm/uncompress.h b/include/asm-arm/arch-msm/uncompress.h
new file mode 100644
index 00000000000..e91ed786ffe
--- /dev/null
+++ b/include/asm-arm/arch-msm/uncompress.h
@@ -0,0 +1,36 @@
+/* linux/include/asm-arm/arch-msm/uncompress.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
+
+#include "hardware.h"
+
+static void putc(int c)
+{
+}
+
+static inline void flush(void)
+{
+}
+
+static inline void arch_decomp_setup(void)
+{
+}
+
+static inline void arch_decomp_wdog(void)
+{
+}
+
+#endif
diff --git a/include/asm-arm/arch-msm/vmalloc.h b/include/asm-arm/arch-msm/vmalloc.h
new file mode 100644
index 00000000000..60f8d910e82
--- /dev/null
+++ b/include/asm-arm/arch-msm/vmalloc.h
@@ -0,0 +1,22 @@
+/* linux/include/asm-arm/arch-msm/vmalloc.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_VMALLOC_H
+#define __ASM_ARCH_MSM_VMALLOC_H
+
+#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
+
+#endif
+
diff --git a/include/asm-arm/arch-omap/tps65010.h b/include/asm-arm/arch-omap/tps65010.h
deleted file mode 100644
index b9aa2b3a390..00000000000
--- a/include/asm-arm/arch-omap/tps65010.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* linux/include/asm-arm/arch-omap/tps65010.h
- *
- * Functions to access TPS65010 power management device.
- *
- * Copyright (C) 2004 Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_TPS65010_H
-#define __ASM_ARCH_TPS65010_H
-
-/*
- * ----------------------------------------------------------------------------
- * Registers, all 8 bits
- * ----------------------------------------------------------------------------
- */
-
-#define TPS_CHGSTATUS 0x01
-# define TPS_CHG_USB (1 << 7)
-# define TPS_CHG_AC (1 << 6)
-# define TPS_CHG_THERM (1 << 5)
-# define TPS_CHG_TERM (1 << 4)
-# define TPS_CHG_TAPER_TMO (1 << 3)
-# define TPS_CHG_CHG_TMO (1 << 2)
-# define TPS_CHG_PRECHG_TMO (1 << 1)
-# define TPS_CHG_TEMP_ERR (1 << 0)
-#define TPS_REGSTATUS 0x02
-# define TPS_REG_ONOFF (1 << 7)
-# define TPS_REG_COVER (1 << 6)
-# define TPS_REG_UVLO (1 << 5)
-# define TPS_REG_NO_CHG (1 << 4) /* tps65013 */
-# define TPS_REG_PG_LD02 (1 << 3)
-# define TPS_REG_PG_LD01 (1 << 2)
-# define TPS_REG_PG_MAIN (1 << 1)
-# define TPS_REG_PG_CORE (1 << 0)
-#define TPS_MASK1 0x03
-#define TPS_MASK2 0x04
-#define TPS_ACKINT1 0x05
-#define TPS_ACKINT2 0x06
-#define TPS_CHGCONFIG 0x07
-# define TPS_CHARGE_POR (1 << 7) /* 65010/65012 */
-# define TPS65013_AUA (1 << 7) /* 65011/65013 */
-# define TPS_CHARGE_RESET (1 << 6)
-# define TPS_CHARGE_FAST (1 << 5)
-# define TPS_CHARGE_CURRENT (3 << 3)
-# define TPS_VBUS_500MA (1 << 2)
-# define TPS_VBUS_CHARGING (1 << 1)
-# define TPS_CHARGE_ENABLE (1 << 0)
-#define TPS_LED1_ON 0x08
-#define TPS_LED1_PER 0x09
-#define TPS_LED2_ON 0x0a
-#define TPS_LED2_PER 0x0b
-#define TPS_VDCDC1 0x0c
-# define TPS_ENABLE_LP (1 << 3)
-#define TPS_VDCDC2 0x0d
-#define TPS_VREGS1 0x0e
-# define TPS_LDO2_ENABLE (1 << 7)
-# define TPS_LDO2_OFF (1 << 6)
-# define TPS_VLDO2_3_0V (3 << 4)
-# define TPS_VLDO2_2_75V (2 << 4)
-# define TPS_VLDO2_2_5V (1 << 4)
-# define TPS_VLDO2_1_8V (0 << 4)
-# define TPS_LDO1_ENABLE (1 << 3)
-# define TPS_LDO1_OFF (1 << 2)
-# define TPS_VLDO1_3_0V (3 << 0)
-# define TPS_VLDO1_2_75V (2 << 0)
-# define TPS_VLDO1_2_5V (1 << 0)
-# define TPS_VLDO1_ADJ (0 << 0)
-#define TPS_MASK3 0x0f
-#define TPS_DEFGPIO 0x10
-
-/*
- * ----------------------------------------------------------------------------
- * Macros used by exported functions
- * ----------------------------------------------------------------------------
- */
-
-#define LED1 1
-#define LED2 2
-#define OFF 0
-#define ON 1
-#define BLINK 2
-#define GPIO1 1
-#define GPIO2 2
-#define GPIO3 3
-#define GPIO4 4
-#define LOW 0
-#define HIGH 1
-
-/*
- * ----------------------------------------------------------------------------
- * Exported functions
- * ----------------------------------------------------------------------------
- */
-
-/* Draw from VBUS:
- * 0 mA -- DON'T DRAW (might supply power instead)
- * 100 mA -- usb unit load (slowest charge rate)
- * 500 mA -- usb high power (fast battery charge)
- */
-extern int tps65010_set_vbus_draw(unsigned mA);
-
-/* tps65010_set_gpio_out_value parameter:
- * gpio: GPIO1, GPIO2, GPIO3 or GPIO4
- * value: LOW or HIGH
- */
-extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value);
-
-/* tps65010_set_led parameter:
- * led: LED1 or LED2
- * mode: ON, OFF or BLINK
- */
-extern int tps65010_set_led(unsigned led, unsigned mode);
-
-/* tps65010_set_vib parameter:
- * value: ON or OFF
- */
-extern int tps65010_set_vib(unsigned value);
-
-/* tps65010_set_low_pwr parameter:
- * mode: ON or OFF
- */
-extern int tps65010_set_low_pwr(unsigned mode);
-
-/* tps65010_config_vregs1 parameter:
- * value to be written to VREGS1 register
- * Note: The complete register is written, set all bits you need
- */
-extern int tps65010_config_vregs1(unsigned value);
-
-/* tps65013_set_low_pwr parameter:
- * mode: ON or OFF
- */
-extern int tps65013_set_low_pwr(unsigned mode);
-
-#endif /* __ASM_ARCH_TPS65010_H */
-
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S
new file mode 100644
index 00000000000..e2a80641f21
--- /dev/null
+++ b/include/asm-arm/arch-orion/debug-macro.S
@@ -0,0 +1,17 @@
+/*
+ * linux/include/asm-arm/arch-orion/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+ .macro addruart,rx
+ mov \rx, #0xf1000000
+ orr \rx, \rx, #0x00012000
+ .endm
+
+#define UART_SHIFT 2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion/dma.h
new file mode 100644
index 00000000000..40a8c178f10
--- /dev/null
+++ b/include/asm-arm/arch-orion/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion/entry-macro.S
new file mode 100644
index 00000000000..b76075a7e44
--- /dev/null
+++ b/include/asm-arm/arch-orion/entry-macro.S
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/arch-orion/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Orion platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/orion.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ ldr \base, =MAIN_IRQ_CAUSE
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ ldr \irqstat, [\base, #0] @ main cause
+ ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
+ mov \irqnr, #0 @ default irqnr
+ @ find cause bits that are unmasked
+ ands \irqstat, \irqstat, \tmp @ clear Z flag if any
+ clzne \irqnr, \irqstat @ calc irqnr
+ rsbne \irqnr, \irqnr, #31
+ .endm
diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion/gpio.h
new file mode 100644
index 00000000000..d66284f9a14
--- /dev/null
+++ b/include/asm-arm/arch-orion/gpio.h
@@ -0,0 +1,28 @@
+/*
+ * include/asm-arm/arch-orion/gpio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+extern int gpio_request(unsigned pin, const char *label);
+extern void gpio_free(unsigned pin);
+extern int gpio_direction_input(unsigned pin);
+extern int gpio_direction_output(unsigned pin, int value);
+extern int gpio_get_value(unsigned pin);
+extern void gpio_set_value(unsigned pin, int value);
+extern void orion_gpio_set_blink(unsigned pin, int blink);
+extern void gpio_display(void); /* debug */
+
+static inline int gpio_to_irq(int pin)
+{
+ return pin + IRQ_ORION_GPIO_START;
+}
+
+static inline int irq_to_gpio(int irq)
+{
+ return irq - IRQ_ORION_GPIO_START;
+}
+
+#include <asm-generic/gpio.h> /* cansleep wrappers */
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h
new file mode 100644
index 00000000000..8a12d213fbd
--- /dev/null
+++ b/include/asm-arm/arch-orion/hardware.h
@@ -0,0 +1,24 @@
+/*
+ * include/asm-arm/arch-orion/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#define __ASM_ARCH_HARDWARE_H__
+
+#include "orion.h"
+
+#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE
+#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
+
+#define pcibios_assign_all_busses() 1
+
+#define PCIBIOS_MIN_IO 0x1000
+#define PCIBIOS_MIN_MEM 0x01000000
+#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h
new file mode 100644
index 00000000000..e0b8c39b916
--- /dev/null
+++ b/include/asm-arm/arch-orion/io.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm-arm/arch-orion/io.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include "orion.h"
+
+#define IO_SPACE_LIMIT 0xffffffff
+#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE
+
+static inline void __iomem *__io(unsigned long addr)
+{
+ return (void __iomem *)addr;
+}
+
+#define __io(a) __io(a)
+#define __mem_pci(a) (a)
+
+#endif
diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h
new file mode 100644
index 00000000000..eea65ca6076
--- /dev/null
+++ b/include/asm-arm/arch-orion/irqs.h
@@ -0,0 +1,61 @@
+/*
+ * include/asm-arm/arch-orion/irqs.h
+ *
+ * IRQ definitions for Orion SoC
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H__
+#define __ASM_ARCH_IRQS_H__
+
+#include "orion.h" /* need GPIO_MAX */
+
+/*
+ * Orion Main Interrupt Controller
+ */
+#define IRQ_ORION_BRIDGE 0
+#define IRQ_ORION_DOORBELL_H2C 1
+#define IRQ_ORION_DOORBELL_C2H 2
+#define IRQ_ORION_UART0 3
+#define IRQ_ORION_UART1 4
+#define IRQ_ORION_I2C 5
+#define IRQ_ORION_GPIO_0_7 6
+#define IRQ_ORION_GPIO_8_15 7
+#define IRQ_ORION_GPIO_16_23 8
+#define IRQ_ORION_GPIO_24_31 9
+#define IRQ_ORION_PCIE0_ERR 10
+#define IRQ_ORION_PCIE0_INT 11
+#define IRQ_ORION_USB1_CTRL 12
+#define IRQ_ORION_DEV_BUS_ERR 14
+#define IRQ_ORION_PCI_ERR 15
+#define IRQ_ORION_USB_BR_ERR 16
+#define IRQ_ORION_USB0_CTRL 17
+#define IRQ_ORION_ETH_RX 18
+#define IRQ_ORION_ETH_TX 19
+#define IRQ_ORION_ETH_MISC 20
+#define IRQ_ORION_ETH_SUM 21
+#define IRQ_ORION_ETH_ERR 22
+#define IRQ_ORION_IDMA_ERR 23
+#define IRQ_ORION_IDMA_0 24
+#define IRQ_ORION_IDMA_1 25
+#define IRQ_ORION_IDMA_2 26
+#define IRQ_ORION_IDMA_3 27
+#define IRQ_ORION_CESA 28
+#define IRQ_ORION_SATA 29
+#define IRQ_ORION_XOR0 30
+#define IRQ_ORION_XOR1 31
+
+/*
+ * Orion General Purpose Pins
+ */
+#define IRQ_ORION_GPIO_START 32
+#define NR_GPIO_IRQS GPIO_MAX
+
+#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
+
+#endif /* __ASM_ARCH_IRQS_H__ */
diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion/memory.h
new file mode 100644
index 00000000000..d954dba87ce
--- /dev/null
+++ b/include/asm-arm/arch-orion/memory.h
@@ -0,0 +1,15 @@
+/*
+ * include/asm-arm/arch-orion/memory.h
+ *
+ * Marvell Orion memory definitions
+ */
+
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+#define PHYS_OFFSET UL(0x00000000)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
new file mode 100644
index 00000000000..f787f752e58
--- /dev/null
+++ b/include/asm-arm/arch-orion/orion.h
@@ -0,0 +1,143 @@
+/*
+ * include/asm-arm/arch-orion/orion.h
+ *
+ * Generic definitions of Orion SoC flavors:
+ * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_ORION_H__
+#define __ASM_ARCH_ORION_H__
+
+/*******************************************************************************
+ * Orion Address Map
+ * Use the same mapping (1:1 virtual:physical) of internal registers and
+ * PCI system (PCI+PCIE) for all machines.
+ * Each machine defines the rest of its mapping (e.g. device bus flashes)
+ ******************************************************************************/
+#define ORION_REGS_BASE 0xf1000000
+#define ORION_REGS_SIZE SZ_1M
+
+#define ORION_PCI_SYS_MEM_BASE 0xe0000000
+#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE
+#define ORION_PCIE_MEM_SIZE SZ_128M
+#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
+#define ORION_PCI_MEM_SIZE SZ_128M
+
+#define ORION_PCI_SYS_IO_BASE 0xf2000000
+#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
+#define ORION_PCIE_IO_SIZE SZ_1M
+#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
+#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
+#define ORION_PCI_IO_SIZE SZ_1M
+#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
+/* Relevant only for Orion-NAS */
+#define ORION_PCIE_WA_BASE 0xf0000000
+#define ORION_PCIE_WA_SIZE SZ_16M
+
+/*******************************************************************************
+ * Supported Devices & Revisions
+ ******************************************************************************/
+/* Orion-1 (88F5181) */
+#define MV88F5181_DEV_ID 0x5181
+#define MV88F5181_REV_B1 3
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID 0x5182
+#define MV88F5182_REV_A2 2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID 0x5281
+#define MV88F5281_REV_D1 5
+#define MV88F5281_REV_D2 6
+
+/*******************************************************************************
+ * Orion Registers Map
+ ******************************************************************************/
+#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000)
+#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000)
+#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000)
+#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000)
+#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000)
+#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000)
+#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000)
+#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000)
+#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000)
+
+#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x))
+#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x))
+#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x))
+#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x))
+#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x))
+#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x))
+#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x))
+#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x))
+#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x))
+
+/*******************************************************************************
+ * Device Bus Registers
+ ******************************************************************************/
+#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000)
+#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004)
+#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050)
+#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008)
+#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010)
+#define GPIO_OUT ORION_DEV_BUS_REG(0x100)
+#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104)
+#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108)
+#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c)
+#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110)
+#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114)
+#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118)
+#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c)
+#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c)
+#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460)
+#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464)
+#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c)
+#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
+#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
+#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
+#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
+#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
+#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
+#define GPIO_MAX 32
+
+/***************************************************************************
+ * Orion CPU Bridge Registers
+ **************************************************************************/
+#define CPU_CONF ORION_BRIDGE_REG(0x100)
+#define CPU_CTRL ORION_BRIDGE_REG(0x104)
+#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108)
+#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c)
+#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C)
+#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110)
+#define BRIDGE_MASK ORION_BRIDGE_REG(0x114)
+#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
+#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
+#define TIMER_CTRL ORION_BRIDGE_REG(0x300)
+#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8))
+#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8))
+
+#ifndef __ASSEMBLY__
+
+/*******************************************************************************
+ * Helpers to access Orion registers
+ ******************************************************************************/
+#include <asm/types.h>
+#include <asm/io.h>
+
+#define orion_read(r) __raw_readl(r)
+#define orion_write(r, val) __raw_writel(val, r)
+
+/*
+ * These are not preempt safe. Locks, if needed, must be taken care by caller.
+ */
+#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask))
+#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask))
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_ORION_H__ */
diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/arch-orion/platform.h
new file mode 100644
index 00000000000..143c38e2fa0
--- /dev/null
+++ b/include/asm-arm/arch-orion/platform.h
@@ -0,0 +1,25 @@
+/*
+ * asm-arm/arch-orion/platform.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_PLATFORM_H__
+#define __ASM_ARCH_PLATFORM_H__
+
+/*
+ * Device bus NAND private data
+ */
+struct orion_nand_data {
+ struct mtd_partition *parts;
+ u32 nr_parts;
+ u8 ale; /* address line number connected to ALE */
+ u8 cle; /* address line number connected to CLE */
+ u8 width; /* buswidth */
+};
+
+#endif
diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion/system.h
new file mode 100644
index 00000000000..17704c68f90
--- /dev/null
+++ b/include/asm-arm/arch-orion/system.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/arch-orion/system.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/orion.h>
+
+static inline void arch_idle(void)
+{
+ cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+ /*
+ * Enable and issue soft reset
+ */
+ orion_setbits(CPU_RESET_MASK, (1 << 2));
+ orion_setbits(CPU_SOFT_RESET, 1);
+}
+
+#endif
diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion/timex.h
new file mode 100644
index 00000000000..26c2c91eecf
--- /dev/null
+++ b/include/asm-arm/arch-orion/timex.h
@@ -0,0 +1,12 @@
+/*
+ * include/asm-arm/arch-orion/timex.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define ORION_TCLK 166666667
+#define CLOCK_TICK_RATE ORION_TCLK
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h
new file mode 100644
index 00000000000..a1a222fb438
--- /dev/null
+++ b/include/asm-arm/arch-orion/uncompress.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-arm/arch-orion/uncompress.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/orion.h>
+
+#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14))
+#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0))
+
+#define LSR_THRE 0x20
+
+static void putc(const char c)
+{
+ int j = 0x1000;
+ while (--j && !(*MV_UART_LSR & LSR_THRE))
+ barrier();
+ *MV_UART_THR = c;
+}
+
+static void flush(void)
+{
+}
+
+static void orion_early_putstr(const char *ptr)
+{
+ char c;
+ while ((c = *ptr++) != '\0') {
+ if (c == '\n')
+ putc('\r');
+ putc(c);
+ }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion/vmalloc.h
new file mode 100644
index 00000000000..23e2a102fe0
--- /dev/null
+++ b/include/asm-arm/arch-orion/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-orion/vmalloc.h
+ */
+
+#define VMALLOC_END 0xf0000000
diff --git a/include/asm-arm/arch-pxa/i2c.h b/include/asm-arm/arch-pxa/i2c.h
index e404b233d8a..80596b01344 100644
--- a/include/asm-arm/arch-pxa/i2c.h
+++ b/include/asm-arm/arch-pxa/i2c.h
@@ -65,7 +65,13 @@ struct i2c_pxa_platform_data {
unsigned int slave_addr;
struct i2c_slave_client *slave;
unsigned int class;
+ int use_pio;
};
extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
+
+#ifdef CONFIG_PXA27x
+extern void pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info);
+#endif
+
#endif
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 9c8cd9abb82..89076c32272 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -92,11 +92,9 @@
#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
#define fifo_full fifo_full_s3c2410
#define fifo_level fifo_level_s3c2410
-#warning 2410only
#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
#define fifo_full fifo_full_s3c24xx
#define fifo_level fifo_level_s3c24xx
-#warning generic
#endif
/* include the reset of the code which will do the work */
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index c6e8d8f6493..4f291d9b7d9 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -214,6 +214,7 @@ struct s3c2410_dma_chan {
unsigned long dev_addr;
unsigned long load_timeout;
unsigned int flags; /* channel flags */
+ unsigned int hw_cfg; /* last hw config */
struct s3c24xx_dma_map *map; /* channel hw maps */
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
index 6dadf58ff98..29592c3ebf2 100644
--- a/include/asm-arm/arch-s3c2410/hardware.h
+++ b/include/asm-arm/arch-s3c2410/hardware.h
@@ -50,6 +50,17 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
extern int s3c2410_gpio_getirq(unsigned int pin);
+/* s3c2410_gpio_irq2pin
+ *
+ * turn the given irq number into the corresponding GPIO number
+ *
+ * returns:
+ * < 0 = no pin
+ * >=0 = gpio pin number
+*/
+
+extern int s3c2410_gpio_irq2pin(unsigned int irq);
+
#ifdef CONFIG_CPU_S3C2400
extern int s3c2400_gpio_getirq(unsigned int pin);
@@ -87,6 +98,18 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
+/* s3c2410_gpio_getpull
+ *
+ * Read the state of the pull-up on a given pin
+ *
+ * return:
+ * < 0 => error code
+ * 0 => enabled
+ * 1 => disabled
+*/
+
+extern int s3c2410_gpio_getpull(unsigned int pin);
+
extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
@@ -99,6 +122,11 @@ extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
#endif /* CONFIG_CPU_S3C2440 */
+#ifdef CONFIG_CPU_S3C2412
+
+extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
+
+#endif /* CONFIG_CPU_S3C2412 */
#endif /* __ASSEMBLY__ */
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
index 996f65488d2..d858b3eb554 100644
--- a/include/asm-arm/arch-s3c2410/irqs.h
+++ b/include/asm-arm/arch-s3c2410/irqs.h
@@ -160,4 +160,7 @@
#define NR_IRQS (IRQ_S3C2440_AC97+1)
#endif
+/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
+#define FIQ_START IRQ_EINT0
+
#endif /* __ASM_ARCH_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index e39656b7a08..dba9df9d871 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -138,6 +138,8 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
#define S3C2412_CLKDIVN_PDIVN (1<<2)
#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
#define S3C2421_CLKDIVN_ARMDIVN (1<<3)
+#define S3C2412_CLKDIVN_DVSEN (1<<4)
+#define S3C2412_CLKDIVN_HALFHCLK (1<<5)
#define S3C2412_CLKDIVN_USB48DIV (1<<6)
#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
index c0748511edb..1235df70f34 100644
--- a/include/asm-arm/arch-s3c2410/regs-dsc.h
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -19,7 +19,7 @@
#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
#endif
-#if defined(CONFIG_CPU_S3C2440)
+#if defined(CONFIG_CPU_S3C244X)
#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index b693158b2d3..0ad75d716de 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -1133,12 +1133,16 @@
#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
-#define S3C2412_GPESLPCON S3C2410_GPIOREG(0x4C)
#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
/* definitions for each pin bit */
+#define S3C2412_GPIO_SLPCON_LOW ( 0x00 )
+#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
+#define S3C2412_GPIO_SLPCON_IN ( 0x02 )
+#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
+
#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2))
#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
index e4d82341f7b..312ff93b63c 100644
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -98,16 +98,19 @@
#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
+#define S3C2410_BANKCON_Tacp_SHIFT (2)
#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
+#define S3C2410_BANKCON_Tcah_SHIFT (4)
#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
+#define S3C2410_BANKCON_Tcoh_SHIFT (6)
#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
@@ -117,16 +120,19 @@
#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
+#define S3C2410_BANKCON_Tacc_SHIFT (8)
#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
+#define S3C2410_BANKCON_Tcos_SHIFT (11)
#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
+#define S3C2410_BANKCON_Tacs_SHIFT (13)
#define S3C2410_BANKCON_SRAM (0x0 << 15)
#define S3C2400_BANKCON_EDODRAM (0x2 << 15)
diff --git a/include/asm-arm/arch-s3c2410/regs-power.h b/include/asm-arm/arch-s3c2410/regs-power.h
index f79987be55e..13d13b7cfe9 100644
--- a/include/asm-arm/arch-s3c2410/regs-power.h
+++ b/include/asm-arm/arch-s3c2410/regs-power.h
@@ -23,7 +23,8 @@
#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
-#define S3C2412_PWRCFG_BATF_IGNORE (0<<0)
+#define S3C2412_PWRCFG_BATF_IRQ (1<<0)
+#define S3C2412_PWRCFG_BATF_IGNORE (2<<0)
#define S3C2412_PWRCFG_BATF_SLEEP (3<<0)
#define S3C2412_PWRCFG_BATF_MASK (3<<0)
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 63891786dfa..14de4e596f8 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -20,6 +20,9 @@
#include <asm/plat-s3c/regs-watchdog.h>
#include <asm/arch/regs-clock.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
void (*s3c24xx_idle)(void);
void (*s3c24xx_reset_hook)(void);
@@ -59,6 +62,8 @@ static void arch_idle(void)
static void
arch_reset(char mode)
{
+ struct clk *wdtclk;
+
if (mode == 's') {
cpu_reset(0);
}
@@ -70,19 +75,28 @@ arch_reset(char mode)
__raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
+ wdtclk = clk_get(NULL, "watchdog");
+ if (!IS_ERR(wdtclk)) {
+ clk_enable(wdtclk);
+ } else
+ printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
+
/* put initial values into count and data */
- __raw_writel(0x100, S3C2410_WTCNT);
- __raw_writel(0x100, S3C2410_WTDAT);
+ __raw_writel(0x80, S3C2410_WTCNT);
+ __raw_writel(0x80, S3C2410_WTDAT);
/* set the watchdog to go and reset... */
__raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
/* wait for reset to assert... */
- mdelay(5000);
+ mdelay(500);
printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+ /* delay to allow the serial port to show the message */
+ mdelay(50);
+
/* we'll take a jump through zero as a poor second */
cpu_reset(0);
}
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 6c1c968b298..759a97b56ee 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -94,6 +94,14 @@
# endif
#endif
+#if defined(CONFIG_CPU_FEROCEON)
+# ifdef _CACHE
+# define MULTI_CACHE 1
+# else
+# define _CACHE feroceon
+# endif
+#endif
+
#if defined(CONFIG_CPU_V6)
//# ifdef _CACHE
# define MULTI_CACHE 1
diff --git a/include/asm-arm/fpstate.h b/include/asm-arm/fpstate.h
index f31cda5a55e..392eb533232 100644
--- a/include/asm-arm/fpstate.h
+++ b/include/asm-arm/fpstate.h
@@ -17,14 +17,18 @@
/*
* VFP storage area has:
* - FPEXC, FPSCR, FPINST and FPINST2.
- * - 16 double precision data registers
- * - an implementation-dependant word of state for FLDMX/FSTMX
+ * - 16 or 32 double precision data registers
+ * - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6)
*
* FPEXC will always be non-zero once the VFP has been used in this process.
*/
struct vfp_hard_struct {
+#ifdef CONFIG_VFPv3
+ __u64 fpregs[32];
+#else
__u64 fpregs[16];
+#endif
#if __LINUX_ARM_ARCH__ < 6
__u32 fpmx_state;
#endif
@@ -35,6 +39,7 @@ struct vfp_hard_struct {
*/
__u32 fpinst;
__u32 fpinst2;
+
#ifdef CONFIG_SMP
__u32 cpu;
#endif
diff --git a/include/asm-arm/kprobes.h b/include/asm-arm/kprobes.h
new file mode 100644
index 00000000000..4e7bd32288a
--- /dev/null
+++ b/include/asm-arm/kprobes.h
@@ -0,0 +1,79 @@
+/*
+ * include/asm-arm/kprobes.h
+ *
+ * Copyright (C) 2006, 2007 Motorola Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef _ARM_KPROBES_H
+#define _ARM_KPROBES_H
+
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/percpu.h>
+
+#define ARCH_SUPPORTS_KRETPROBES
+#define __ARCH_WANT_KPROBES_INSN_SLOT
+#define MAX_INSN_SIZE 2
+#define MAX_STACK_SIZE 64 /* 32 would probably be OK */
+
+/*
+ * This undefined instruction must be unique and
+ * reserved solely for kprobes' use.
+ */
+#define KPROBE_BREAKPOINT_INSTRUCTION 0xe7f001f8
+
+#define regs_return_value(regs) ((regs)->ARM_r0)
+#define flush_insn_slot(p) do { } while (0)
+#define kretprobe_blacklist_size 0
+
+typedef u32 kprobe_opcode_t;
+
+struct kprobe;
+typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *);
+
+/* Architecture specific copy of original instruction. */
+struct arch_specific_insn {
+ kprobe_opcode_t *insn;
+ kprobe_insn_handler_t *insn_handler;
+};
+
+struct prev_kprobe {
+ struct kprobe *kp;
+ unsigned int status;
+};
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+ unsigned int kprobe_status;
+ struct prev_kprobe prev_kprobe;
+ struct pt_regs jprobe_saved_regs;
+ char jprobes_stack[MAX_STACK_SIZE];
+};
+
+void arch_remove_kprobe(struct kprobe *);
+
+int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr);
+int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr);
+int kprobe_exceptions_notify(struct notifier_block *self,
+ unsigned long val, void *data);
+
+enum kprobe_insn {
+ INSN_REJECTED,
+ INSN_GOOD,
+ INSN_GOOD_NO_SLOT
+};
+
+enum kprobe_insn arm_kprobe_decode_insn(kprobe_opcode_t,
+ struct arch_specific_insn *);
+void __init arm_kprobe_decode_init(void);
+
+#endif /* _ARM_KPROBES_H */
diff --git a/include/asm-arm/plat-s3c24xx/dma.h b/include/asm-arm/plat-s3c24xx/dma.h
index 2c59406435e..c78efe316fc 100644
--- a/include/asm-arm/plat-s3c24xx/dma.h
+++ b/include/asm-arm/plat-s3c24xx/dma.h
@@ -32,6 +32,7 @@ struct s3c24xx_dma_map {
struct s3c24xx_dma_addr hw_addr;
unsigned long channels[S3C2410_DMA_CHANNELS];
+ unsigned long channels_rx[S3C2410_DMA_CHANNELS];
};
struct s3c24xx_dma_selection {
@@ -41,6 +42,10 @@ struct s3c24xx_dma_selection {
void (*select)(struct s3c2410_dma_chan *chan,
struct s3c24xx_dma_map *map);
+
+ void (*direction)(struct s3c2410_dma_chan *chan,
+ struct s3c24xx_dma_map *map,
+ enum s3c2410_dmasrc dir);
};
extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
diff --git a/include/asm-arm/plat-s3c24xx/irq.h b/include/asm-arm/plat-s3c24xx/irq.h
index 8af6d9579b3..45746a99534 100644
--- a/include/asm-arm/plat-s3c24xx/irq.h
+++ b/include/asm-arm/plat-s3c24xx/irq.h
@@ -15,7 +15,9 @@
#define EXTINT_OFF (IRQ_EINT4 - 4)
+/* these are exported for arch/arm/mach-* usage */
extern struct irq_chip s3c_irq_level_chip;
+extern struct irq_chip s3c_irq_chip;
static inline void
s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
diff --git a/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h b/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
new file mode 100644
index 00000000000..25d4058bcfe
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
@@ -0,0 +1,72 @@
+/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
+ *
+ * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2412 IIS register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
+#define __ASM_ARCH_REGS_S3C2412_IIS_H
+
+#define S3C2412_IISCON (0x00)
+#define S3C2412_IISMOD (0x04)
+#define S3C2412_IISFIC (0x08)
+#define S3C2412_IISPSR (0x0C)
+#define S3C2412_IISTXD (0x10)
+#define S3C2412_IISRXD (0x14)
+
+#define S3C2412_IISCON_LRINDEX (1 << 11)
+#define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10)
+#define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9)
+#define S3C2412_IISCON_TXFIFO_FULL (1 << 8)
+#define S3C2412_IISCON_RXFIFO_FULL (1 << 7)
+#define S3C2412_IISCON_TXDMA_PAUSE (1 << 6)
+#define S3C2412_IISCON_RXDMA_PAUSE (1 << 5)
+#define S3C2412_IISCON_TXCH_PAUSE (1 << 4)
+#define S3C2412_IISCON_RXCH_PAUSE (1 << 3)
+#define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2)
+#define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1)
+#define S3C2412_IISCON_IIS_ACTIVE (1 << 0)
+
+#define S3C2412_IISMOD_MASTER_INTERNAL (0 << 10)
+#define S3C2412_IISMOD_MASTER_EXTERNAL (1 << 10)
+#define S3C2412_IISMOD_SLAVE (2 << 10)
+#define S3C2412_IISMOD_MASTER_MASK (3 << 10)
+#define S3C2412_IISMOD_MODE_TXONLY (0 << 8)
+#define S3C2412_IISMOD_MODE_RXONLY (1 << 8)
+#define S3C2412_IISMOD_MODE_TXRX (2 << 8)
+#define S3C2412_IISMOD_MODE_MASK (3 << 8)
+#define S3C2412_IISMOD_LR_LLOW (0 << 7)
+#define S3C2412_IISMOD_LR_RLOW (1 << 7)
+#define S3C2412_IISMOD_SDF_IIS (0 << 5)
+#define S3C2412_IISMOD_SDF_MSB (0 << 5)
+#define S3C2412_IISMOD_SDF_LSB (0 << 5)
+#define S3C2412_IISMOD_SDF_MASK (3 << 5)
+#define S3C2412_IISMOD_RCLK_256FS (0 << 3)
+#define S3C2412_IISMOD_RCLK_512FS (1 << 3)
+#define S3C2412_IISMOD_RCLK_384FS (2 << 3)
+#define S3C2412_IISMOD_RCLK_768FS (3 << 3)
+#define S3C2412_IISMOD_RCLK_MASK (3 << 3)
+#define S3C2412_IISMOD_BCLK_32FS (0 << 1)
+#define S3C2412_IISMOD_BCLK_48FS (1 << 1)
+#define S3C2412_IISMOD_BCLK_16FS (2 << 1)
+#define S3C2412_IISMOD_BCLK_24FS (3 << 1)
+#define S3C2412_IISMOD_BCLK_MASK (3 << 1)
+#define S3C2412_IISMOD_8BIT (1 << 0)
+
+#define S3C2412_IISPSR_PSREN (1 << 15)
+
+#define S3C2412_IISFIC_TXFLUSH (1 << 15)
+#define S3C2412_IISFIC_RXFLUSH (1 << 7)
+#define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf)
+#define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf)
+
+
+
+#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
+
diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h
index 4a499a13825..ea565b007d0 100644
--- a/include/asm-arm/plat-s3c24xx/regs-spi.h
+++ b/include/asm-arm/plat-s3c24xx/regs-spi.h
@@ -17,6 +17,21 @@
#define S3C2410_SPCON (0x00)
+#define S3C2412_SPCON_RXFIFO_RB2 (0<<14)
+#define S3C2412_SPCON_RXFIFO_RB4 (1<<14)
+#define S3C2412_SPCON_RXFIFO_RB12 (2<<14)
+#define S3C2412_SPCON_RXFIFO_RB14 (3<<14)
+#define S3C2412_SPCON_TXFIFO_RB2 (0<<12)
+#define S3C2412_SPCON_TXFIFO_RB4 (1<<12)
+#define S3C2412_SPCON_TXFIFO_RB12 (2<<12)
+#define S3C2412_SPCON_TXFIFO_RB14 (3<<12)
+#define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */
+#define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */
+#define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */
+#define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */
+
+#define S3C2412_SPCON_DIRC_RX (1<<7)
+
#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
@@ -34,10 +49,19 @@
#define S3C2410_SPSTA (0x04)
+#define S3C2412_SPSTA_RXFIFO_AE (1<<11)
+#define S3C2412_SPSTA_TXFIFO_AE (1<<10)
+#define S3C2412_SPSTA_RXFIFO_ERROR (1<<9)
+#define S3C2412_SPSTA_TXFIFO_ERROR (1<<8)
+#define S3C2412_SPSTA_RXFIFO_FIFO (1<<7)
+#define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6)
+#define S3C2412_SPSTA_TXFIFO_NFULL (1<<5)
+#define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4)
+
#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
-
+#define S3C2412_SPSTA_READY_ORG (1<<3)
#define S3C2410_SPPIN (0x08)
@@ -46,9 +70,13 @@
#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
-
#define S3C2410_SPPRE (0x0C)
#define S3C2410_SPTDAT (0x10)
#define S3C2410_SPRDAT (0x14)
+#define S3C2412_TXFIFO (0x18)
+#define S3C2412_RXFIFO (0x18)
+#define S3C2412_SPFIC (0x24)
+
+
#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index 5599d4e5e70..a4ce457199d 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -185,6 +185,14 @@
# define CPU_NAME cpu_xsc3
# endif
# endif
+# ifdef CONFIG_CPU_FEROCEON
+# ifdef CPU_NAME
+# undef MULTI_CPU
+# define MULTI_CPU
+# else
+# define CPU_NAME cpu_feroceon
+# endif
+# endif
# ifdef CONFIG_CPU_V6
# ifdef CPU_NAME
# undef MULTI_CPU
diff --git a/include/asm-arm/traps.h b/include/asm-arm/traps.h
index d4f34dc83eb..f1541afcf85 100644
--- a/include/asm-arm/traps.h
+++ b/include/asm-arm/traps.h
@@ -15,4 +15,13 @@ struct undef_hook {
void register_undef_hook(struct undef_hook *hook);
void unregister_undef_hook(struct undef_hook *hook);
+static inline int in_exception_text(unsigned long ptr)
+{
+ extern char __exception_text_start[];
+ extern char __exception_text_end[];
+
+ return ptr >= (unsigned long)&__exception_text_start &&
+ ptr < (unsigned long)&__exception_text_end;
+}
+
#endif
diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h
index bd6be9d7f77..5f9a2cb3d45 100644
--- a/include/asm-arm/vfp.h
+++ b/include/asm-arm/vfp.h
@@ -7,7 +7,11 @@
#define FPSID cr0
#define FPSCR cr1
+#define MVFR1 cr6
+#define MVFR0 cr7
#define FPEXC cr8
+#define FPINST cr9
+#define FPINST2 cr10
/* FPSID bits */
#define FPSID_IMPLEMENTER_BIT (24)
@@ -28,6 +32,19 @@
/* FPEXC bits */
#define FPEXC_EX (1 << 31)
#define FPEXC_EN (1 << 30)
+#define FPEXC_DEX (1 << 29)
+#define FPEXC_FP2V (1 << 28)
+#define FPEXC_VV (1 << 27)
+#define FPEXC_TFV (1 << 26)
+#define FPEXC_LENGTH_BIT (8)
+#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
+#define FPEXC_IDF (1 << 7)
+#define FPEXC_IXF (1 << 4)
+#define FPEXC_UFF (1 << 3)
+#define FPEXC_OFF (1 << 2)
+#define FPEXC_DZF (1 << 1)
+#define FPEXC_IOF (1 << 0)
+#define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
/* FPSCR bits */
#define FPSCR_DEFAULT_NAN (1<<25)
@@ -55,20 +72,9 @@
#define FPSCR_IXC (1<<4)
#define FPSCR_IDC (1<<7)
-/*
- * VFP9-S specific.
- */
-#define FPINST cr9
-#define FPINST2 cr10
-
-/* FPEXC bits */
-#define FPEXC_FPV2 (1<<28)
-#define FPEXC_LENGTH_BIT (8)
-#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
-#define FPEXC_INV (1 << 7)
-#define FPEXC_UFC (1 << 3)
-#define FPEXC_OFC (1 << 2)
-#define FPEXC_IOC (1 << 0)
+/* MVFR0 bits */
+#define MVFR0_A_SIMD_BIT (0)
+#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT)
/* Bit patterns for decoding the packaged operation descriptors */
#define VFPOPDESC_LENGTH_BIT (9)
diff --git a/include/asm-arm/vfpmacros.h b/include/asm-arm/vfpmacros.h
index 27fe028b4e7..cccb3892e73 100644
--- a/include/asm-arm/vfpmacros.h
+++ b/include/asm-arm/vfpmacros.h
@@ -15,19 +15,33 @@
.endm
@ read all the working registers back into the VFP
- .macro VFPFLDMIA, base
+ .macro VFPFLDMIA, base, tmp
#if __LINUX_ARM_ARCH__ < 6
LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15}
#else
LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
#endif
+#ifdef CONFIG_VFPv3
+ VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
+ and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
+ cmp \tmp, #2 @ 32 x 64bit registers?
+ ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
+ addne \base, \base, #32*4 @ step over unused register space
+#endif
.endm
@ write all the working registers out of the VFP
- .macro VFPFSTMIA, base
+ .macro VFPFSTMIA, base, tmp
#if __LINUX_ARM_ARCH__ < 6
STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
#else
STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
#endif
+#ifdef CONFIG_VFPv3
+ VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
+ and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
+ cmp \tmp, #2 @ 32 x 64bit registers?
+ stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
+ addne \base, \base, #32*4 @ step over unused register space
+#endif
.endm