diff options
Diffstat (limited to 'include/asm-arm')
39 files changed, 1529 insertions, 385 deletions
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h index 24b51cccde8..9eceb414892 100644 --- a/include/asm-arm/arch-aaec2000/memory.h +++ b/include/asm-arm/arch-aaec2000/memory.h @@ -17,8 +17,6 @@ #define __virt_to_bus(x) __virt_to_phys(x) #define __bus_to_virt(x) __phys_to_virt(x) -#ifdef CONFIG_DISCONTIGMEM - /* * The nodes are the followings: * @@ -27,42 +25,6 @@ * node 2: 0xf800.0000 - 0xfbff.ffff * node 3: 0xfc00.0000 - 0xffff.ffff */ - -/* - * Given a kernel address, find the home node of the underlying memory. - */ -#define KVADDR_TO_NID(addr) \ - (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT) - -/* - * Given a page frame number, convert it to a node id. - */ -#define PFN_TO_NID(pfn) \ - (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT)) - -/* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and return the mem_map of that node. - */ -#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) - -/* - * Given a page frame number, find the owning node of the memory - * and return the mem_map of that node. - */ -#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) - -/* - * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory - * and returns the index corresponding to the appropriate page in the - * node's mem_map. - */ -#define LOCAL_MAP_NR(addr) \ - (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT) - -#define NODE_MAX_MEM_SHIFT 26 -#define NODE_MAX_MEM_SIZE (1 << NODE_MAX_MEM_SHIFT) - -#endif /* CONFIG_DISCONTIGMEM */ +#define NODE_MEM_SIZE_BITS 26 #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h index c6e8dcf674d..42768cc8bfb 100644 --- a/include/asm-arm/arch-clps711x/memory.h +++ b/include/asm-arm/arch-clps711x/memory.h @@ -62,7 +62,15 @@ * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM. */ -#ifdef CONFIG_DISCONTIGMEM +/* + * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 + * uses only one of the two banks (bank #1). However, even within + * bank #1, memory is discontiguous. + * + * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between + * them, so we use 24 for the node max shift to get 16MB node sizes. + */ + /* * Because of the wide memory address space between physical RAM banks on the * SA1100, it's much more convenient to use Linux's NUMA support to implement @@ -80,48 +88,7 @@ * node 2: 0xd0000000 - 0xd7ffffff * node 3: 0xd8000000 - 0xdfffffff */ - -/* - * Given a kernel address, find the home node of the underlying memory. - */ -#define KVADDR_TO_NID(addr) \ - (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT) - -/* - * Given a page frame number, convert it to a node id. - */ -#define PFN_TO_NID(pfn) \ - (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT)) - -/* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and returns the mem_map of that node. - */ -#define ADDR_TO_MAPBASE(kaddr) \ - NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr))) - -#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) - -/* - * Given a kaddr, LOCAL_MAR_NR finds the owning node of the memory - * and returns the index corresponding to the appropriate page in the - * node's mem_map. - */ -#define LOCAL_MAP_NR(addr) \ - (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT) - -/* - * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 - * uses only one of the two banks (bank #1). However, even within - * bank #1, memory is discontiguous. - * - * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between - * them, so we use 24 for the node max shift to get 16MB node sizes. - */ -#define NODE_MAX_MEM_SHIFT 24 -#define NODE_MAX_MEM_SIZE (1<<NODE_MAX_MEM_SHIFT) - -#endif /* CONFIG_DISCONTIGMEM */ +#define NODE_MEM_SIZE_BITS 24 #endif diff --git a/include/asm-arm/arch-imx/timex.h b/include/asm-arm/arch-imx/timex.h index 8c91674706b..e22ba789546 100644 --- a/include/asm-arm/arch-imx/timex.h +++ b/include/asm-arm/arch-imx/timex.h @@ -21,7 +21,6 @@ #ifndef __ASM_ARCH_TIMEX_H #define __ASM_ARCH_TIMEX_H -#include <asm/hardware.h> -#define CLOCK_TICK_RATE (CLK32) +#define CLOCK_TICK_RATE (16000000) #endif diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S new file mode 100644 index 00000000000..788b4e386c1 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/debug-macro.S @@ -0,0 +1,26 @@ +/* + * include/asm-arm/arch-iop13xx/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ mmu enabled? + moveq \rx, #0xff000000 @ physical + orreq \rx, \rx, #0x00d80000 + movne \rx, #0xfe000000 @ virtual + orrne \rx, \rx, #0x00e80000 + orr \rx, \rx, #0x00002300 + orr \rx, \rx, #0x00000040 + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h new file mode 100644 index 00000000000..2e15da53ff7 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/dma.h @@ -0,0 +1,3 @@ +#ifndef _IOP13XX_DMA_H +#define _IOP13XX_DMA_H_ +#endif diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S new file mode 100644 index 00000000000..94c50283dc5 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/entry-macro.S @@ -0,0 +1,39 @@ +/* + * iop13xx low level irq macros + * Copyright (c) 2005-2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place - Suite 330, Boston, MA 02111-1307 USA. + * + */ + .macro disable_fiq + .endm + + /* + * Note: a 1-cycle window exists where iintvec will return the value + * of iintbase, so we explicitly check for "bad zeros" + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mrc p15, 0, \tmp, c15, c1, 0 + orr \tmp, \tmp, #(1 << 6) + mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access + + mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC + cmp \irqnr, #0 + mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero + adds \irqstat, \irqnr, #1 @ Check for 0xffffffff + movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr + + biceq \tmp, \tmp, #(1 << 6) + mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts + .endm diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/include/asm-arm/arch-iop13xx/hardware.h new file mode 100644 index 00000000000..8e1d5628984 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/hardware.h @@ -0,0 +1,28 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H +#include <asm/types.h> + +#define pcibios_assign_all_busses() 1 + +#ifndef __ASSEMBLY__ +extern unsigned long iop13xx_pcibios_min_io; +extern unsigned long iop13xx_pcibios_min_mem; +extern u16 iop13xx_dev_id(void); +extern void iop13xx_set_atu_mmr_bases(void); +#endif + +#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io) +#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem) + +/* + * Generic chipset bits + * + */ +#include "iop13xx.h" + +/* + * Board specific bits + */ +#include "iq81340.h" + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h new file mode 100644 index 00000000000..db6de2480a2 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/io.h @@ -0,0 +1,41 @@ +/* + * iop13xx custom ioremap implementation + * Copyright (c) 2005-2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place - Suite 330, Boston, MA 02111-1307 USA. + * + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) (a) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +extern void __iomem * __ioremap(unsigned long, size_t, unsigned long); +extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, + unsigned long flags); +extern void __iop13xx_iounmap(void __iomem *addr); + +extern u32 iop13xx_atue_mem_base; +extern u32 iop13xx_atux_mem_base; +extern size_t iop13xx_atue_mem_size; +extern size_t iop13xx_atux_mem_size; + +#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f) +#define __arch_iounmap(a) __iop13xx_iounmap(a) + +#endif diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h new file mode 100644 index 00000000000..a88522a0ff8 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -0,0 +1,492 @@ +#ifndef _IOP13XX_HW_H_ +#define _IOP13XX_HW_H_ + +#ifndef __ASSEMBLY__ +/* The ATU offsets can change based on the strapping */ +extern u32 iop13xx_atux_pmmr_offset; +extern u32 iop13xx_atue_pmmr_offset; +void iop13xx_init_irq(void); +void iop13xx_map_io(void); +void iop13xx_platform_init(void); +void iop13xx_init_irq(void); +void iop13xx_init_time(unsigned long tickrate); +unsigned long iop13xx_gettimeoffset(void); + +/* handle cp6 access + * to do: handle access in entry-armv5.S and unify with + * the iop3xx implementation + * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h) + * when interrupts are enabled + */ +static inline unsigned long iop13xx_cp6_save(void) +{ + u32 temp, cp_flags; + + asm volatile ( + "mrc p15, 0, %1, c15, c1, 0\n\t" + "orr %0, %1, #(1 << 6)\n\t" + "mcr p15, 0, %0, c15, c1, 0\n\t" + : "=r" (temp), "=r"(cp_flags)); + + return cp_flags; +} + +static inline void iop13xx_cp6_restore(unsigned long cp_flags) +{ + asm volatile ( + "mcr p15, 0, %0, c15, c1, 0\n\t" + : : "r" (cp_flags) ); +} + +/* CPUID CP6 R0 Page 0 */ +static inline int iop13xx_cpu_id(void) +{ + int id; + asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id)); + return id; +} + +#endif + +/* + * IOP13XX I/O and Mem space regions for PCI autoconfiguration + */ +#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */ +#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE + +/* PCI MAP + * 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM + * 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB) +*/ +#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL +#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL +#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL +#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL +#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\ + IOP13XX_PCIX_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\ + IOP13XX_PCIX_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\ + IOP13XX_PCIX_LOWER_IO_BA) +#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ + (IOP13XX_PCIX_LOWER_IO_PA\ + - IOP13XX_PCIX_LOWER_IO_VA)) + +#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL +#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL +#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) +#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\ + IOP13XX_PCIX_LOWER_MEM_BA) +#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\ + IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\ + IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) + +#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL +#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE +#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\ + IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\ + IOP13XX_PCIX_LOWER_MEM_BA) + +/* PCI-E ranges */ +#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL +#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL +#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL +#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL +#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\ + IOP13XX_PCIE_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\ + IOP13XX_PCIE_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\ + IOP13XX_PCIE_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\ + IOP13XX_PCIE_LOWER_IO_BA) +#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ + (IOP13XX_PCIE_LOWER_IO_PA\ + - IOP13XX_PCIE_LOWER_IO_VA)) + +#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL +#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL +#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) +#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\ + IOP13XX_PCIE_LOWER_MEM_BA) +#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\ + IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\ + IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) + +/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */ +#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL +#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE +#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\ + IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\ + IOP13XX_PCIE_LOWER_MEM_BA) + +/* PBI Ranges */ +#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL +#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL +#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL +#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE +#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\ + IOP13XX_PBI_MEM_WINDOW_SIZE - 1) + +/* + * IOP13XX chipset registers + */ +#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ +#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */ +#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 +#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ + IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ + IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\ + (IOP13XX_PMMR_PHYS_MEM_BASE\ + - IOP13XX_PMMR_VIRT_MEM_BASE)) +#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ + (IOP13XX_PMMR_PHYS_MEM_BASE\ + - IOP13XX_PMMR_VIRT_MEM_BASE)) +#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) +#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) +#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) +#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) +#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) +#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) +#define IOP13XX_PMMR_SIZE 0x00080000 + +/*=================== Defines for Platform Devices =====================*/ +#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300) +#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340) +#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300) +#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340) + +#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) +#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) +#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540) +#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500) +#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520) +#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540) + +/* ATU selection flags */ +/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */ +#define IOP13XX_INIT_ATU_DEFAULT (0) +#define IOP13XX_INIT_ATU_ATUX (1 << 0) +#define IOP13XX_INIT_ATU_ATUE (1 << 1) +#define IOP13XX_INIT_ATU_NONE (1 << 2) + +/* UART selection flags */ +/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */ +#define IOP13XX_INIT_UART_DEFAULT (0) +#define IOP13XX_INIT_UART_0 (1 << 0) +#define IOP13XX_INIT_UART_1 (1 << 1) + +/* I2C selection flags */ +/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */ +#define IOP13XX_INIT_I2C_DEFAULT (0) +#define IOP13XX_INIT_I2C_0 (1 << 0) +#define IOP13XX_INIT_I2C_1 (1 << 1) +#define IOP13XX_INIT_I2C_2 (1 << 2) + +#define IQ81340_NUM_UART 2 +#define IQ81340_NUM_I2C 3 +#define IQ81340_NUM_PHYS_MAP_FLASH 1 +#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\ + IQ81340_NUM_I2C +\ + IQ81340_NUM_PHYS_MAP_FLASH) + +/*========================== PMMR offsets for key registers ============*/ +#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000 +#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000 +#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000 +#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000 +#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 +#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 +#define IOP13XX_PBI_PMMR_OFFSET 0x00001580 +#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 +#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) + +#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */ +#define IOP13XX_CONTROLLER_ONLY (1 << 14) +#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15) + +#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000 +#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\ + IOP13XX_PMON_PMMR_OFFSET) +#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\ + IOP13XX_PMON_PMMR_OFFSET) + +#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0) +#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4) +#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8) +#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC) + +#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30) +#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34) +#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38) +#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C) + +#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70) +#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74) +#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78) +#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C) + +#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040) +#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044) + +/*================================ATU===================================*/ +#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\ + iop13xx_atux_pmmr_offset + (ofs)) + +#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\ + iop13xx_atux_pmmr_offset + 0x2) + +#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\ + iop13xx_atux_pmmr_offset + 0x4) +#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\ + iop13xx_atux_pmmr_offset + 0x6) + +#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10) +#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14) +#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18) +#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c) +#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20) +#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24) +#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40) +#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44) +#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48) +#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c) +#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50) +#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54) +#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58) +#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c) +#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60) +#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70) +#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74) +#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78) +#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4) +#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200) +#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204) +#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208) +#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c) +#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210) + +#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300) +#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304) +#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308) +#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c) +#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310) +#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314) +#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318) +#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c) +#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320) +#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324) +#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328) +#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c) +#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330) +#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334) + +#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1) +#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25) +#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21) +#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15) +#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14) +#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16) + +#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18) +#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17) +#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16) +#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15) +#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14) +#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13) +#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12) +#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11) +#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10) +#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 ) +#define IOP13XX_ATUX_STAT_BIST (1 << 8 ) +#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 ) +#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 ) +#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 ) +#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 ) +#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 ) +#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 ) + +#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8) +#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3) +#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0) + +#define IOP13XX_ATUX_IALR_DISABLE 0x00000001 +#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000 + +#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\ + iop13xx_atue_pmmr_offset + (ofs)) + +#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\ + iop13xx_atue_pmmr_offset + 0x2) +#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\ + iop13xx_atue_pmmr_offset + 0x4) +#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\ + iop13xx_atue_pmmr_offset + 0x6) + +#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10) +#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14) +#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18) +#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c) +#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20) +#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24) +#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40) +#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44) +#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48) +#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c) +#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50) +#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54) +#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58) +#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c) +#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60) +#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\ + iop13xx_atue_pmmr_offset + 0xe2) +#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304) +#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308) +#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c) +#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310) +#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314) +#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318) +#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c) +#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320) +#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324) + +#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70) +#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74) +#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78) +#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300) +#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c) +#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330) + +#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384) +#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388) + +#define IOP13XX_ATUE_ATUCR_IVM (1 << 6) +#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1) +#define IOP13XX_ATUE_OCCAR_BUS_NUM (24) +#define IOP13XX_ATUE_OCCAR_DEV_NUM (19) +#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16) +#define IOP13XX_ATUE_OCCAR_EXT_REG (8) +#define IOP13XX_ATUE_OCCAR_REG (2) + +#define IOP13XX_ATUE_PCSR_BUS_NUM (24) +#define IOP13XX_ATUE_PCSR_DEV_NUM (19) +#define IOP13XX_ATUE_PCSR_FUNC_NUM (16) +#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15) +#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14) +#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13) +#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12) + +#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff) +#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f) +#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7) + +#define IOP13XX_ATUE_PCSR_CORE_RESET (8) +#define IOP13XX_ATUE_PCSR_FUNC_NUM (16) + +#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11) +#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28) +#define IOP13XX_ATUE_STAT_PME (1 << 27) +#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26) +#define IOP13XX_ATUE_STAT_IVM (1 << 25) +#define IOP13XX_ATUE_STAT_BIST (1 << 24) +#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18) +#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17) +#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16) +#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13) +#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12) +#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11) +#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10) +#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 ) +#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 ) +#define IOP13XX_ATUE_STAT_CRS (1 << 7 ) +#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 ) +#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 ) +#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 ) +#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 ) +#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 ) +#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 ) +#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 ) + +#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31) +#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30) +#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29) +#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28) +#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20) +#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19) +#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18) +#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17) +#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16) +#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15) +#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14) +#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13) +#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12) +#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 ) +#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 ) + +#define IOP13XX_ATUE_IALR_DISABLE (0x00000001) +#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000) +#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28) +#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) +/*=======================================================================*/ + +/*==============================ADMA UNITS===============================*/ +#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) +#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) +#define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs)) + +#define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0) +#define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4) +#define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8) +#define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18) +#define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c) +#define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20) +#define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24) +#define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28) +#define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c) +#define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30) +#define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34) +#define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38) +#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3)) +#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3)) + +/*==============================XSI BRIDGE===============================*/ +#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c) +#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790) +#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794) +#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ + IOP13XX_PMMR_VIRT_TO_PHYS(\ + IOP13XX_ATUE_OCCDR))\ + && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) +#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ + IOP13XX_PMMR_VIRT_TO_PHYS(\ + IOP13XX_ATUX_OCCDR))\ + && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) +/*=======================================================================*/ + +#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\ + (ofs)) + +#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0) +#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4) +#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8) +#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc) +#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) +#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) + +#define IOP13XX_TMR_TC 0x01 +#define IOP13XX_TMR_EN 0x02 +#define IOP13XX_TMR_RELOAD 0x04 +#define IOP13XX_TMR_PRIVILEGED 0x08 + +#define IOP13XX_TMR_RATIO_1_1 0x00 +#define IOP13XX_TMR_RATIO_4_1 0x10 +#define IOP13XX_TMR_RATIO_8_1 0x20 +#define IOP13XX_TMR_RATIO_16_1 0x30 + +#endif /* _IOP13XX_HW_H_ */ diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/include/asm-arm/arch-iop13xx/iq81340.h new file mode 100644 index 00000000000..b98f8f109c2 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/iq81340.h @@ -0,0 +1,31 @@ +#ifndef _IQ81340_H_ +#define _IQ81340_H_ + +#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA +#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000) + +#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */ + +#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a)) + +#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0) +#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000) +#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000) +#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000) +#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000) +#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000) +#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000) +#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000) +#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000) +#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000) +#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000) +#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */ + +#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH) +#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1) + +/* These are the values used in the Machine description */ +#define PHYS_IO 0xfeffff00 +#define IO_PG_OFFSET 0xffffff00 +#define BOOT_PARAM_OFFSET 0x00000100 +#endif /* _IQ81340_H_ */ diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h new file mode 100644 index 00000000000..442e35a4035 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/irqs.h @@ -0,0 +1,207 @@ +#ifndef _IOP13XX_IRQS_H_ +#define _IOP13XX_IRQS_H_ + +#ifndef __ASSEMBLER__ +#include <linux/types.h> +#include <asm/system.h> /* local_irq_save */ +#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */ + +/* INTPND0 CP6 R0 Page 3 + */ +static inline u32 read_intpnd_0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val)); + return val; +} + +/* INTPND1 CP6 R1 Page 3 + */ +static inline u32 read_intpnd_1(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val)); + return val; +} + +/* INTPND2 CP6 R2 Page 3 + */ +static inline u32 read_intpnd_2(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val)); + return val; +} + +/* INTPND3 CP6 R3 Page 3 + */ +static inline u32 read_intpnd_3(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); + return val; +} + +static inline void +iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags) +{ + local_irq_save(*irq_flags); + *cp_flags = iop13xx_cp6_save(); +} + +static inline void +iop13xx_cp6_irq_restore(unsigned long *cp_flags, + unsigned long *irq_flags) +{ + iop13xx_cp6_restore(*cp_flags); + local_irq_restore(*irq_flags); +} +#endif + +#define INTBASE 0 +#define INTSIZE_4 1 + +/* + * iop34x chipset interrupts + */ +#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x)) + +/* + * On IRQ or FIQ register + */ +#define IRQ_IOP13XX_ADMA0_EOT (0) +#define IRQ_IOP13XX_ADMA0_EOC (1) +#define IRQ_IOP13XX_ADMA1_EOT (2) +#define IRQ_IOP13XX_ADMA1_EOC (3) +#define IRQ_IOP13XX_ADMA2_EOT (4) +#define IRQ_IOP13XX_ADMA2_EOC (5) +#define IRQ_IOP134_WATCHDOG (6) +#define IRQ_IOP13XX_RSVD_7 (7) +#define IRQ_IOP13XX_TIMER0 (8) +#define IRQ_IOP13XX_TIMER1 (9) +#define IRQ_IOP13XX_I2C_0 (10) +#define IRQ_IOP13XX_I2C_1 (11) +#define IRQ_IOP13XX_MSG (12) +#define IRQ_IOP13XX_MSGIBQ (13) +#define IRQ_IOP13XX_ATU_IM (14) +#define IRQ_IOP13XX_ATU_BIST (15) +#define IRQ_IOP13XX_PPMU (16) +#define IRQ_IOP13XX_COREPMU (17) +#define IRQ_IOP13XX_CORECACHE (18) +#define IRQ_IOP13XX_RSVD_19 (19) +#define IRQ_IOP13XX_RSVD_20 (20) +#define IRQ_IOP13XX_RSVD_21 (21) +#define IRQ_IOP13XX_RSVD_22 (22) +#define IRQ_IOP13XX_RSVD_23 (23) +#define IRQ_IOP13XX_XINT0 (24) +#define IRQ_IOP13XX_XINT1 (25) +#define IRQ_IOP13XX_XINT2 (26) +#define IRQ_IOP13XX_XINT3 (27) +#define IRQ_IOP13XX_XINT4 (28) +#define IRQ_IOP13XX_XINT5 (29) +#define IRQ_IOP13XX_XINT6 (30) +#define IRQ_IOP13XX_XINT7 (31) + /* IINTSRC1 bit */ +#define IRQ_IOP13XX_XINT8 (32) /* 0 */ +#define IRQ_IOP13XX_XINT9 (33) /* 1 */ +#define IRQ_IOP13XX_XINT10 (34) /* 2 */ +#define IRQ_IOP13XX_XINT11 (35) /* 3 */ +#define IRQ_IOP13XX_XINT12 (36) /* 4 */ +#define IRQ_IOP13XX_XINT13 (37) /* 5 */ +#define IRQ_IOP13XX_XINT14 (38) /* 6 */ +#define IRQ_IOP13XX_XINT15 (39) /* 7 */ +#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */ +#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */ +#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */ +#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */ +#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */ +#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */ +#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */ +#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */ +#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */ +#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */ +#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */ +#define IRQ_IOP13XX_UART0 (51) /* 19 */ +#define IRQ_IOP13XX_UART1 (52) /* 20 */ +#define IRQ_IOP13XX_PBIE (53) /* 21 */ +#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */ +#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */ +#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */ +#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */ +#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */ +#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */ +#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */ +#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */ +#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */ +#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */ + /* IINTSRC2 bit */ +#define IRQ_IOP13XX_INTERPROC (64) /* 0 */ +#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */ +#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */ +#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */ +#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */ +#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */ +#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */ +#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */ +#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */ +#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */ +#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */ +#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */ +#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */ +#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */ +#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */ +#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */ +#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */ +#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */ +#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */ +#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */ +#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */ +#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */ +#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */ +#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */ +#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */ +#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */ +#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */ +#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */ +#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */ +#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */ +#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */ +#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */ + /* IINTSRC3 bit */ +#define IRQ_IOP13XX_I2C_2 (96) /* 0 */ +#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */ +#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */ +#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */ +#define IRQ_IOP13XX_IMU (100) /* 4 */ +#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */ +#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */ +#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */ +#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */ +#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */ +#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */ +#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */ +#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */ +#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */ +#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ +#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ +#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ +#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */ +#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ +#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ +#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ +#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */ +#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */ +#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */ +#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */ +#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */ +#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */ +#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */ +#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */ +#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */ +#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ +#define IRQ_IOP13XX_HPI (127) /* 31 */ + +#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) +#define NR_IRQS NR_IOP13XX_IRQS + +#endif /* _IOP13XX_IRQ_H_ */ diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h new file mode 100644 index 00000000000..031a0fa78ef --- /dev/null +++ b/include/asm-arm/arch-iop13xx/memory.h @@ -0,0 +1,64 @@ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include <asm/arch/hardware.h> + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x00000000) +#define TASK_SIZE UL(0x3f000000) +#define PAGE_OFFSET UL(0x40000000) +#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3) + +#ifndef __ASSEMBLY__ + +#if defined(CONFIG_ARCH_IOP13XX) +#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE) +#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE) +#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) +#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) + +/* + * Virtual view <-> PCI DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ + +/* RAM has 1:1 mapping on the PCIe/x Busses */ +#define __virt_to_bus(x) (__virt_to_phys(x)) +#define __bus_to_virt(x) (__phys_to_virt(x)) + +#define virt_to_lbus(x) \ +(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \ +((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \ +((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \ +((x) - PAGE_OFFSET + PHYS_OFFSET)) + +#define lbus_to_virt(x) \ +(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \ +((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \ +((x) - PHYS_OFFSET + PAGE_OFFSET)) + +/* Device is an lbus device if it is on the platform bus of the IOP13XX */ +#define is_lbus_device(dev) (dev &&\ + (strncmp(dev->bus->name, "platform", 8) == 0)) + +#define __arch_page_to_dma(dev, page) \ +({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \ +(dma_addr_t)__virt_to_bus(page_address(page));}) + +#define __arch_dma_to_virt(dev, addr) \ +({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);}) + +#define __arch_virt_to_dma(dev, addr) \ +({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);}) + +#endif /* CONFIG_ARCH_IOP13XX */ +#endif /* !ASSEMBLY */ + +#define PFN_TO_NID(addr) (0) + +#endif diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h new file mode 100644 index 00000000000..4041f30d4cd --- /dev/null +++ b/include/asm-arm/arch-iop13xx/pci.h @@ -0,0 +1,57 @@ +#ifndef _IOP13XX_PCI_H_ +#define _IOP13XX_PCI_H_ +#include <asm/arch/irqs.h> +#include <asm/io.h> + +struct pci_sys_data; +struct hw_pci; +int iop13xx_pci_setup(int nr, struct pci_sys_data *sys); +struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *); +void iop13xx_atu_select(struct hw_pci *plat_pci); +void iop13xx_pci_init(void); +void iop13xx_map_pci_memory(void); + +#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \ + PCI_STATUS_SIG_TARGET_ABORT | \ + PCI_STATUS_REC_TARGET_ABORT | \ + PCI_STATUS_REC_TARGET_ABORT | \ + PCI_STATUS_REC_MASTER_ABORT | \ + PCI_STATUS_SIG_SYSTEM_ERROR | \ + PCI_STATUS_DETECTED_PARITY) + +#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \ + IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \ + IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \ + IOP13XX_ATUE_STAT_ERR_COR | \ + IOP13XX_ATUE_STAT_ERR_UNCOR | \ + IOP13XX_ATUE_STAT_CRS | \ + IOP13XX_ATUE_STAT_DET_PAR_ERR | \ + IOP13XX_ATUE_STAT_EXT_REC_MABORT | \ + IOP13XX_ATUE_STAT_SIG_TABORT | \ + IOP13XX_ATUE_STAT_EXT_REC_TABORT | \ + IOP13XX_ATUE_STAT_MASTER_DATA_PAR) + +#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \ + IOP13XX_ATUX_STAT_REC_SCEM | \ + IOP13XX_ATUX_STAT_TX_SERR | \ + IOP13XX_ATUX_STAT_DET_PAR_ERR | \ + IOP13XX_ATUX_STAT_INT_REC_MABORT | \ + IOP13XX_ATUX_STAT_REC_SERR | \ + IOP13XX_ATUX_STAT_EXT_REC_MABORT | \ + IOP13XX_ATUX_STAT_EXT_REC_TABORT | \ + IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \ + IOP13XX_ATUX_STAT_MASTER_DATA_PAR) + +/* PCI interrupts + */ +#define ATUX_INTA IRQ_IOP13XX_XINT0 +#define ATUX_INTB IRQ_IOP13XX_XINT1 +#define ATUX_INTC IRQ_IOP13XX_XINT2 +#define ATUX_INTD IRQ_IOP13XX_XINT3 + +#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA +#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB +#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC +#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD + +#endif /* _IOP13XX_PCI_H_ */ diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h new file mode 100644 index 00000000000..ee3a62530af --- /dev/null +++ b/include/asm-arm/arch-iop13xx/system.h @@ -0,0 +1,59 @@ +/* + * linux/include/asm-arm/arch-iop13xx/system.h + * + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <asm/arch/iop13xx.h> +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +/* WDTCR CP6 R7 Page 9 */ +static inline u32 read_wdtcr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); + return val; +} +static inline void write_wdtcr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); +} + +/* WDTSR CP6 R8 Page 9 */ +static inline u32 read_wdtsr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); + return val; +} +static inline void write_wdtsr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); +} + +#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e +#define IOP13XX_WDTCR_EN 0xe1e1e1e1 +#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f +#define IOP13XX_WDTCR_DIS 0xf1f1f1f1 +#define IOP13XX_WDTSR_WRITE_EN (1 << 31) +#define IOP13XX_WDTCR_IB_RESET (1 << 0) +static inline void arch_reset(char mode) +{ + /* + * Reset the internal bus (warning both cores are reset) + */ + u32 cp_flags = iop13xx_cp6_save(); + write_wdtcr(IOP13XX_WDTCR_EN_ARM); + write_wdtcr(IOP13XX_WDTCR_EN); + write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); + write_wdtcr(0x1000); + iop13xx_cp6_restore(cp_flags); + + for(;;); +} diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h new file mode 100644 index 00000000000..f0c51dd97ed --- /dev/null +++ b/include/asm-arm/arch-iop13xx/timex.h @@ -0,0 +1,3 @@ +#include <asm/hardware.h> + +#define CLOCK_TICK_RATE (100 * HZ) diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h new file mode 100644 index 00000000000..b9525d59b7a --- /dev/null +++ b/include/asm-arm/arch-iop13xx/uncompress.h @@ -0,0 +1,24 @@ +#include <asm/types.h> +#include <linux/serial_reg.h> +#include <asm/hardware.h> +#include <asm/processor.h> + +#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS) +#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) + +static inline void putc(char c) +{ + while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE) + cpu_relax(); + UART_BASE[UART_TX] = c; +} + +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/include/asm-arm/arch-iop13xx/vmalloc.h new file mode 100644 index 00000000000..c5345674034 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/vmalloc.h @@ -0,0 +1,4 @@ +#ifndef _VMALLOC_H_ +#define _VMALLOC_H_ +#define VMALLOC_END 0xfa000000UL +#endif diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h index 4281838873e..6b437f7c995 100644 --- a/include/asm-arm/arch-ixp4xx/nslu2.h +++ b/include/asm-arm/arch-ixp4xx/nslu2.h @@ -76,6 +76,7 @@ #define NSLU2_GPIO_BUZZ 4 #define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ) + /* LEDs */ #define NSLU2_LED_RED NSLU2_GPIO0 @@ -84,8 +85,8 @@ #define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED) #define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN) -#define NSLU2_LED_DISK1 NSLU2_GPIO2 -#define NSLU2_LED_DISK2 NSLU2_GPIO3 +#define NSLU2_LED_DISK1 NSLU2_GPIO3 +#define NSLU2_LED_DISK2 NSLU2_GPIO2 #define NSLU2_LED_DISK1_BM (1L << NSLU2_GPIO2) #define NSLU2_LED_DISK2_BM (1L << NSLU2_GPIO3) diff --git a/include/asm-arm/arch-ixp4xx/udc.h b/include/asm-arm/arch-ixp4xx/udc.h new file mode 100644 index 00000000000..dbdec36ff0d --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/udc.h @@ -0,0 +1,8 @@ +/* + * linux/include/asm-arm/arch-ixp4xx/udc.h + * + */ +#include <asm/mach/udc_pxa2xx.h> + +extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info); + diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h index d744d97c18a..645dbdfb390 100644 --- a/include/asm-arm/arch-l7200/io.h +++ b/include/asm-arm/arch-l7200/io.h @@ -17,59 +17,11 @@ /* * There are not real ISA nor PCI buses, so we fake it. */ -#define __io_pci(a) ((void __iomem *)(PCIO_BASE + (a))) -#define __mem_pci(a) (a) - -#define __ioaddr(p) __io_pci(p) - -/* - * Generic virtual read/write - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -static inline unsigned int __arch_getw(unsigned long a) -{ - unsigned int value; - __asm__ __volatile__("ldrh %0, [%1, #0] @ getw" - : "=&r" (value) - : "r" (a) : "cc"); - return value; -} - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -static inline void __arch_putw(unsigned int value, unsigned long a) +static inline void __iomem *__io(unsigned long addr) { - __asm__ __volatile__("strh %0, [%1, #0] @ putw" - : : "r" (value), "r" (a) : "cc"); + return (void __iomem *)addr; } - -/* - * Translated address IO functions - * - * IO address has already been translated to a virtual address - */ -#define outb_t(v,p) (*(volatile unsigned char *)(p) = (v)) -#define inb_t(p) (*(volatile unsigned char *)(p)) -#define outw_t(v,p) (*(volatile unsigned int *)(p) = (v)) -#define inw_t(p) (*(volatile unsigned int *)(p)) -#define outl_t(v,p) (*(volatile unsigned long *)(p) = (v)) -#define inl_t(p) (*(volatile unsigned long *)(p)) - -/* - * FIXME - These are to allow for linking. On all the other - * ARM platforms, the entire IO space is contiguous. - * The 7200 has three separate IO spaces. The below - * macros will eventually become more involved. Use - * with caution and don't be surprised by kernel oopses!!! - */ -#define inb(p) inb_t(p) -#define inw(p) inw_t(p) -#define inl(p) inl_t(p) -#define outb(v,p) outb_t(v,p) -#define outw(v,p) outw_t(v,p) -#define outl(v,p) outl_t(v,p) +#define __io(a) __io(a) +#define __mem_pci(a) (a) #endif diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h index 9f1a58cbf40..9b0c8012e71 100644 --- a/include/asm-arm/arch-lh7a40x/memory.h +++ b/include/asm-arm/arch-lh7a40x/memory.h @@ -58,18 +58,6 @@ #endif /* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and return the mem_map of that node. - */ -# define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) - -/* - * Given a page frame number, find the owning node of the memory - * and return the mem_map of that node. - */ -# define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) - -/* * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory * and returns the index corresponding to the appropriate page in the * node's mem_map. diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h index eaf6d43939e..e17f9881faf 100644 --- a/include/asm-arm/arch-pxa/memory.h +++ b/include/asm-arm/arch-pxa/memory.h @@ -27,7 +27,6 @@ #define __virt_to_bus(x) __virt_to_phys(x) #define __bus_to_virt(x) __phys_to_virt(x) -#ifdef CONFIG_DISCONTIGMEM /* * The nodes are matched with the physical SDRAM banks as follows: * @@ -35,38 +34,9 @@ * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff + * + * This needs a node mem size of 26 bits. */ - -/* - * Given a kernel address, find the home node of the underlying memory. - */ -#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26) - -/* - * Given a page frame number, convert it to a node id. - */ -#define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT)) - -/* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and returns the mem_map of that node. - */ -#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) - -/* - * Given a page frame number, find the owning node of the memory - * and returns the mem_map of that node. - */ -#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) - -/* - * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory - * and returns the index corresponding to the appropriate page in the - * node's mem_map. - */ -#define LOCAL_MAP_NR(addr) \ - (((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT) - -#endif +#define NODE_MEM_SIZE_BITS 26 #endif diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index cff752f3523..083e03c5639 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -99,7 +99,7 @@ #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ -#define DCSR_ENRINTR (1 << 9) /* The end of Receive */ +#define DCSR_EORINTR (1 << 9) /* The end of Receive */ #endif #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ @@ -803,12 +803,11 @@ #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */ -#define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCISR1_IERU (1 << 29) /* IntEn - Resume */ -#define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */ -#define UDCISR1_IERS (1 << 27) /* IntEn - Reset */ - +#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ +#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ +#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ +#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ +#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ diff --git a/include/asm-arm/arch-s3c2410/h1940.h b/include/asm-arm/arch-s3c2410/h1940.h new file mode 100644 index 00000000000..6135592e60f --- /dev/null +++ b/include/asm-arm/arch-s3c2410/h1940.h @@ -0,0 +1,21 @@ +/* linux/include/asm-arm/arch-s3c2410/h1940.h + * + * Copyright 2006 Ben Dooks <ben-linux@fluff.org> + * + * H1940 definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_H1940_H +#define __ASM_ARCH_H1940_H + +#define H1940_SUSPEND_CHECKSUM (0x30003ff8) +#define H1940_SUSPEND_RESUMEAT (0x30081000) +#define H1940_SUSPEND_CHECK (0x30080000) + +extern void h1940_pm_return(void); + +#endif /* __ASM_ARCH_H1940_H */ diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h index 718246d8595..4f72a853a5c 100644 --- a/include/asm-arm/arch-s3c2410/system.h +++ b/include/asm-arm/arch-s3c2410/system.h @@ -71,7 +71,7 @@ arch_reset(char mode) /* set the watchdog to go and reset... */ __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | - S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); + S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); /* wait for reset to assert... */ mdelay(5000); diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h deleted file mode 100644 index 3f37ca07806..00000000000 --- a/include/asm-arm/arch-sa1100/jornada720.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * linux/include/asm-arm/arch-sa1100/jornada720.h - * - * Created 2000/11/29 by John Ankcorn <jca@lcs.mit.edu> - * - * This file contains the hardware specific definitions for HP Jornada 720 - * - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#error "include <asm/hardware.h> instead" -#endif - -#define SA1111_BASE (0x40000000) - -#define GPIO_JORNADA720_KEYBOARD GPIO_GPIO(0) -#define GPIO_JORNADA720_MOUSE GPIO_GPIO(9) - -#define GPIO_JORNADA720_KEYBOARD_IRQ IRQ_GPIO0 -#define GPIO_JORNADA720_MOUSE_IRQ IRQ_GPIO9 - -/* MCU COMMANDS */ -#define MCU_GetBatteryData 0xc0 -#define MCU_GetScanKeyCode 0x90 -#define MCU_GetTouchSamples 0xa0 -#define MCU_GetContrast 0xD0 -#define MCU_SetContrast 0xD1 -#define MCU_GetBrightness 0xD2 -#define MCU_SetBrightness 0xD3 -#define MCU_ContrastOff 0xD8 -#define MCU_BrightnessOff 0xD9 -#define MCU_PWMOFF 0xDF -#define MCU_TxDummy 0x11 -#define MCU_ErrorCode 0x00 - -#ifndef __ASSEMBLY__ - -void jornada720_mcu_init(void); -void jornada_contrast(int arg_contrast); -void jornada720_battery(void); -int jornada720_getkey(unsigned char *data, int size); -#endif diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h index 1ff172dc8e3..0e907fc6d42 100644 --- a/include/asm-arm/arch-sa1100/memory.h +++ b/include/asm-arm/arch-sa1100/memory.h @@ -39,7 +39,6 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); #define __virt_to_bus(x) __virt_to_phys(x) #define __bus_to_virt(x) __phys_to_virt(x) -#ifdef CONFIG_DISCONTIGMEM /* * Because of the wide memory address space between physical RAM banks on the * SA1100, it's much convenient to use Linux's NUMA support to implement our @@ -57,38 +56,7 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); * node 2: 0xd0000000 - 0xd7ffffff * node 3: 0xd8000000 - 0xdfffffff */ - -/* - * Given a kernel address, find the home node of the underlying memory. - */ -#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 27) - -/* - * Given a page frame number, convert it to a node id. - */ -#define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (27 - PAGE_SHIFT)) - -/* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and return the mem_map of that node. - */ -#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) - -/* - * Given a page frame number, find the owning node of the memory - * and return the mem_map of that node. - */ -#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) - -/* - * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory - * and returns the index corresponding to the appropriate page in the - * node's mem_map. - */ -#define LOCAL_MAP_NR(addr) \ - (((unsigned long)(addr) & 0x07ffffff) >> PAGE_SHIFT) - -#endif +#define NODE_MEM_SIZE_BITS 27 /* * Cache flushing area - SA1100 zero bank diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h index 0e36fd5d87d..7b62351f097 100644 --- a/include/asm-arm/bug.h +++ b/include/asm-arm/bug.h @@ -4,10 +4,10 @@ #ifdef CONFIG_BUG #ifdef CONFIG_DEBUG_BUGVERBOSE -extern void __bug(const char *file, int line, void *data) __attribute__((noreturn)); +extern void __bug(const char *file, int line) __attribute__((noreturn)); /* give file/line information */ -#define BUG() __bug(__FILE__, __LINE__, NULL) +#define BUG() __bug(__FILE__, __LINE__) #else diff --git a/include/asm-arm/cnt32_to_63.h b/include/asm-arm/cnt32_to_63.h new file mode 100644 index 00000000000..480c873fa74 --- /dev/null +++ b/include/asm-arm/cnt32_to_63.h @@ -0,0 +1,78 @@ +/* + * include/asm/cnt32_to_63.h -- extend a 32-bit counter to 63 bits + * + * Author: Nicolas Pitre + * Created: December 3, 2006 + * Copyright: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#ifndef __INCLUDE_CNT32_TO_63_H__ +#define __INCLUDE_CNT32_TO_63_H__ + +#include <linux/compiler.h> +#include <asm/types.h> +#include <asm/byteorder.h> + +/* + * Prototype: u64 cnt32_to_63(u32 cnt) + * Many hardware clock counters are only 32 bits wide and therefore have + * a relatively short period making wrap-arounds rather frequent. This + * is a problem when implementing sched_clock() for example, where a 64-bit + * non-wrapping monotonic value is expected to be returned. + * + * To overcome that limitation, let's extend a 32-bit counter to 63 bits + * in a completely lock free fashion. Bits 0 to 31 of the clock are provided + * by the hardware while bits 32 to 62 are stored in memory. The top bit in + * memory is used to synchronize with the hardware clock half-period. When + * the top bit of both counters (hardware and in memory) differ then the + * memory is updated with a new value, incrementing it when the hardware + * counter wraps around. + * + * Because a word store in memory is atomic then the incremented value will + * always be in synch with the top bit indicating to any potential concurrent + * reader if the value in memory is up to date or not with regards to the + * needed increment. And any race in updating the value in memory is harmless + * as the same value would simply be stored more than once. + * + * The only restriction for the algorithm to work properly is that this + * code must be executed at least once per each half period of the 32-bit + * counter to properly update the state bit in memory. This is usually not a + * problem in practice, but if it is then a kernel timer could be scheduled + * to manage for this code to be executed often enough. + * + * Note that the top bit (bit 63) in the returned value should be considered + * as garbage. It is not cleared here because callers are likely to use a + * multiplier on the returned value which can get rid of the top bit + * implicitly by making the multiplier even, therefore saving on a runtime + * clear-bit instruction. Otherwise caller must remember to clear the top + * bit explicitly. + */ + +/* this is used only to give gcc a clue about good code generation */ +typedef union { + struct { +#if defined(__LITTLE_ENDIAN) + u32 lo, hi; +#elif defined(__BIG_ENDIAN) + u32 hi, lo; +#endif + }; + u64 val; +} cnt32_to_63_t; + +#define cnt32_to_63(cnt_lo) \ +({ \ + static volatile u32 __m_cnt_hi = 0; \ + cnt32_to_63_t __x; \ + __x.hi = __m_cnt_hi; \ + __x.lo = (cnt_lo); \ + if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \ + __m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \ + __x.val; \ +}) + +#endif diff --git a/include/asm-arm/div64.h b/include/asm-arm/div64.h index 3682616804c..37e0a96e878 100644 --- a/include/asm-arm/div64.h +++ b/include/asm-arm/div64.h @@ -27,7 +27,7 @@ #define __xh "r1" #endif -#define do_div(n,base) \ +#define __do_div_asm(n, base) \ ({ \ register unsigned int __base asm("r4") = base; \ register unsigned long long __n asm("r0") = n; \ @@ -45,4 +45,182 @@ __rem; \ }) +#if __GNUC__ < 4 + +/* + * gcc versions earlier than 4.0 are simply too problematic for the + * optimized implementation below. First there is gcc PR 15089 that + * tend to trig on more complex constructs, spurious .global __udivsi3 + * are inserted even if none of those symbols are referenced in the + * generated code, and those gcc versions are not able to do constant + * propagation on long long values anyway. + */ +#define do_div(n, base) __do_div_asm(n, base) + +#elif __GNUC__ >= 4 + +#include <asm/bug.h> + +/* + * If the divisor happens to be constant, we determine the appropriate + * inverse at compile time to turn the division into a few inline + * multiplications instead which is much faster. And yet only if compiling + * for ARMv4 or higher (we need umull/umlal) and if the gcc version is + * sufficiently recent to perform proper long long constant propagation. + * (It is unfortunate that gcc doesn't perform all this internally.) + */ +#define do_div(n, base) \ +({ \ + unsigned int __r, __b = (base); \ + if (!__builtin_constant_p(__b) || __b == 0 || \ + (__LINUX_ARM_ARCH__ < 4 && (__b & (__b - 1)) != 0)) { \ + /* non-constant divisor (or zero): slow path */ \ + __r = __do_div_asm(n, __b); \ + } else if ((__b & (__b - 1)) == 0) { \ + /* Trivial: __b is constant and a power of 2 */ \ + /* gcc does the right thing with this code. */ \ + __r = n; \ + __r &= (__b - 1); \ + n /= __b; \ + } else { \ + /* Multiply by inverse of __b: n/b = n*(p/b)/p */ \ + /* We rely on the fact that most of this code gets */ \ + /* optimized away at compile time due to constant */ \ + /* propagation and only a couple inline assembly */ \ + /* instructions should remain. Better avoid any */ \ + /* code construct that might prevent that. */ \ + unsigned long long __res, __x, __t, __m, __n = n; \ + unsigned int __c, __p, __z = 0; \ + /* preserve low part of n for reminder computation */ \ + __r = __n; \ + /* determine number of bits to represent __b */ \ + __p = 1 << __div64_fls(__b); \ + /* compute __m = ((__p << 64) + __b - 1) / __b */ \ + __m = (~0ULL / __b) * __p; \ + __m += (((~0ULL % __b + 1) * __p) + __b - 1) / __b; \ + /* compute __res = __m*(~0ULL/__b*__b-1)/(__p << 64) */ \ + __x = ~0ULL / __b * __b - 1; \ + __res = (__m & 0xffffffff) * (__x & 0xffffffff); \ + __res >>= 32; \ + __res += (__m & 0xffffffff) * (__x >> 32); \ + __t = __res; \ + __res += (__x & 0xffffffff) * (__m >> 32); \ + __t = (__res < __t) ? (1ULL << 32) : 0; \ + __res = (__res >> 32) + __t; \ + __res += (__m >> 32) * (__x >> 32); \ + __res /= __p; \ + /* Now sanitize and optimize what we've got. */ \ + if (~0ULL % (__b / (__b & -__b)) == 0) { \ + /* those cases can be simplified with: */ \ + __n /= (__b & -__b); \ + __m = ~0ULL / (__b / (__b & -__b)); \ + __p = 1; \ + __c = 1; \ + } else if (__res != __x / __b) { \ + /* We can't get away without a correction */ \ + /* to compensate for bit truncation errors. */ \ + /* To avoid it we'd need an additional bit */ \ + /* to represent __m which would overflow it. */ \ + /* Instead we do m=p/b and n/b=(n*m+m)/p. */ \ + __c = 1; \ + /* Compute __m = (__p << 64) / __b */ \ + __m = (~0ULL / __b) * __p; \ + __m += ((~0ULL % __b + 1) * __p) / __b; \ + } else { \ + /* Reduce __m/__p, and try to clear bit 31 */ \ + /* of __m when possible otherwise that'll */ \ + /* need extra overflow handling later. */ \ + unsigned int __bits = -(__m & -__m); \ + __bits |= __m >> 32; \ + __bits = (~__bits) << 1; \ + /* If __bits == 0 then setting bit 31 is */ \ + /* unavoidable. Simply apply the maximum */ \ + /* possible reduction in that case. */ \ + /* Otherwise the MSB of __bits indicates the */ \ + /* best reduction we should apply. */ \ + if (!__bits) { \ + __p /= (__m & -__m); \ + __m /= (__m & -__m); \ + } else { \ + __p >>= __div64_fls(__bits); \ + __m >>= __div64_fls(__bits); \ + } \ + /* No correction needed. */ \ + __c = 0; \ + } \ + /* Now we have a combination of 2 conditions: */ \ + /* 1) whether or not we need a correction (__c), and */ \ + /* 2) whether or not there might be an overflow in */ \ + /* the cross product (__m & ((1<<63) | (1<<31))) */ \ + /* Select the best insn combination to perform the */ \ + /* actual __m * __n / (__p << 64) operation. */ \ + if (!__c) { \ + asm ( "umull %Q0, %R0, %1, %Q2\n\t" \ + "mov %Q0, #0" \ + : "=&r" (__res) \ + : "r" (__m), "r" (__n) \ + : "cc" ); \ + } else if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \ + __res = __m; \ + asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t" \ + "mov %Q0, #0" \ + : "+r" (__res) \ + : "r" (__m), "r" (__n) \ + : "cc" ); \ + } else { \ + asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" \ + "cmn %Q0, %Q1\n\t" \ + "adcs %R0, %R0, %R1\n\t" \ + "adc %Q0, %3, #0" \ + : "=&r" (__res) \ + : "r" (__m), "r" (__n), "r" (__z) \ + : "cc" ); \ + } \ + if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \ + asm ( "umlal %R0, %Q0, %R1, %Q2\n\t" \ + "umlal %R0, %Q0, %Q1, %R2\n\t" \ + "mov %R0, #0\n\t" \ + "umlal %Q0, %R0, %R1, %R2" \ + : "+r" (__res) \ + : "r" (__m), "r" (__n) \ + : "cc" ); \ + } else { \ + asm ( "umlal %R0, %Q0, %R2, %Q3\n\t" \ + "umlal %R0, %1, %Q2, %R3\n\t" \ + "mov %R0, #0\n\t" \ + "adds %Q0, %1, %Q0\n\t" \ + "adc %R0, %R0, #0\n\t" \ + "umlal %Q0, %R0, %R2, %R3" \ + : "+r" (__res), "+r" (__z) \ + : "r" (__m), "r" (__n) \ + : "cc" ); \ + } \ + __res /= __p; \ + /* The reminder can be computed with 32-bit regs */ \ + /* only, and gcc is good at that. */ \ + { \ + unsigned int __res0 = __res; \ + unsigned int __b0 = __b; \ + __r -= __res0 * __b0; \ + } \ + /* BUG_ON(__r >= __b || __res * __b + __r != n); */ \ + n = __res; \ + } \ + __r; \ +}) + +/* our own fls implementation to make sure constant propagation is fine */ +#define __div64_fls(bits) \ +({ \ + unsigned int __left = (bits), __nr = 0; \ + if (__left & 0xffff0000) __nr += 16, __left >>= 16; \ + if (__left & 0x0000ff00) __nr += 8, __left >>= 8; \ + if (__left & 0x000000f0) __nr += 4, __left >>= 4; \ + if (__left & 0x0000000c) __nr += 2, __left >>= 2; \ + if (__left & 0x00000002) __nr += 1; \ + __nr; \ +}) + +#endif + #endif diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h index 17f0c656d27..642382d2c9f 100644 --- a/include/asm-arm/elf.h +++ b/include/asm-arm/elf.h @@ -1,17 +1,22 @@ #ifndef __ASMARM_ELF_H #define __ASMARM_ELF_H - +#ifndef __ASSEMBLY__ /* * ELF register definitions.. */ - #include <asm/ptrace.h> #include <asm/user.h> typedef unsigned long elf_greg_t; typedef unsigned long elf_freg_t[3]; +#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +typedef struct user_fp elf_fpregset_t; +#endif + #define EM_ARM 40 #define EF_ARM_APCS26 0x08 #define EF_ARM_SOFT_FLOAT 0x200 @@ -23,11 +28,6 @@ typedef unsigned long elf_freg_t[3]; #define R_ARM_CALL 28 #define R_ARM_JUMP24 29 -#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -typedef struct user_fp elf_fpregset_t; - /* * These are used to set parameters in the core dumps. */ @@ -39,97 +39,99 @@ typedef struct user_fp elf_fpregset_t; #endif #define ELF_ARCH EM_ARM -#ifdef __KERNEL__ -#include <asm/procinfo.h> - /* - * This is used to ensure we don't load something for the wrong architecture. + * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP */ -#define elf_check_arch(x) ( ((x)->e_machine == EM_ARM) && (ELF_PROC_OK((x))) ) - -#define USE_ELF_CORE_DUMP -#define ELF_EXEC_PAGESIZE 4096 - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) - -/* When the program starts, a1 contains a pointer to a function to be - registered with atexit, as per the SVR4 ABI. A value of 0 means we - have no such handler. */ -#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0 - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. */ +#define HWCAP_SWP 1 +#define HWCAP_HALF 2 +#define HWCAP_THUMB 4 +#define HWCAP_26BIT 8 /* Play it safe */ +#define HWCAP_FAST_MULT 16 +#define HWCAP_FPA 32 +#define HWCAP_VFP 64 +#define HWCAP_EDSP 128 +#define HWCAP_JAVA 256 +#define HWCAP_IWMMXT 512 +#ifdef __KERNEL__ +#ifndef __ASSEMBLY__ +/* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ #define ELF_HWCAP (elf_hwcap) +extern unsigned int elf_hwcap; -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. */ - -/* For now we just provide a fairly general string that describes the - processor family. This could be made more specific later if someone - implemented optimisations that require it. 26-bit CPUs give you - "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't - supported). 32-bit CPUs give you "v3[lb]" for anything based on an - ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1 - core. */ - +/* + * This yields a string that ld.so will use to load implementation + * specific libraries for optimization. This is more specific in + * intent than poking at uname or /proc/cpuinfo. + * + * For now we just provide a fairly general string that describes the + * processor family. This could be made more specific later if someone + * implemented optimisations that require it. 26-bit CPUs give you + * "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't + * supported). 32-bit CPUs give you "v3[lb]" for anything based on an + * ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1 + * core. + */ #define ELF_PLATFORM_SIZE 8 -extern char elf_platform[]; #define ELF_PLATFORM (elf_platform) +extern char elf_platform[]; +#endif + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) ((x)->e_machine == EM_ARM && ELF_PROC_OK(x)) + /* * 32-bit code is always OK. Some cpus can do 26-bit, some can't. */ #define ELF_PROC_OK(x) (ELF_THUMB_OK(x) && ELF_26BIT_OK(x)) #define ELF_THUMB_OK(x) \ - (( (elf_hwcap & HWCAP_THUMB) && ((x)->e_entry & 1) == 1) || \ + ((elf_hwcap & HWCAP_THUMB && ((x)->e_entry & 1) == 1) || \ ((x)->e_entry & 3) == 0) #define ELF_26BIT_OK(x) \ - (( (elf_hwcap & HWCAP_26BIT) && (x)->e_flags & EF_ARM_APCS26) || \ + ((elf_hwcap & HWCAP_26BIT && (x)->e_flags & EF_ARM_APCS26) || \ ((x)->e_flags & EF_ARM_APCS26) == 0) -#ifndef CONFIG_IWMMXT +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 -/* Old NetWinder binaries were compiled in such a way that the iBCS - heuristic always trips on them. Until these binaries become uncommon - enough not to care, don't trust the `ibcs' flag here. In any case - there is no other ELF system currently supported by iBCS. - @@ Could print a warning message to encourage users to upgrade. */ -#define SET_PERSONALITY(ex,ibcs2) \ - set_personality(((ex).e_flags&EF_ARM_APCS26 ?PER_LINUX :PER_LINUX_32BIT)) +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ -#else +#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) + +/* When the program starts, a1 contains a pointer to a function to be + registered with atexit, as per the SVR4 ABI. A value of 0 means we + have no such handler. */ +#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0 /* - * All iWMMXt capable CPUs don't support 26-bit mode. Yet they can run - * legacy binaries which used to contain FPA11 floating point instructions - * that have always been emulated by the kernel. PFA11 and iWMMXt overlap - * on coprocessor 1 space though. We therefore must decide if given task - * is allowed to use CP 0 and 1 for iWMMXt, or if they should be blocked - * at all times for the prefetch exception handler to catch FPA11 opcodes - * and emulate them. The best indication to discriminate those two cases - * is the SOFT_FLOAT flag in the ELF header. + * Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0 + * and CP1, we only enable access to the iWMMXt coprocessor if the + * binary is EABI or softfloat (and thus, guaranteed not to use + * FPA instructions.) */ - -#define SET_PERSONALITY(ex,ibcs2) \ -do { \ - set_personality(PER_LINUX_32BIT); \ - if (((ex).e_flags & EF_ARM_EABI_MASK) || \ - ((ex).e_flags & EF_ARM_SOFT_FLOAT)) \ - set_thread_flag(TIF_USING_IWMMXT); \ - else \ - clear_thread_flag(TIF_USING_IWMMXT); \ -} while (0) - -#endif +#define SET_PERSONALITY(ex, ibcs2) \ + do { \ + if ((ex).e_flags & EF_ARM_APCS26) { \ + set_personality(PER_LINUX); \ + } else { \ + set_personality(PER_LINUX_32BIT); \ + if (elf_hwcap & HWCAP_IWMMXT && (ex).e_flags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) \ + set_thread_flag(TIF_USING_IWMMXT); \ + else \ + clear_thread_flag(TIF_USING_IWMMXT); \ + } \ + } while (0) #endif diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index ae999fd5dc6..288f76b166d 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -75,14 +75,6 @@ extern void __readwrite_bug(const char *fn); */ #include <asm/arch/io.h> -#ifdef __io_pci -#warning machine class uses buggy __io_pci -#endif -#if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \ - defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl) -#warning machine class uses old __arch_putw or __arch_getw -#endif - /* * IO port access primitives * ------------------------- diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h index 0e017ecf209..eb0bfba6570 100644 --- a/include/asm-arm/mach/irq.h +++ b/include/asm-arm/mach/irq.h @@ -22,12 +22,6 @@ extern void init_FIQ(void); extern int show_fiq_list(struct seq_file *, void *); /* - * Function wrappers - */ -#define set_irq_chipdata(irq, d) set_irq_chip_data(irq, d) -#define get_irq_chipdata(irq) get_irq_chip_data(irq) - -/* * Obsolete inline function for calling irq descriptor handlers. */ static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc) @@ -44,12 +38,6 @@ void set_irq_flags(unsigned int irq, unsigned int flags); /* * This is for easy migration, but should be changed in the source */ -#define do_level_IRQ handle_level_irq -#define do_edge_IRQ handle_edge_irq -#define do_simple_IRQ handle_simple_irq -#define irqdesc irq_desc -#define irqchip irq_chip - #define do_bad_IRQ(irq,desc) \ do { \ spin_lock(&desc->lock); \ diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index 91d536c215d..d9bfb39adab 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h @@ -215,6 +215,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x) * virt_addr_valid(k) indicates whether a virtual address is valid */ #ifndef CONFIG_DISCONTIGMEM + #define ARCH_PFN_OFFSET PHYS_PFN_OFFSET #define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) @@ -230,6 +231,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x) * around in memory. */ #include <linux/numa.h> + #define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn) #define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT) @@ -256,6 +258,43 @@ static inline __deprecated void *bus_to_virt(unsigned long x) */ #define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) +/* + * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory + * and returns the mem_map of that node. + */ +#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) + +/* + * Given a page frame number, find the owning node of the memory + * and returns the mem_map of that node. + */ +#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) + +#ifdef NODE_MEM_SIZE_BITS +#define NODE_MEM_SIZE_MASK ((1 << NODE_MEM_SIZE_BITS) - 1) + +/* + * Given a kernel address, find the home node of the underlying memory. + */ +#define KVADDR_TO_NID(addr) \ + (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS) + +/* + * Given a page frame number, convert it to a node id. + */ +#define PFN_TO_NID(pfn) \ + (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT)) + +/* + * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory + * and returns the index corresponding to the appropriate page in the + * node's mem_map. + */ +#define LOCAL_MAP_NR(addr) \ + (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT) + +#endif /* NODE_MEM_SIZE_BITS */ + #endif /* !CONFIG_DISCONTIGMEM */ /* diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h index c1b264dff28..7b1c9acdf79 100644 --- a/include/asm-arm/pgtable-nommu.h +++ b/include/asm-arm/pgtable-nommu.h @@ -44,7 +44,6 @@ #define PAGE_READONLY __pgprot(0) #define PAGE_KERNEL __pgprot(0) -//extern void paging_init(struct meminfo *, struct machine_desc *); #define swapper_pg_dir ((pgd_t *) 0) #define __swp_type(x) (0) diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index ed8cb5963e9..88cd5c784ef 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -169,8 +169,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define L_PTE_WRITE (1 << 5) #define L_PTE_EXEC (1 << 6) #define L_PTE_DIRTY (1 << 7) -#define L_PTE_COHERENT (1 << 9) /* I/O coherent (xsc3) */ -#define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */ +#define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */ #define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */ #ifndef __ASSEMBLY__ diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h index 04f4d34c631..b442e8e2a80 100644 --- a/include/asm-arm/processor.h +++ b/include/asm-arm/processor.h @@ -20,7 +20,6 @@ #ifdef __KERNEL__ #include <asm/ptrace.h> -#include <asm/procinfo.h> #include <asm/types.h> union debug_insn { diff --git a/include/asm-arm/procinfo.h b/include/asm-arm/procinfo.h index 91a31adfa8a..4d3c685075e 100644 --- a/include/asm-arm/procinfo.h +++ b/include/asm-arm/procinfo.h @@ -10,7 +10,7 @@ #ifndef __ASM_PROCINFO_H #define __ASM_PROCINFO_H -#ifndef __ASSEMBLY__ +#ifdef __KERNEL__ struct cpu_tlb_fns; struct cpu_user_fns; @@ -42,19 +42,8 @@ struct proc_info_list { struct cpu_cache_fns *cache; }; -extern unsigned int elf_hwcap; - -#endif /* __ASSEMBLY__ */ - -#define HWCAP_SWP 1 -#define HWCAP_HALF 2 -#define HWCAP_THUMB 4 -#define HWCAP_26BIT 8 /* Play it safe */ -#define HWCAP_FAST_MULT 16 -#define HWCAP_FPA 32 -#define HWCAP_VFP 64 -#define HWCAP_EDSP 128 -#define HWCAP_JAVA 256 -#define HWCAP_IWMMXT 512 - +#else /* __KERNEL__ */ +#include <asm/elf.h> +#warning "Please include asm/elf.h instead" +#endif /* __KERNEL__ */ #endif diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h index f28b236139e..d9b8bddc873 100644 --- a/include/asm-arm/thread_info.h +++ b/include/asm-arm/thread_info.h @@ -94,8 +94,18 @@ static inline struct thread_info *current_thread_info(void) return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); } -extern struct thread_info *alloc_thread_info(struct task_struct *task); -extern void free_thread_info(struct thread_info *); +/* thread information allocation */ +#ifdef CONFIG_DEBUG_STACK_USAGE +#define alloc_thread_info(tsk) \ + ((struct thread_info *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, \ + THREAD_SIZE_ORDER)) +#else +#define alloc_thread_info(tsk) \ + ((struct thread_info *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER)) +#endif + +#define free_thread_info(info) \ + free_pages((unsigned long)info, THREAD_SIZE_ORDER); #define thread_saved_pc(tsk) \ ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc))) |