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Diffstat (limited to 'include/asm-powerpc/pci-bridge.h')
-rw-r--r--include/asm-powerpc/pci-bridge.h16
1 files changed, 13 insertions, 3 deletions
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index e72c2a60853..d53e0eb1de1 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -45,10 +45,17 @@ struct pci_controller {
* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
* to determine which bus number to match on when generating type0
* config cycles
+ * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
+ * hanging if we don't have link and try to do config cycles to
+ * anything but the PHB. Only allow talking to the PHB if this is
+ * set.
+ * BIG_ENDIAN - cfg_addr is a big endian register
*/
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
+#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008)
+#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010)
u32 indirect_type;
/* Currently, we limit ourselves to 1 IO range and 3 mem
@@ -79,11 +86,14 @@ int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
int where, u32 val);
-extern void setup_indirect_pci_nomap(struct pci_controller* hose,
- void __iomem *cfg_addr, void __iomem *cfg_data);
+extern int early_find_capability(struct pci_controller *hose, int bus,
+ int dev_fn, int cap);
+
extern void setup_indirect_pci(struct pci_controller* hose,
- u32 cfg_addr, u32 cfg_data);
+ u32 cfg_addr, u32 cfg_data, u32 flags);
extern void setup_grackle(struct pci_controller *hose);
+extern void __init update_bridge_resource(struct pci_dev *dev,
+ struct resource *res);
#else