diff options
Diffstat (limited to 'include')
110 files changed, 2517 insertions, 1956 deletions
diff --git a/include/asm-alpha/atomic.h b/include/asm-alpha/atomic.h index cb03bbe92cd..fc77f741308 100644 --- a/include/asm-alpha/atomic.h +++ b/include/asm-alpha/atomic.h @@ -176,6 +176,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) } #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) #define atomic_add_unless(v, a, u) \ ({ \ diff --git a/include/asm-alpha/mutex.h b/include/asm-alpha/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-alpha/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h new file mode 100644 index 00000000000..58f40931a5c --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h @@ -0,0 +1,261 @@ +/* + * include/asm-arm/arch-at91rm9200/at91rm9200.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Common definitions. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91RM9200_H +#define AT91RM9200_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripheral */ +#define AT91_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91_ID_PIOD 5 /* Parallel IO Controller D */ +#define AT91_ID_US0 6 /* USART 0 */ +#define AT91_ID_US1 7 /* USART 1 */ +#define AT91_ID_US2 8 /* USART 2 */ +#define AT91_ID_US3 9 /* USART 3 */ +#define AT91_ID_MCI 10 /* Multimedia Card Interface */ +#define AT91_ID_UDP 11 /* USB Device Port */ +#define AT91_ID_TWI 12 /* Two-Wire Interface */ +#define AT91_ID_SPI 13 /* Serial Peripheral Interface */ +#define AT91_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define AT91_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define AT91_ID_SSC2 16 /* Serial Synchronous Controller 2 */ +#define AT91_ID_TC0 17 /* Timer Counter 0 */ +#define AT91_ID_TC1 18 /* Timer Counter 1 */ +#define AT91_ID_TC2 19 /* Timer Counter 2 */ +#define AT91_ID_TC3 20 /* Timer Counter 3 */ +#define AT91_ID_TC4 21 /* Timer Counter 4 */ +#define AT91_ID_TC5 22 /* Timer Counter 5 */ +#define AT91_ID_UHP 23 /* USB Host port */ +#define AT91_ID_EMAC 24 /* Ethernet MAC */ +#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ +#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ +#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ +#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ +#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ + + +/* + * Peripheral physical base addresses. + */ +#define AT91_BASE_TCB0 0xfffa0000 +#define AT91_BASE_TC0 0xfffa0000 +#define AT91_BASE_TC1 0xfffa0040 +#define AT91_BASE_TC2 0xfffa0080 +#define AT91_BASE_TCB1 0xfffa4000 +#define AT91_BASE_TC3 0xfffa4000 +#define AT91_BASE_TC4 0xfffa4040 +#define AT91_BASE_TC5 0xfffa4080 +#define AT91_BASE_UDP 0xfffb0000 +#define AT91_BASE_MCI 0xfffb4000 +#define AT91_BASE_TWI 0xfffb8000 +#define AT91_BASE_EMAC 0xfffbc000 +#define AT91_BASE_US0 0xfffc0000 +#define AT91_BASE_US1 0xfffc4000 +#define AT91_BASE_US2 0xfffc8000 +#define AT91_BASE_US3 0xfffcc000 +#define AT91_BASE_SSC0 0xfffd0000 +#define AT91_BASE_SSC1 0xfffd4000 +#define AT91_BASE_SSC2 0xfffd8000 +#define AT91_BASE_SPI 0xfffe0000 +#define AT91_BASE_SYS 0xfffff000 + + +/* + * PIO pin definitions (peripheral A/B multiplexing). + */ +#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */ +#define AT91_PA0_PCK3 (1 << 0) /* B: PMC Programmable Clock Output 3 */ +#define AT91_PA1_MOSI (1 << 1) /* A: SPI Master-Out Slave-In */ +#define AT91_PA1_PCK0 (1 << 1) /* B: PMC Programmable Clock Output 0 */ +#define AT91_PA2_SPCK (1 << 2) /* A: SPI Serial Clock */ +#define AT91_PA2_IRQ4 (1 << 2) /* B: External Interrupt 4 */ +#define AT91_PA3_NPCS0 (1 << 3) /* A: SPI Peripheral Chip Select 0 */ +#define AT91_PA3_IRQ5 (1 << 3) /* B: External Interrupt 5 */ +#define AT91_PA4_NPCS1 (1 << 4) /* A: SPI Peripheral Chip Select 1 */ +#define AT91_PA4_PCK1 (1 << 4) /* B: PMC Programmable Clock Output 1 */ +#define AT91_PA5_NPCS2 (1 << 5) /* A: SPI Peripheral Chip Select 2 */ +#define AT91_PA5_TXD3 (1 << 5) /* B: USART Transmit Data 3 */ +#define AT91_PA6_NPCS3 (1 << 6) /* A: SPI Peripheral Chip Select 3 */ +#define AT91_PA6_RXD3 (1 << 6) /* B: USART Receive Data 3 */ +#define AT91_PA7_ETXCK_EREFCK (1 << 7) /* A: Ethernet Reference Clock / Transmit Clock */ +#define AT91_PA7_PCK2 (1 << 7) /* B: PMC Programmable Clock Output 2 */ +#define AT91_PA8_ETXEN (1 << 8) /* A: Ethernet Transmit Enable */ +#define AT91_PA8_MCCDB (1 << 8) /* B: MMC Multimedia Card B Command */ +#define AT91_PA9_ETX0 (1 << 9) /* A: Ethernet Transmit Data 0 */ +#define AT91_PA9_MCDB0 (1 << 9) /* B: MMC Multimedia Card B Data 0 */ +#define AT91_PA10_ETX1 (1 << 10) /* A: Ethernet Transmit Data 1 */ +#define AT91_PA10_MCDB1 (1 << 10) /* B: MMC Multimedia Card B Data 1 */ +#define AT91_PA11_ECRS_ECRSDV (1 << 11) /* A: Ethernet Carrier Sense / Data Valid */ +#define AT91_PA11_MCDB2 (1 << 11) /* B: MMC Multimedia Card B Data 2 */ +#define AT91_PA12_ERX0 (1 << 12) /* A: Ethernet Receive Data 0 */ +#define AT91_PA12_MCDB3 (1 << 12) /* B: MMC Multimedia Card B Data 3 */ +#define AT91_PA13_ERX1 (1 << 13) /* A: Ethernet Receive Data 1 */ +#define AT91_PA13_TCLK0 (1 << 13) /* B: TC External Clock Input 0 */ +#define AT91_PA14_ERXER (1 << 14) /* A: Ethernet Receive Error */ +#define AT91_PA14_TCLK1 (1 << 14) /* B: TC External Clock Input 1 */ +#define AT91_PA15_EMDC (1 << 15) /* A: Ethernet Management Data Clock */ +#define AT91_PA15_TCLK2 (1 << 15) /* B: TC External Clock Input 2 */ +#define AT91_PA16_EMDIO (1 << 16) /* A: Ethernet Management Data I/O */ +#define AT91_PA16_IRQ6 (1 << 16) /* B: External Interrupt 6 */ +#define AT91_PA17_TXD0 (1 << 17) /* A: USART Transmit Data 0 */ +#define AT91_PA17_TIOA0 (1 << 17) /* B: TC I/O Line A 0 */ +#define AT91_PA18_RXD0 (1 << 18) /* A: USART Receive Data 0 */ +#define AT91_PA18_TIOB0 (1 << 18) /* B: TC I/O Line B 0 */ +#define AT91_PA19_SCK0 (1 << 19) /* A: USART Serial Clock 0 */ +#define AT91_PA19_TIOA1 (1 << 19) /* B: TC I/O Line A 1 */ +#define AT91_PA20_CTS0 (1 << 20) /* A: USART Clear To Send 0 */ +#define AT91_PA20_TIOB1 (1 << 20) /* B: TC I/O Line B 1 */ +#define AT91_PA21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ +#define AT91_PA21_TIOA2 (1 << 21) /* B: TC I/O Line A 2 */ +#define AT91_PA22_RXD2 (1 << 22) /* A: USART Receive Data 2 */ +#define AT91_PA22_TIOB2 (1 << 22) /* B: TC I/O Line B 2 */ +#define AT91_PA23_TXD2 (1 << 23) /* A: USART Transmit Data 2 */ +#define AT91_PA23_IRQ3 (1 << 23) /* B: External Interrupt 3 */ +#define AT91_PA24_SCK2 (1 << 24) /* A: USART Serial Clock 2 */ +#define AT91_PA24_PCK1 (1 << 24) /* B: PMC Programmable Clock Output 1 */ +#define AT91_PA25_TWD (1 << 25) /* A: TWI Two-wire Serial Data */ +#define AT91_PA25_IRQ2 (1 << 25) /* B: External Interrupt 2 */ +#define AT91_PA26_TWCK (1 << 26) /* A: TWI Two-wire Serial Clock */ +#define AT91_PA26_IRQ1 (1 << 26) /* B: External Interrupt 1 */ +#define AT91_PA27_MCCK (1 << 27) /* A: MMC Multimedia Card Clock */ +#define AT91_PA27_TCLK3 (1 << 27) /* B: TC External Clock Input 3 */ +#define AT91_PA28_MCCDA (1 << 28) /* A: MMC Multimedia Card A Command */ +#define AT91_PA28_TCLK4 (1 << 28) /* B: TC External Clock Input 4 */ +#define AT91_PA29_MCDA0 (1 << 29) /* A: MMC Multimedia Card A Data 0 */ +#define AT91_PA29_TCLK5 (1 << 29) /* B: TC External Clock Input 5 */ +#define AT91_PA30_DRXD (1 << 30) /* A: DBGU Receive Data */ +#define AT91_PA30_CTS2 (1 << 30) /* B: USART Clear To Send 2 */ +#define AT91_PA31_DTXD (1 << 31) /* A: DBGU Transmit Data */ +#define AT91_PA31_RTS2 (1 << 31) /* B: USART Ready To Send 2 */ + +#define AT91_PB0_TF0 (1 << 0) /* A: SSC Transmit Frame Sync 0 */ +#define AT91_PB0_RTS3 (1 << 0) /* B: USART Ready To Send 3 */ +#define AT91_PB1_TK0 (1 << 1) /* A: SSC Transmit Clock 0 */ +#define AT91_PB1_CTS3 (1 << 1) /* B: USART Clear To Send 3 */ +#define AT91_PB2_TD0 (1 << 2) /* A: SSC Transmit Data 0 */ +#define AT91_PB2_SCK3 (1 << 2) /* B: USART Serial Clock 3 */ +#define AT91_PB3_RD0 (1 << 3) /* A: SSC Receive Data 0 */ +#define AT91_PB3_MCDA1 (1 << 3) /* B: MMC Multimedia Card A Data 1 */ +#define AT91_PB4_RK0 (1 << 4) /* A: SSC Receive Clock 0 */ +#define AT91_PB4_MCDA2 (1 << 4) /* B: MMC Multimedia Card A Data 2 */ +#define AT91_PB5_RF0 (1 << 5) /* A: SSC Receive Frame Sync 0 */ +#define AT91_PB5_MCDA3 (1 << 5) /* B: MMC Multimedia Card A Data 3 */ +#define AT91_PB6_TF1 (1 << 6) /* A: SSC Transmit Frame Sync 1 */ +#define AT91_PB6_TIOA3 (1 << 6) /* B: TC I/O Line A 3 */ +#define AT91_PB7_TK1 (1 << 7) /* A: SSC Transmit Clock 1 */ +#define AT91_PB7_TIOB3 (1 << 7) /* B: TC I/O Line B 3 */ +#define AT91_PB8_TD1 (1 << 8) /* A: SSC Transmit Data 1 */ +#define AT91_PB8_TIOA4 (1 << 8) /* B: TC I/O Line A 4 */ +#define AT91_PB9_RD1 (1 << 9) /* A: SSC Receive Data 1 */ +#define AT91_PB9_TIOB4 (1 << 9) /* B: TC I/O Line B 4 */ +#define AT91_PB10_RK1 (1 << 10) /* A: SSC Receive Clock 1 */ +#define AT91_PB10_TIOA5 (1 << 10) /* B: TC I/O Line A 5 */ +#define AT91_PB11_RF1 (1 << 11) /* A: SSC Receive Frame Sync 1 */ +#define AT91_PB11_TIOB5 (1 << 11) /* B: TC I/O Line B 5 */ +#define AT91_PB12_TF2 (1 << 12) /* A: SSC Transmit Frame Sync 2 */ +#define AT91_PB12_ETX2 (1 << 12) /* B: Ethernet Transmit Data 2 */ +#define AT91_PB13_TK2 (1 << 13) /* A: SSC Transmit Clock 3 */ +#define AT91_PB13_ETX3 (1 << 13) /* B: Ethernet Transmit Data 3 */ +#define AT91_PB14_TD2 (1 << 14) /* A: SSC Transmit Data 2 */ +#define AT91_PB14_ETXER (1 << 14) /* B: Ethernet Transmit Coding Error */ +#define AT91_PB15_RD2 (1 << 15) /* A: SSC Receive Data 2 */ +#define AT91_PB15_ERX2 (1 << 15) /* B: Ethernet Receive Data 2 */ +#define AT91_PB16_RK2 (1 << 16) /* A: SSC Receive Clock 2 */ +#define AT91_PB16_ERX3 (1 << 16) /* B: Ethernet Receive Data 3 */ +#define AT91_PB17_RF2 (1 << 17) /* A: SSC Receive Frame Sync 2 */ +#define AT91_PB17_ERXDV (1 << 17) /* B: Ethernet Receive Data Valid */ +#define AT91_PB18_RI1 (1 << 18) /* A: USART Ring Indicator 1 */ +#define AT91_PB18_ECOL (1 << 18) /* B: Ethernet Collision Detected */ +#define AT91_PB19_DTR1 (1 << 19) /* A: USART Data Terminal Ready 1 */ +#define AT91_PB19_ERXCK (1 << 19) /* B: Ethernet Receive Clock */ +#define AT91_PB20_TXD1 (1 << 20) /* A: USART Transmit Data 1 */ +#define AT91_PB21_RXD1 (1 << 21) /* A: USART Receive Data 1 */ +#define AT91_PB22_SCK1 (1 << 22) /* A: USART Serial Clock 1 */ +#define AT91_PB23_DCD1 (1 << 23) /* A: USART Data Carrier Detect 1 */ +#define AT91_PB24_CTS1 (1 << 24) /* A: USART Clear To Send 1 */ +#define AT91_PB25_DSR1 (1 << 25) /* A: USART Data Set Ready 1 */ +#define AT91_PB25_EF100 (1 << 25) /* B: Ethernet Force 100 Mbit */ +#define AT91_PB26_RTS1 (1 << 26) /* A: USART Ready To Send 1 */ +#define AT91_PB27_PCK0 (1 << 27) /* B: PMC Programmable Clock Output 0 */ +#define AT91_PB28_FIQ (1 << 28) /* A: Fast Interrupt */ +#define AT91_PB29_IRQ0 (1 << 29) /* A: External Interrupt 0 */ + +#define AT91_PC0_BFCK (1 << 0) /* A: Burst Flash Clock */ +#define AT91_PC1_BFRDY_SMOE (1 << 1) /* A: Burst Flash Ready / SmartMedia Output Enable */ +#define AT91_PC2_BFAVD (1 << 2) /* A: Burst Flash Address Valid */ +#define AT91_PC3_BFBAA_SMWE (1 << 3) /* A: Burst Flash Address Advance / SmartMedia Write Enable */ +#define AT91_PC4_BFOE (1 << 4) /* A: Burst Flash Output Enable */ +#define AT91_PC5_BFWE (1 << 5) /* A: Burst Flash Write Enable */ +#define AT91_PC6_NWAIT (1 << 6) /* A: SMC Wait Signal */ +#define AT91_PC7_A23 (1 << 7) /* A: Address Bus 23 */ +#define AT91_PC8_A24 (1 << 8) /* A: Address Bus 24 */ +#define AT91_PC9_A25_CFRNW (1 << 9) /* A: Address Bus 25 / Compact Flash Read Not Write */ +#define AT91_PC10_NCS4_CFCS (1 << 10) /* A: SMC Chip Select 4 / Compact Flash Chip Select */ +#define AT91_PC11_NCS5_CFCE1 (1 << 11) /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */ +#define AT91_PC12_NCS6_CFCE2 (1 << 12) /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */ +#define AT91_PC13_NCS7 (1 << 13) /* A: Chip Select 7 */ + +#define AT91_PD0_ETX0 (1 << 0) /* A: Ethernet Transmit Data 0 */ +#define AT91_PD1_ETX1 (1 << 1) /* A: Ethernet Transmit Data 1 */ +#define AT91_PD2_ETX2 (1 << 2) /* A: Ethernet Transmit Data 2 */ +#define AT91_PD3_ETX3 (1 << 3) /* A: Ethernet Transmit Data 3 */ +#define AT91_PD4_ETXEN (1 << 4) /* A: Ethernet Transmit Enable */ +#define AT91_PD5_ETXER (1 << 5) /* A: Ethernet Transmit Coding Error */ +#define AT91_PD6_DTXD (1 << 6) /* A: DBGU Transmit Data */ +#define AT91_PD7_PCK0 (1 << 7) /* A: PMC Programmable Clock Output 0 */ +#define AT91_PD7_TSYNC (1 << 7) /* B: ETM Trace Synchronization Signal */ +#define AT91_PD8_PCK1 (1 << 8) /* A: PMC Programmable Clock Output 1 */ +#define AT91_PD8_TCLK (1 << 8) /* B: ETM Trace Clock */ +#define AT91_PD9_PCK2 (1 << 9) /* A: PMC Programmable Clock Output 2 */ +#define AT91_PD9_TPS0 (1 << 9) /* B: ETM Trace ARM Pipeline Status 0 */ +#define AT91_PD10_PCK3 (1 << 10) /* A: PMC Programmable Clock Output 3 */ +#define AT91_PD10_TPS1 (1 << 10) /* B: ETM Trace ARM Pipeline Status 1 */ +#define AT91_PD11_TPS2 (1 << 11) /* B: ETM Trace ARM Pipeline Status 2 */ +#define AT91_PD12_TPK0 (1 << 12) /* B: ETM Trace Packet Port 0 */ +#define AT91_PD13_TPK1 (1 << 13) /* B: ETM Trace Packet Port 1 */ +#define AT91_PD14_TPK2 (1 << 14) /* B: ETM Trace Packet Port 2 */ +#define AT91_PD15_TD0 (1 << 15) /* A: SSC Transmit Data 0 */ +#define AT91_PD15_TPK3 (1 << 15) /* B: ETM Trace Packet Port 3 */ +#define AT91_PD16_TD1 (1 << 16) /* A: SSC Transmit Data 1 */ +#define AT91_PD16_TPK4 (1 << 16) /* B: ETM Trace Packet Port 4 */ +#define AT91_PD17_TD2 (1 << 17) /* A: SSC Transmit Data 2 */ +#define AT91_PD17_TPK5 (1 << 17) /* B: ETM Trace Packet Port 5 */ +#define AT91_PD18_NPCS1 (1 << 18) /* A: SPI Peripheral Chip Select 1 */ +#define AT91_PD18_TPK6 (1 << 18) /* B: ETM Trace Packet Port 6 */ +#define AT91_PD19_NPCS2 (1 << 19) /* A: SPI Peripheral Chip Select 2 */ +#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */ +#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */ +#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */ +#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ +#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */ +#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */ +#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */ +#define AT91_PD23_RTS2 (1 << 23) /* A: USART Ready To Send 2 */ +#define AT91_PD23_TPK11 (1 << 23) /* B: ETM Trace Packet Port 11 */ +#define AT91_PD24_RTS3 (1 << 24) /* A: USART Ready To Send 3 */ +#define AT91_PD24_TPK12 (1 << 24) /* B: ETM Trace Packet Port 12 */ +#define AT91_PD25_DTR1 (1 << 25) /* A: USART Data Terminal Ready 1 */ +#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */ +#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */ +#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */ + +#endif diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h new file mode 100644 index 00000000000..9bfffdbf1e0 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h @@ -0,0 +1,328 @@ +/* + * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91RM9200_SYS_H +#define AT91RM9200_SYS_H + +/* + * Advanced Interrupt Controller. + */ +#define AT91_AIC 0x000 + +#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ +#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ +#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ +#define AT91_AIC_SRCTYPE_LOW (0 << 5) +#define AT91_AIC_SRCTYPE_FALLING (1 << 5) +#define AT91_AIC_SRCTYPE_HIGH (2 << 5) +#define AT91_AIC_SRCTYPE_RISING (3 << 5) + +#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ +#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ +#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ +#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ +#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ + +#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ +#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ +#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ +#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ +#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ + +#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ +#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ +#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ +#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ +#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ +#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ +#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ +#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ +#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ + + +/* + * Debug Unit. + */ +#define AT91_DBGU 0x200 + +#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ +#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ +#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ +#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ +#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ +#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ +#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ +#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ +#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ +#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ +#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ +#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ +#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ + + +/* + * PIO Controllers. + */ +#define AT91_PIOA 0x400 +#define AT91_PIOB 0x600 +#define AT91_PIOC 0x800 +#define AT91_PIOD 0xa00 + +#define PIO_PER 0x00 /* Enable Register */ +#define PIO_PDR 0x04 /* Disable Register */ +#define PIO_PSR 0x08 /* Status Register */ +#define PIO_OER 0x10 /* Output Enable Register */ +#define PIO_ODR 0x14 /* Output Disable Register */ +#define PIO_OSR 0x18 /* Output Status Register */ +#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ +#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ +#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ +#define PIO_SODR 0x30 /* Set Output Data Register */ +#define PIO_CODR 0x34 /* Clear Output Data Register */ +#define PIO_ODSR 0x38 /* Output Data Status Register */ +#define PIO_PDSR 0x3c /* Pin Data Status Register */ +#define PIO_IER 0x40 /* Interrupt Enable Register */ +#define PIO_IDR 0x44 /* Interrupt Disable Register */ +#define PIO_IMR 0x48 /* Interrupt Mask Register */ +#define PIO_ISR 0x4c /* Interrupt Status Register */ +#define PIO_MDER 0x50 /* Multi-driver Enable Register */ +#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ +#define PIO_MDSR 0x58 /* Multi-driver Status Register */ +#define PIO_PUDR 0x60 /* Pull-up Disable Register */ +#define PIO_PUER 0x64 /* Pull-up Enable Register */ +#define PIO_PUSR 0x68 /* Pull-up Status Register */ +#define PIO_ASR 0x70 /* Peripheral A Select Register */ +#define PIO_BSR 0x74 /* Peripheral B Select Register */ +#define PIO_ABSR 0x78 /* AB Status Register */ +#define PIO_OWER 0xa0 /* Output Write Enable Register */ +#define PIO_OWDR 0xa4 /* Output Write Disable Register */ +#define PIO_OWSR 0xa8 /* Output Write Status Register */ + +#define AT91_PIO_P(n) (1 << (n)) + + +/* + * Power Management Controller. + */ +#define AT91_PMC 0xc00 + +#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ +#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ + +#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ +#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ +#define AT91_PMC_UDP (1 << 1) /* USB Devcice Port Clock */ +#define AT91_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend */ +#define AT91_PMC_UHP (1 << 4) /* USB Host Port Clock */ +#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ + +#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ +#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ +#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ + +#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ +#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ +#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ + +#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ +#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ +#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ + +#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ +#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ +#define AT91_PMC_DIV (0xff << 0) /* Divider */ +#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ +#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ +#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ +#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ + +#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ +#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ +#define AT91_PMC_CSS_SLOW (0 << 0) +#define AT91_PMC_CSS_MAIN (1 << 0) +#define AT91_PMC_CSS_PLLA (2 << 0) +#define AT91_PMC_CSS_PLLB (3 << 0) +#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ +#define AT91_PMC_PRES_1 (0 << 2) +#define AT91_PMC_PRES_2 (1 << 2) +#define AT91_PMC_PRES_4 (2 << 2) +#define AT91_PMC_PRES_8 (3 << 2) +#define AT91_PMC_PRES_16 (4 << 2) +#define AT91_PMC_PRES_32 (5 << 2) +#define AT91_PMC_PRES_64 (6 << 2) +#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ +#define AT91_PMC_MDIV_1 (0 << 8) +#define AT91_PMC_MDIV_2 (1 << 8) +#define AT91_PMC_MDIV_3 (2 << 8) +#define AT91_PMC_MDIV_4 (3 << 8) + +#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ +#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ +#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ +#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ +#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ +#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ +#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ +#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ + + +/* + * System Timer. + */ +#define AT91_ST 0xd00 + +#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ +#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ +#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ +#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ +#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ +#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ +#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ +#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ +#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ +#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ +#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ +#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ +#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ +#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ +#define AT91_ST_ALMS (1 << 3) /* Alarm Status */ +#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ +#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ +#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ +#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ +#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ +#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ +#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ + + +/* + * Real-time Clock. + */ +#define AT91_RTC 0xe00 + +#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ +#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ +#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ +#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ +#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) +#define AT91_RTC_TIMEVSEL_HOUR (1 << 8) +#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) +#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) +#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ +#define AT91_RTC_CALEVSEL_WEEK (0 << 16) +#define AT91_RTC_CALEVSEL_MONTH (1 << 16) +#define AT91_RTC_CALEVSEL_YEAR (2 << 16) + +#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ +#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ + +#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ +#define AT91_RTC_SEC (0x7f << 0) /* Current Second */ +#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ +#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ +#define At91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ + +#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ +#define AT91_RTC_CENT (0x7f << 0) /* Current Century */ +#define AT91_RTC_YEAR (0xff << 8) /* Current Year */ +#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ +#define AT91_RTC_DAY (7 << 21) /* Current Day */ +#define AT91_RTC_DATE (0x3f << 24) /* Current Date */ + +#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ +#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ +#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ +#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ + +#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ +#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ +#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ + +#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ +#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ +#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ +#define AT91_RTC_SECEV (1 << 2) /* Second Event */ +#define AT91_RTC_TIMEV (1 << 3) /* Time Event */ +#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ + +#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ +#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ +#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ +#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ + +#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ +#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ +#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ +#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ +#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ + + +/* + * Memory Controller. + */ +#define AT91_MC 0xf00 + +#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ +#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ + +#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ +#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ +#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ + +/* External Bus Interface (EBI) registers */ +#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ +#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ +#define AT91_EBI_CS0A_SMC (0 << 0) +#define AT91_EBI_CS0A_BFC (1 << 0) +#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_EBI_CS1A_SMC (0 << 1) +#define AT91_EBI_CS1A_SDRAMC (1 << 1) +#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ +#define AT91_EBI_CS3A_SMC (0 << 3) +#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ +#define AT91_EBI_CS4A_SMC (0 << 4) +#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) +#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ +#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ + +/* Static Memory Controller (SMC) registers */ +#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ +#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ +#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ +#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ +#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ +#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ +#define AT91_SMC_DBW_16 (1 << 13) +#define AT91_SMC_DBW_8 (2 << 13) +#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ +#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ +#define AT91_SMC_ACSS_STD (0 << 16) +#define AT91_SMC_ACSS_1 (1 << 16) +#define AT91_SMC_ACSS_2 (2 << 16) +#define AT91_SMC_ACSS_3 (3 << 16) +#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ +#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ + + +#endif diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h new file mode 100644 index 00000000000..2e7d1139a79 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/board.h @@ -0,0 +1,80 @@ +/* + * include/asm-arm/arch-at91rm9200/board.h + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * These are data structures found in platform_device.dev.platform_data, + * and describing board-specfic data needed by drivers. For example, + * which pin is used for a given GPIO role. + * + * In 2.6, drivers should strongly avoid board-specific knowledge so + * that supporting new boards normally won't require driver patches. + * Most board-specific knowledge should be in arch/.../board-*.c files. + */ + +#ifndef __ASM_ARCH_BOARD_H +#define __ASM_ARCH_BOARD_H + + /* Clocks */ +extern unsigned long at91_master_clock; + + /* Serial Port */ +extern int at91_serial_map[AT91_NR_UART]; +extern int at91_console_port; + + /* USB Device */ +struct at91_udc_data { + u8 vbus_pin; /* high == host powering us */ + u8 pullup_pin; /* high == D+ pulled up */ +}; +extern void __init at91_add_device_udc(struct at91_udc_data *data); + + /* Compact Flash */ +struct at91_cf_data { + u8 irq_pin; /* I/O IRQ */ + u8 det_pin; /* Card detect */ + u8 vcc_pin; /* power switching */ + u8 rst_pin; /* card reset */ +}; +extern void __init at91_add_device_cf(struct at91_cf_data *data); + + /* MMC / SD */ +struct at91_mmc_data { + u8 det_pin; /* card detect IRQ */ + unsigned is_b:1; /* uses B side (vs A) */ + unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ + u8 wp_pin; /* (SD) writeprotect detect */ + u8 vcc_pin; /* power switching (high == on) */ +}; +extern void __init at91_add_device_mmc(struct at91_mmc_data *data); + + /* Ethernet */ +struct at91_eth_data { + u8 phy_irq_pin; /* PHY IRQ */ + u8 is_rmii; /* using RMII interface? */ +}; +extern void __init at91_add_device_eth(struct at91_eth_data *data); + + /* USB Host */ +struct at91_usbh_data { + u8 ports; /* number of ports on root hub */ +}; +extern void __init at91_add_device_usbh(struct at91_usbh_data *data); + +#endif diff --git a/include/asm-arm/arch-at91rm9200/debug-macro.S b/include/asm-arm/arch-at91rm9200/debug-macro.S new file mode 100644 index 00000000000..f496b54c4c3 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/debug-macro.S @@ -0,0 +1,38 @@ +/* + * include/asm-arm/arch-at91rm9200/debug-macro.S + * + * Copyright (C) 2003-2005 SAN People + * + * Debugging macro include header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include <asm/hardware.h> + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =AT91_BASE_SYS @ System peripherals (phys address) + ldrne \rx, =AT91_VA_BASE_SYS @ System peripherals (virt address) + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #AT91_DBGU_THR] @ Write to Transmitter Holding Register + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register + tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit + beq 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register + tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete + beq 1001b + .endm + diff --git a/include/asm-arm/arch-epxa10db/param.h b/include/asm-arm/arch-at91rm9200/dma.h index 783dedd71c8..22c1dfdd8da 100644 --- a/include/asm-arm/arch-epxa10db/param.h +++ b/include/asm-arm/arch-at91rm9200/dma.h @@ -1,7 +1,7 @@ /* - * linux/include/asm-arm/arch-epxa10db/param.h + * include/asm-arm/arch-at91rm9200/dma.h * - * Copyright (C) 1999 ARM Limited + * Copyright (C) 2003 SAN People * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S new file mode 100644 index 00000000000..61a326e9490 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/entry-macro.S @@ -0,0 +1,25 @@ +/* + * include/asm-arm/arch-at91rm9200/entry-macro.S + * + * Copyright (C) 2003-2005 SAN People + * + * Low-level IRQ helper macros for AT91RM9200 platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/hardware.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =(AT91_VA_BASE_SYS) @ base virtual address of SYS peripherals + ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) + ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number + teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt + streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now. + .endm + diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h new file mode 100644 index 00000000000..0f0a61e2f12 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/gpio.h @@ -0,0 +1,193 @@ +/* + * include/asm-arm/arch-at91rm9200/gpio.h + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_AT91RM9200_GPIO_H +#define __ASM_ARCH_AT91RM9200_GPIO_H + +#define PIN_BASE NR_AIC_IRQS + +#define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */ +#define BGA_GPIO_BANKS 4 /* BGA package has 4 banks */ + +/* these pin numbers double as IRQ numbers, like AT91_ID_* values */ + +#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) +#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) +#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) +#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) +#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) + +#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) +#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) +#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) +#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) +#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) + +#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) +#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) +#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) +#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) +#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) + +#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) +#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) +#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) +#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) +#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) + +#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) +#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) +#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) +#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) +#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) + +#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) +#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) +#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) +#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) +#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) + +#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) +#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) + +#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) +#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) +#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) +#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) +#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) + +#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) +#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) +#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) +#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) +#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) + +#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) +#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) +#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) +#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) +#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) + +#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) +#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) +#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) +#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) +#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) + +#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) +#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) +#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) +#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) +#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) + +#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) +#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) +#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) +#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) +#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) + +#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) +#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) + +#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) +#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) +#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) +#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) +#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) + +#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) +#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) +#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) +#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) +#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) + +#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) +#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) +#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) +#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) +#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) + +#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) +#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) +#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) +#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) +#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) + +#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) +#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) +#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) +#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) +#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) + +#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) +#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) +#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) +#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) +#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) + +#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) +#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) + +#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) +#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) +#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) +#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) +#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) + +#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) +#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) +#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) +#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) +#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) + +#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) +#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) +#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) +#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) +#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) + +#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) +#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) +#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) +#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) +#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) + +#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) +#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) +#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) +#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) +#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) + +#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) +#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) +#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) +#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) +#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) + +#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) +#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) + +#ifndef __ASSEMBLY__ +/* setup setup routines, called from board init or driver probe() */ +extern int at91_set_A_periph(unsigned pin, int use_pullup); +extern int at91_set_B_periph(unsigned pin, int use_pullup); +extern int at91_set_gpio_input(unsigned pin, int use_pullup); +extern int at91_set_gpio_output(unsigned pin, int value); +extern int at91_set_deglitch(unsigned pin, int is_on); + +/* callable at any time */ +extern int at91_set_gpio_value(unsigned pin, int value); +extern int at91_get_gpio_value(unsigned pin); +#endif + +#endif + diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h new file mode 100644 index 00000000000..2646c01f8e9 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/hardware.h @@ -0,0 +1,92 @@ +/* + * include/asm-arm/arch-at91rm9200/hardware.h + * + * Copyright (C) 2003 SAN People + * Copyright (C) 2003 ATMEL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> + +#include <asm/arch/at91rm9200.h> +#include <asm/arch/at91rm9200_sys.h> + +/* + * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF + * to 0xFEFA0000 .. 0xFF000000. (384Kb) + */ +#define AT91_IO_PHYS_BASE 0xFFFA0000 +#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) +#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) + + /* Convert a physical IO address to virtual IO address */ +#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) + +/* + * Virtual to Physical Address mapping for IO devices. + */ +#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) +#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91_BASE_SPI) +#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91_BASE_SSC2) +#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91_BASE_SSC1) +#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91_BASE_SSC0) +#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91_BASE_US3) +#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91_BASE_US2) +#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91_BASE_US1) +#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91_BASE_US0) +#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91_BASE_EMAC) +#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91_BASE_TWI) +#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91_BASE_MCI) +#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91_BASE_UDP) +#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91_BASE_TCB1) +#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91_BASE_TCB0) + +/* Internal SRAM */ +#define AT91_BASE_SRAM 0x00200000 /* Internal SRAM base address */ +#define AT91_SRAM_SIZE 0x00004000 /* Internal SRAM SIZE (16Kb) */ + +/* Serial ports */ +#define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */ + +/* FLASH */ +#define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */ + +/* SDRAM */ +#define AT91_SDRAM_BASE 0x20000000 /* NCS1: SDRAM physical base address */ + +/* SmartMedia */ +#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3: Smartmedia physical base address */ + +/* Multi-Master Memory controller */ +#define AT91_UHP_BASE 0x00300000 /* USB Host controller */ + +/* Clocks */ +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#ifndef __ASSEMBLY__ +#include <asm/io.h> + +static inline unsigned int at91_sys_read(unsigned int reg_offset) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + return readl(addr + reg_offset); +} + +static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + writel(value, addr + reg_offset); +} +#endif + +#endif diff --git a/include/asm-arm/arch-at91rm9200/io.h b/include/asm-arm/arch-at91rm9200/io.h new file mode 100644 index 00000000000..23e670d85c9 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/io.h @@ -0,0 +1,33 @@ +/* + * include/asm-arm/arch-at91rm9200/io.h + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include <asm/arch/at91rm9200.h> +#include <asm/io.h> + +#define IO_SPACE_LIMIT 0xFFFFFFFF + +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) + + +#endif diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h new file mode 100644 index 00000000000..27b0497f1b3 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/irqs.h @@ -0,0 +1,52 @@ +/* + * include/asm-arm/arch-at91rm9200/irqs.h + * + * Copyright (C) 2004 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#define NR_AIC_IRQS 32 + + +/* + * Acknowledge interrupt with AIC after interrupt has been handled. + * (by kernel/irq.c) + */ +#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0) + + +/* + * IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h + * for IRQs handled directly through the AIC, or else the AT91_PIN_* + * symbols in gpio.h for ones handled indirectly as GPIOs. + * We make provision for 4 banks of GPIO. + */ +#include <asm/arch/gpio.h> + +#define NR_IRQS (NR_AIC_IRQS + (4 * 32)) + + +#ifndef __ASSEMBLY__ +/* + * Initialize the IRQ controller. + */ +extern void at91rm9200_init_irq(unsigned int priority[]); +#endif + +#endif diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-at91rm9200/memory.h index 999541b6a9f..462f1f0ad67 100644 --- a/include/asm-arm/arch-epxa10db/memory.h +++ b/include/asm-arm/arch-at91rm9200/memory.h @@ -1,7 +1,7 @@ /* - * linux/include/asm-arm/arch-epxa10/memory.h + * include/asm-arm/arch-at91rm9200/memory.h * - * Copyright (C) 2001 Altera Corporation + * Copyright (C) 2004 SAN People * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,13 +17,14 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -/* - * Physical DRAM offset. - */ -#define PHYS_OFFSET UL(0x00000000) +#include <asm/arch/hardware.h> + +#define PHYS_OFFSET (AT91_SDRAM_BASE) + /* * Virtual view <-> DMA view memory address translations @@ -32,7 +33,9 @@ * bus_to_virt: Used to convert an address for DMA operations * to an address that the kernel can use. */ -#define __virt_to_bus(x) (x - PAGE_OFFSET + /*SDRAM_BASE*/0) -#define __bus_to_virt(x) (x - /*SDRAM_BASE*/0 + PAGE_OFFSET) +#define __virt_to_bus__is_a_macro +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt__is_a_macro +#define __bus_to_virt(x) __phys_to_virt(x) #endif diff --git a/include/asm-arm/arch-epxa10db/dma.h b/include/asm-arm/arch-at91rm9200/param.h index de20ec8e74b..9480f844685 100644 --- a/include/asm-arm/arch-epxa10db/dma.h +++ b/include/asm-arm/arch-at91rm9200/param.h @@ -1,7 +1,7 @@ /* - * linux/include/asm-arm/arch-camelot/dma.h + * include/asm-arm/arch-at91rm9200/param.h * - * Copyright (C) 1997,1998 Russell King + * Copyright (C) 2003 SAN People * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,3 +17,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +#ifndef __ASM_ARCH_PARAM_H +#define __ASM_ARCH_PARAM_H + +/* + * We use default params + */ + +#endif diff --git a/include/asm-arm/arch-at91rm9200/pio.h b/include/asm-arm/arch-at91rm9200/pio.h new file mode 100644 index 00000000000..a89501b4a70 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/pio.h @@ -0,0 +1,115 @@ +/* + * include/asm-arm/arch-at91rm9200/pio.h + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_PIO_H +#define __ASM_ARCH_PIO_H + +#include <asm/arch/hardware.h> + +static inline void AT91_CfgPIO_USART0(void) { + at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA17_TXD0 | AT91_PA18_RXD0 | AT91_PA20_CTS0); + + /* + * Errata #39 - RTS0 is not internally connected to PA21. We need to drive + * the pin manually. Default is off (RTS is active low). + */ + at91_sys_write(AT91_PIOA + PIO_PER, AT91_PA21_RTS0); + at91_sys_write(AT91_PIOA + PIO_OER, AT91_PA21_RTS0); + at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0); +} + +static inline void AT91_CfgPIO_USART1(void) { + at91_sys_write(AT91_PIOB + PIO_PDR, AT91_PB18_RI1 | AT91_PB19_DTR1 + | AT91_PB20_TXD1 | AT91_PB21_RXD1 | AT91_PB23_DCD1 + | AT91_PB24_CTS1 | AT91_PB25_DSR1 | AT91_PB26_RTS1); +} + +static inline void AT91_CfgPIO_USART2(void) { + at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA22_RXD2 | AT91_PA23_TXD2); +} + +static inline void AT91_CfgPIO_USART3(void) { + at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_TXD3 | AT91_PA6_RXD3); + at91_sys_write(AT91_PIOA + PIO_BSR, AT91_PA5_TXD3 | AT91_PA6_RXD3); +} + +static inline void AT91_CfgPIO_DBGU(void) { + at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA31_DTXD | AT91_PA30_DRXD); +} + +/* + * Enable the Two-Wire interface. + */ +static inline void AT91_CfgPIO_TWI(void) { + at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA25_TWD | AT91_PA26_TWCK); + at91_sys_write(AT91_PIOA + PIO_ASR, AT91_PA25_TWD | AT91_PA26_TWCK); + at91_sys_write(AT91_PIOA + PIO_MDER, AT91_PA25_TWD | AT91_PA26_TWCK); /* open drain */ +} + +/* + * Enable the Serial Peripheral Interface. + */ +static inline void AT91_CfgPIO_SPI(void) { + at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA0_MISO | AT91_PA1_MOSI | AT91_PA2_SPCK); +} + +static inline void AT91_CfgPIO_SPI_CS0(void) { + at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA3_NPCS0); +} + +static inline void AT91_CfgPIO_SPI_CS1(void) { + at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA4_NPCS1); +} + +static inline void AT91_CfgPIO_SPI_CS2(void) { + at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_NPCS2); +} + +static inline void AT91_CfgPIO_SPI_CS3(void) { + at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA6_NPCS3); +} + +/* + * Select the DataFlash card. + */ +static inline void AT91_CfgPIO_DataFlashCard(void) { + at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(7)); + at91_sys_write(AT91_PIOB + PIO_OER, AT91_PIO_P(7)); + at91_sys_write(AT91_PIOB + PIO_CODR, AT91_PIO_P(7)); +} + +/* + * Enable NAND Flash (SmartMedia) interface. + */ +static inline void AT91_CfgPIO_SmartMedia(void) { + /* enable PC0=SMCE, PC1=SMOE, PC3=SMWE, A21=CLE, A22=ALE */ + at91_sys_write(AT91_PIOC + PIO_ASR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE); + at91_sys_write(AT91_PIOC + PIO_PDR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE); + + /* Configure PC2 as input (signal READY of the SmartMedia) */ + at91_sys_write(AT91_PIOC + PIO_PER, AT91_PC2_BFAVD); /* enable direct output enable */ + at91_sys_write(AT91_PIOC + PIO_ODR, AT91_PC2_BFAVD); /* disable output */ + + /* Configure PB1 as input (signal Card Detect of the SmartMedia) */ + at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(1)); /* enable direct output enable */ + at91_sys_write(AT91_PIOB + PIO_ODR, AT91_PIO_P(1)); /* disable output */ +} + +static inline int AT91_PIO_SmartMedia_RDY(void) { + return (at91_sys_read(AT91_PIOC + PIO_PDSR) & AT91_PIO_P(2)) ? 1 : 0; +} + +static inline int AT91_PIO_SmartMedia_CardDetect(void) { + return (at91_sys_read(AT91_PIOB + PIO_PDSR) & AT91_PIO_P(1)) ? 1 : 0; +} + +#endif diff --git a/include/asm-arm/arch-epxa10db/system.h b/include/asm-arm/arch-at91rm9200/system.h index 345b092a1ed..29c42655f05 100644 --- a/include/asm-arm/arch-epxa10db/system.h +++ b/include/asm-arm/arch-at91rm9200/system.h @@ -1,9 +1,7 @@ /* - * linux/include/asm-arm/arch-epxa10db/system.h + * include/asm-arm/arch-at91rm9200/system.h * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2001 Altera Corporation + * Copyright (C) 2003 SAN People * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,23 +17,35 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H -#include <asm/arch/platform.h> +#include <asm/arch/hardware.h> static inline void arch_idle(void) { /* - * This should do all the clock switching - * and wait for interrupt tricks + * Disable the processor clock. The processor will be automatically + * re-enabled by an interrupt or by a reset. + */ +// at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); + + /* + * Set the processor (CP15) into 'Wait for Interrupt' mode. + * Unlike disabling the processor clock via the PMC (above) + * this allows the processor to be woken via JTAG. */ cpu_do_idle(); } -extern __inline__ void arch_reset(char mode) +static inline void arch_reset(char mode) { - /* Hmm... We can probably do something with the watchdog... */ + /* + * Perform a hardware reset with the use of the Watchdog timer. + */ + at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); + at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); } #endif diff --git a/include/asm-arm/arch-epxa10db/vmalloc.h b/include/asm-arm/arch-at91rm9200/timex.h index 546fb7d2b6a..3f112dd1258 100644 --- a/include/asm-arm/arch-epxa10db/vmalloc.h +++ b/include/asm-arm/arch-at91rm9200/timex.h @@ -1,7 +1,7 @@ /* - * linux/include/asm-arm/arch-epxa10db/vmalloc.h + * include/asm-arm/arch-at91rm9200/timex.h * - * Copyright (C) 2000 Russell King. + * Copyright (C) 2003 SAN People * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,4 +17,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +#include <asm/arch/hardware.h> + +#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) + +#endif diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h new file mode 100644 index 00000000000..b30dd552071 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/uncompress.h @@ -0,0 +1,55 @@ +/* + * include/asm-arm/arch-at91rm9200/uncompress.h + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include <asm/arch/hardware.h> + +/* + * The following code assumes the serial port has already been + * initialized by the bootloader. We search for the first enabled + * port in the most probable order. If you didn't setup a port in + * your bootloader then nothing will appear (which might be desired). + * + * This does not append a newline + */ +static void putstr(const char *s) +{ + void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ + + while (*s) { + while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); } + __raw_writel(*s, sys + AT91_DBGU_THR); + if (*s == '\n') { + while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); } + __raw_writel('\r', sys + AT91_DBGU_THR); + } + s++; + } + /* wait for transmission to complete */ + while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) { barrier(); } +} + +#define arch_decomp_setup() + +#define arch_decomp_wdog() + +#endif diff --git a/include/asm-arm/arch-epxa10db/timex.h b/include/asm-arm/arch-at91rm9200/vmalloc.h index b87a75fc958..34d9718feb9 100644 --- a/include/asm-arm/arch-epxa10db/timex.h +++ b/include/asm-arm/arch-at91rm9200/vmalloc.h @@ -1,9 +1,7 @@ /* - * linux/include/asm-arm/arch-epxa10db/timex.h + * include/asm-arm/arch-at91rm9200/vmalloc.h * - * Excalibur timex specifications - * - * Copyright (C) 2001 Altera Corporation + * Copyright (C) 2003 SAN People * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,7 +18,9 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -/* - * ?? - */ -#define CLOCK_TICK_RATE (50000000 / 16) +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (AT91_IO_VIRT_BASE & PGDIR_MASK) + +#endif diff --git a/include/asm-arm/arch-epxa10db/debug-macro.S b/include/asm-arm/arch-epxa10db/debug-macro.S deleted file mode 100644 index 1d11c51f498..00000000000 --- a/include/asm-arm/arch-epxa10db/debug-macro.S +++ /dev/null @@ -1,41 +0,0 @@ -/* linux/include/asm-arm/arch-epxa10db/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <asm/arch/excalibur.h> -#define UART00_TYPE -#include <asm/arch/uart00.h> - - .macro addruart,rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - ldr \rx, =EXC_UART00_BASE @ physical base address - orrne \rx, \rx, #0xff000000 @ virtual base - orrne \rx, \rx, #0x00f00000 - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #UART_TD(0)] - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #UART_TSR(0)] - and \rd, \rd, #UART_TSR_TX_LEVEL_MSK - cmp \rd, #15 - beq 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #UART_TSR(0)] - ands \rd, \rd, #UART_TSR_TX_LEVEL_MSK - bne 1001b - .endm diff --git a/include/asm-arm/arch-epxa10db/entry-macro.S b/include/asm-arm/arch-epxa10db/entry-macro.S deleted file mode 100644 index de6ae08334e..00000000000 --- a/include/asm-arm/arch-epxa10db/entry-macro.S +++ /dev/null @@ -1,25 +0,0 @@ -/* - * include/asm-arm/arch-epxa10db/entry-macro.S - * - * Low-level IRQ helper macros for epxa10db platform - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <asm/arch/platform.h> -#undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */ -#include <asm/arch/int_ctrl00.h> - - .macro disable_fiq - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - ldr \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE)) - ldr \irqnr,[\irqstat] - cmp \irqnr,#0 - subne \irqnr,\irqnr,#1 - - .endm - diff --git a/include/asm-arm/arch-epxa10db/ether00.h b/include/asm-arm/arch-epxa10db/ether00.h deleted file mode 100644 index b737b8aabe2..00000000000 --- a/include/asm-arm/arch-epxa10db/ether00.h +++ /dev/null @@ -1,482 +0,0 @@ -#ifndef __ETHER00_H -#define __ETHER00_H - - - -/* - * Register definitions for the Ethernet MAC - */ - -/* - * Copyright (c) Altera Corporation 2000. - * All rights reserved. - */ - -/* -* Structures for the DMA controller -*/ -typedef struct fda_desc - { - struct fda_desc * FDNext; - long FDSystem; - long FDStat; - short FDLength; - short FDCtl; - }FDA_DESC; - -typedef struct buf_desc - { - char * BuffData; - short BuffLength; - char BDStat; - char BDCtl; - }BUF_DESC; - -/* -* Control masks for the DMA controller -*/ -#define FDCTL_BDCOUNT_MSK (0x1F) -#define FDCTL_BDCOUNT_OFST (0) -#define FDCTL_FRMOPT_MSK (0x7C00) -#define FDCTL_FRMOPT_OFST (10) -#define FDCTL_COWNSFD_MSK (0x8000) -#define FDCTL_COWNSFD_OFST (15) - -#define BDCTL_RXBDSEQN_MSK (0x7F) -#define BDCTL_RXBDSEQN_OFST (0) -#define BDCTL_COWNSBD_MSK (0x80) -#define BDCTL_COWNSBD_OFST (7) - -#define FDNEXT_EOL_MSK (0x1) -#define FDNEXT_EOL_OFST (0) -#define FDNEXT_EOL_POINTER_MSK (0xFFFFFFF0) -#define FDNEXT_EOL_POINTER_OFST (4) - -#define ETHER_ARC_SIZE (21) - -/* -* Register definitions and masks -*/ -#define ETHER_DMA_CTL(base) (ETHER00_TYPE (base + 0x100)) -#define ETHER_DMA_CTL_DMBURST_OFST (2) -#define ETHER_DMA_CTL_DMBURST_MSK (0x1FC) -#define ETHER_DMA_CTL_POWRMGMNT_OFST (11) -#define ETHER_DMA_CTL_POWRMGMNT_MSK (0x1000) -#define ETHER_DMA_CTL_TXBIGE_OFST (14) -#define ETHER_DMA_CTL_TXBIGE_MSK (0x4000) -#define ETHER_DMA_CTL_RXBIGE_OFST (15) -#define ETHER_DMA_CTL_RXBIGE_MSK (0x8000) -#define ETHER_DMA_CTL_TXWAKEUP_OFST (16) -#define ETHER_DMA_CTL_TXWAKEUP_MSK (0x10000) -#define ETHER_DMA_CTL_SWINTREQ_OFST (17) -#define ETHER_DMA_CTL_SWINTREQ_MSK (0x20000) -#define ETHER_DMA_CTL_INTMASK_OFST (18) -#define ETHER_DMA_CTL_INTMASK_MSK (0x40000) -#define ETHER_DMA_CTL_M66ENSTAT_OFST (19) -#define ETHER_DMA_CTL_M66ENSTAT_MSK (0x80000) -#define ETHER_DMA_CTL_RMTXINIT_OFST (20) -#define ETHER_DMA_CTL_RMTXINIT_MSK (0x100000) -#define ETHER_DMA_CTL_RMRXINIT_OFST (21) -#define ETHER_DMA_CTL_RMRXINIT_MSK (0x200000) -#define ETHER_DMA_CTL_RXALIGN_OFST (22) -#define ETHER_DMA_CTL_RXALIGN_MSK (0xC00000) -#define ETHER_DMA_CTL_RMSWRQ_OFST (24) -#define ETHER_DMA_CTL_RMSWRQ_MSK (0x1000000) -#define ETHER_DMA_CTL_RMEMBANK_OFST (25) -#define ETHER_DMA_CTL_RMEMBANK_MSK (0x2000000) - -#define ETHER_TXFRMPTR(base) (ETHER00_TYPE (base + 0x104)) - -#define ETHER_TXTHRSH(base) (ETHER00_TYPE (base + 0x308)) - -#define ETHER_TXPOLLCTR(base) (ETHER00_TYPE (base + 0x30c)) - -#define ETHER_BLFRMPTR(base) (ETHER00_TYPE (base + 0x110)) -#define ETHER_BLFFRMPTR_EOL_OFST (0) -#define ETHER_BLFFRMPTR_EOL_MSK (0x1) -#define ETHER_BLFFRMPTR_ADDRESS_OFST (4) -#define ETHER_BLFFRMPTR_ADDRESS_MSK (0xFFFFFFF0) - -#define ETHER_RXFRAGSIZE(base) (ETHER00_TYPE (base + 0x114)) -#define ETHER_RXFRAGSIZE_MINFRAG_OFST (2) -#define ETHER_RXFRAGSIZE_MINFRAG_MSK (0xFFC) -#define ETHER_RXFRAGSIZE_ENPACK_OFST (15) -#define ETHER_RXFRAGSIZE_ENPACK_MSK (0x8000) - -#define ETHER_INT_EN(base) (ETHER00_TYPE (base + 0x118)) -#define ETHER_INT_EN_FDAEXEN_OFST (0) -#define ETHER_INT_EN_FDAEXEN_MSK (0x1) -#define ETHER_INT_EN_BLEXEN_OFST (1) -#define ETHER_INT_EN_BLEXN_MSK (0x2) -#define ETHER_INT_EN_STARGABTEN_OFST (2) -#define ETHER_INT_EN_STARGABTEN_MSK (0x4) -#define ETHER_INT_EN_RTARGABTEN_OFST (3) -#define ETHER_INT_EN_RTARGABTEN_MSK (0x8) -#define ETHER_INT_EN_RMASABTEN_OFST (4) -#define ETHER_INT_EN_RMASABTEN_MSK (0x10) -#define ETHER_INT_EN_SSYSERREN_OFST (5) -#define ETHER_INT_EN_SSYSERREN_MSK (0x20) -#define ETHER_INT_EN_DPARERREN_OFST (6) -#define ETHER_INT_EN_DPARERREN_MSK (0x40) -#define ETHER_INT_EN_EARNOTEN_OFST (7) -#define ETHER_INT_EN_EARNOTEN_MSK (0x80) -#define ETHER_INT_EN_DPARDEN_OFST (8) -#define ETHER_INT_EN_DPARDEN_MSK (0x100) -#define ETHER_INT_EN_DMPARERREN_OFST (9) -#define ETHER_INT_EN_DMPARERREN_MSK (0x200) -#define ETHER_INT_EN_TXCTLCMPEN_OFST (10) -#define ETHER_INT_EN_TXCTLCMPEN_MSK (0x400) -#define ETHER_INT_EN_NRABTEN_OFST (11) -#define ETHER_INT_EN_NRABTEN_MSK (0x800) - -#define ETHER_FDA_BAS(base) (ETHER00_TYPE (base + 0x11C)) -#define ETHER_FDA_BAS_ADDRESS_OFST (4) -#define ETHER_FDA_BAS_ADDRESS_MSK (0xFFFFFFF0) - -#define ETHER_FDA_LIM(base) (ETHER00_TYPE (base + 0x120)) -#define ETHER_FDA_LIM_COUNT_OFST (4) -#define ETHER_FDA_LIM_COUNT_MSK (0xFFF0) - -#define ETHER_INT_SRC(base) (ETHER00_TYPE (base + 0x124)) -#define ETHER_INT_SRC_INTMACTX_OFST (0) -#define ETHER_INT_SRC_INTMACTX_MSK (0x1) -#define ETHER_INT_SRC_INTMACRX_OFST (1) -#define ETHER_INT_SRC_INTMACRX_MSK (0x2) -#define ETHER_INT_SRC_INTSBUS_OFST (2) -#define ETHER_INT_SRC_INTSBUS_MSK (0x4) -#define ETHER_INT_SRC_INTFDAEX_OFST (3) -#define ETHER_INT_SRC_INTFDAEX_MSK (0x8) -#define ETHER_INT_SRC_INTBLEX_OFST (4) -#define ETHER_INT_SRC_INTBLEX_MSK (0x10) -#define ETHER_INT_SRC_SWINT_OFST (5) -#define ETHER_INT_SRC_SWINT_MSK (0x20) -#define ETHER_INT_SRC_INTEARNOT_OFST (6) -#define ETHER_INT_SRC_INTEARNOT_MSK (0x40) -#define ETHER_INT_SRC_DMPARERR_OFST (7) -#define ETHER_INT_SRC_DMPARERR_MSK (0x80) -#define ETHER_INT_SRC_INTEXBD_OFST (8) -#define ETHER_INT_SRC_INTEXBD_MSK (0x100) -#define ETHER_INT_SRC_INTTXCTLCMP_OFST (9) -#define ETHER_INT_SRC_INTTXCTLCMP_MSK (0x200) -#define ETHER_INT_SRC_INTNRABT_OFST (10) -#define ETHER_INT_SRC_INTNRABT_MSK (0x400) -#define ETHER_INT_SRC_FDAEX_OFST (11) -#define ETHER_INT_SRC_FDAEX_MSK (0x800) -#define ETHER_INT_SRC_BLEX_OFST (12) -#define ETHER_INT_SRC_BLEX_MSK (0x1000) -#define ETHER_INT_SRC_DMPARERRSTAT_OFST (13) -#define ETHER_INT_SRC_DMPARERRSTAT_MSK (0x2000) -#define ETHER_INT_SRC_NRABT_OFST (14) -#define ETHER_INT_SRC_NRABT_MSK (0x4000) -#define ETHER_INT_SRC_INTLINK_OFST (15) -#define ETHER_INT_SRC_INTLINK_MSK (0x8000) -#define ETHER_INT_SRC_INTEXDEFER_OFST (16) -#define ETHER_INT_SRC_INTEXDEFER_MSK (0x10000) -#define ETHER_INT_SRC_INTRMON_OFST (17) -#define ETHER_INT_SRC_INTRMON_MSK (0x20000) -#define ETHER_INT_SRC_IRQ_MSK (0x83FF) - -#define ETHER_PAUSECNT(base) (ETHER00_TYPE (base + 0x40)) -#define ETHER_PAUSECNT_COUNT_OFST (0) -#define ETHER_PAUSECNT_COUNT_MSK (0xFFFF) - -#define ETHER_REMPAUCNT(base) (ETHER00_TYPE (base + 0x44)) -#define ETHER_REMPAUCNT_COUNT_OFST (0) -#define ETHER_REMPAUCNT_COUNT_MSK (0xFFFF) - -#define ETHER_TXCONFRMSTAT(base) (ETHER00_TYPE (base + 0x348)) -#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST (0) -#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK (0x3FFFFF) - -#define ETHER_MAC_CTL(base) (ETHER00_TYPE (base + 0)) -#define ETHER_MAC_CTL_HALTREQ_OFST (0) -#define ETHER_MAC_CTL_HALTREQ_MSK (0x1) -#define ETHER_MAC_CTL_HALTIMM_OFST (1) -#define ETHER_MAC_CTL_HALTIMM_MSK (0x2) -#define ETHER_MAC_CTL_RESET_OFST (2) -#define ETHER_MAC_CTL_RESET_MSK (0x4) -#define ETHER_MAC_CTL_FULLDUP_OFST (3) -#define ETHER_MAC_CTL_FULLDUP_MSK (0x8) -#define ETHER_MAC_CTL_MACLOOP_OFST (4) -#define ETHER_MAC_CTL_MACLOOP_MSK (0x10) -#define ETHER_MAC_CTL_CONN_OFST (5) -#define ETHER_MAC_CTL_CONN_MSK (0x60) -#define ETHER_MAC_CTL_LOOP10_OFST (7) -#define ETHER_MAC_CTL_LOOP10_MSK (0x80) -#define ETHER_MAC_CTL_LNKCHG_OFST (8) -#define ETHER_MAC_CTL_LNKCHG_MSK (0x100) -#define ETHER_MAC_CTL_MISSROLL_OFST (10) -#define ETHER_MAC_CTL_MISSROLL_MSK (0x400) -#define ETHER_MAC_CTL_ENMISSROLL_OFST (13) -#define ETHER_MAC_CTL_ENMISSROLL_MSK (0x2000) -#define ETHER_MAC_CTL_LINK10_OFST (15) -#define ETHER_MAC_CTL_LINK10_MSK (0x8000) - -#define ETHER_ARC_CTL(base) (ETHER00_TYPE (base + 0x4)) -#define ETHER_ARC_CTL_STATIONACC_OFST (0) -#define ETHER_ARC_CTL_STATIONACC_MSK (0x1) -#define ETHER_ARC_CTL_GROUPACC_OFST (1) -#define ETHER_ARC_CTL_GROUPACC_MSK (0x2) -#define ETHER_ARC_CTL_BROADACC_OFST (2) -#define ETHER_ARC_CTL_BROADACC_MSK (0x4) -#define ETHER_ARC_CTL_NEGARC_OFST (3) -#define ETHER_ARC_CTL_NEGARC_MSK (0x8) -#define ETHER_ARC_CTL_COMPEN_OFST (4) -#define ETHER_ARC_CTL_COMPEN_MSK (0x10) - -#define ETHER_TX_CTL(base) (ETHER00_TYPE (base + 0x8)) -#define ETHER_TX_CTL_TXEN_OFST (0) -#define ETHER_TX_CTL_TXEN_MSK (0x1) -#define ETHER_TX_CTL_TXHALT_OFST (1) -#define ETHER_TX_CTL_TXHALT_MSK (0x2) -#define ETHER_TX_CTL_NOPAD_OFST (2) -#define ETHER_TX_CTL_NOPAD_MSK (0x4) -#define ETHER_TX_CTL_NOCRC_OFST (3) -#define ETHER_TX_CTL_NOCRC_MSK (0x8) -#define ETHER_TX_CTL_FBACK_OFST (4) -#define ETHER_TX_CTL_FBACK_MSK (0x10) -#define ETHER_TX_CTL_NOEXDEF_OFST (5) -#define ETHER_TX_CTL_NOEXDEF_MSK (0x20) -#define ETHER_TX_CTL_SDPAUSE_OFST (6) -#define ETHER_TX_CTL_SDPAUSE_MSK (0x40) -#define ETHER_TX_CTL_MII10_OFST (7) -#define ETHER_TX_CTL_MII10_MSK (0x80) -#define ETHER_TX_CTL_ENUNDER_OFST (8) -#define ETHER_TX_CTL_ENUNDER_MSK (0x100) -#define ETHER_TX_CTL_ENEXDEFER_OFST (9) -#define ETHER_TX_CTL_ENEXDEFER_MSK (0x200) -#define ETHER_TX_CTL_ENLCARR_OFST (10) -#define ETHER_TX_CTL_ENLCARR_MSK (0x400) -#define ETHER_TX_CTL_ENEXCOLL_OFST (11) -#define ETHER_TX_CTL_ENEXCOLL_MSK (0x800) -#define ETHER_TX_CTL_ENLATECOLL_OFST (12) -#define ETHER_TX_CTL_ENLATECOLL_MSK (0x1000) -#define ETHER_TX_CTL_ENTXPAR_OFST (13) -#define ETHER_TX_CTL_ENTXPAR_MSK (0x2000) -#define ETHER_TX_CTL_ENCOMP_OFST (14) -#define ETHER_TX_CTL_ENCOMP_MSK (0x4000) - -#define ETHER_TX_STAT(base) (ETHER00_TYPE (base + 0xc)) -#define ETHER_TX_STAT_TXCOLL_OFST (0) -#define ETHER_TX_STAT_TXCOLL_MSK (0xF) -#define ETHER_TX_STAT_EXCOLL_OFST (4) -#define ETHER_TX_STAT_EXCOLL_MSK (0x10) -#define ETHER_TX_STAT_TXDEFER_OFST (5) -#define ETHER_TX_STAT_TXDEFER_MSK (0x20) -#define ETHER_TX_STAT_PAUSED_OFST (6) -#define ETHER_TX_STAT_PAUSED_MSK (0x40) -#define ETHER_TX_STAT_INTTX_OFST (7) -#define ETHER_TX_STAT_INTTX_MSK (0x80) -#define ETHER_TX_STAT_UNDER_OFST (8) -#define ETHER_TX_STAT_UNDER_MSK (0x100) -#define ETHER_TX_STAT_EXDEFER_OFST (9) -#define ETHER_TX_STAT_EXDEFER_MSK (0x200) -#define ETHER_TX_STAT_LCARR_OFST (10) -#define ETHER_TX_STAT_LCARR_MSK (0x400) -#define ETHER_TX_STAT_TX10STAT_OFST (11) -#define ETHER_TX_STAT_TX10STAT_MSK (0x800) -#define ETHER_TX_STAT_LATECOLL_OFST (12) -#define ETHER_TX_STAT_LATECOLL_MSK (0x1000) -#define ETHER_TX_STAT_TXPAR_OFST (13) -#define ETHER_TX_STAT_TXPAR_MSK (0x2000) -#define ETHER_TX_STAT_COMP_OFST (14) -#define ETHER_TX_STAT_COMP_MSK (0x4000) -#define ETHER_TX_STAT_TXHALTED_OFST (15) -#define ETHER_TX_STAT_TXHALTED_MSK (0x8000) -#define ETHER_TX_STAT_SQERR_OFST (16) -#define ETHER_TX_STAT_SQERR_MSK (0x10000) -#define ETHER_TX_STAT_TXMCAST_OFST (17) -#define ETHER_TX_STAT_TXMCAST_MSK (0x20000) -#define ETHER_TX_STAT_TXBCAST_OFST (18) -#define ETHER_TX_STAT_TXBCAST_MSK (0x40000) -#define ETHER_TX_STAT_VLAN_OFST (19) -#define ETHER_TX_STAT_VLAN_MSK (0x80000) -#define ETHER_TX_STAT_MACC_OFST (20) -#define ETHER_TX_STAT_MACC_MSK (0x100000) -#define ETHER_TX_STAT_TXPAUSE_OFST (21) -#define ETHER_TX_STAT_TXPAUSE_MSK (0x200000) - -#define ETHER_RX_CTL(base) (ETHER00_TYPE (base + 0x10)) -#define ETHER_RX_CTL_RXEN_OFST (0) -#define ETHER_RX_CTL_RXEN_MSK (0x1) -#define ETHER_RX_CTL_RXHALT_OFST (1) -#define ETHER_RX_CTL_RXHALT_MSK (0x2) -#define ETHER_RX_CTL_LONGEN_OFST (2) -#define ETHER_RX_CTL_LONGEN_MSK (0x4) -#define ETHER_RX_CTL_SHORTEN_OFST (3) -#define ETHER_RX_CTL_SHORTEN_MSK (0x8) -#define ETHER_RX_CTL_STRIPCRC_OFST (4) -#define ETHER_RX_CTL_STRIPCRC_MSK (0x10) -#define ETHER_RX_CTL_PASSCTL_OFST (5) -#define ETHER_RX_CTL_PASSCTL_MSK (0x20) -#define ETHER_RX_CTL_IGNORECRC_OFST (6) -#define ETHER_RX_CTL_IGNORECRC_MSK (0x40) -#define ETHER_RX_CTL_ENALIGN_OFST (8) -#define ETHER_RX_CTL_ENALIGN_MSK (0x100) -#define ETHER_RX_CTL_ENCRCERR_OFST (9) -#define ETHER_RX_CTL_ENCRCERR_MSK (0x200) -#define ETHER_RX_CTL_ENOVER_OFST (10) -#define ETHER_RX_CTL_ENOVER_MSK (0x400) -#define ETHER_RX_CTL_ENLONGERR_OFST (11) -#define ETHER_RX_CTL_ENLONGERR_MSK (0x800) -#define ETHER_RX_CTL_ENRXPAR_OFST (13) -#define ETHER_RX_CTL_ENRXPAR_MSK (0x2000) -#define ETHER_RX_CTL_ENGOOD_OFST (14) -#define ETHER_RX_CTL_ENGOOD_MSK (0x4000) - -#define ETHER_RX_STAT(base) (ETHER00_TYPE (base + 0x14)) -#define ETHER_RX_STAT_LENERR_OFST (4) -#define ETHER_RX_STAT_LENERR_MSK (0x10) -#define ETHER_RX_STAT_CTLRECD_OFST (5) -#define ETHER_RX_STAT_CTLRECD_MSK (0x20) -#define ETHER_RX_STAT_INTRX_OFST (6) -#define ETHER_RX_STAT_INTRX_MSK (0x40) -#define ETHER_RX_STAT_RX10STAT_OFST (7) -#define ETHER_RX_STAT_RX10STAT_MSK (0x80) -#define ETHER_RX_STAT_ALIGNERR_OFST (8) -#define ETHER_RX_STAT_ALIGNERR_MSK (0x100) -#define ETHER_RX_STAT_CRCERR_OFST (9) -#define ETHER_RX_STAT_CRCERR_MSK (0x200) -#define ETHER_RX_STAT_OVERFLOW_OFST (10) -#define ETHER_RX_STAT_OVERFLOW_MSK (0x400) -#define ETHER_RX_STAT_LONGERR_OFST (11) -#define ETHER_RX_STAT_LONGERR_MSK (0x800) -#define ETHER_RX_STAT_RXPAR_OFST (13) -#define ETHER_RX_STAT_RXPAR_MSK (0x2000) -#define ETHER_RX_STAT_GOOD_OFST (14) -#define ETHER_RX_STAT_GOOD_MSK (0x4000) -#define ETHER_RX_STAT_RXHALTED_OFST (15) -#define ETHER_RX_STAT_RXHALTED_MSK (0x8000) -#define ETHER_RX_STAT_RXMCAST_OFST (17) -#define ETHER_RX_STAT_RXMCAST_MSK (0x10000) -#define ETHER_RX_STAT_RXBCAST_OFST (18) -#define ETHER_RX_STAT_RXBCAST_MSK (0x20000) -#define ETHER_RX_STAT_RXVLAN_OFST (19) -#define ETHER_RX_STAT_RXVLAN_MSK (0x40000) -#define ETHER_RX_STAT_RXPAUSE_OFST (20) -#define ETHER_RX_STAT_RXPAUSE_MSK (0x80000) -#define ETHER_RX_STAT_ARCSTATUS_OFST (21) -#define ETHER_RX_STAT_ARCSTATUS_MSK (0xF00000) -#define ETHER_RX_STAT_ARCENT_OFST (25) -#define ETHER_RX_STAT_ARCENT_MSK (0x1F000000) - -#define ETHER_MD_DATA(base) (ETHER00_TYPE (base + 0x18)) - -#define ETHER_MD_CA(base) (ETHER00_TYPE (base + 0x1c)) -#define ETHER_MD_CA_ADDR_OFST (0) -#define ETHER_MD_CA_ADDR_MSK (0x1F) -#define ETHER_MD_CA_PHY_OFST (5) -#define ETHER_MD_CA_PHY_MSK (0x3E0) -#define ETHER_MD_CA_WR_OFST (10) -#define ETHER_MD_CA_WR_MSK (0x400) -#define ETHER_MD_CA_BUSY_OFST (11) -#define ETHER_MD_CA_BUSY_MSK (0x800) -#define ETHER_MD_CA_PRESUPP_OFST (12) -#define ETHER_MD_CA_PRESUPP_MSK (0x1000) - -#define ETHER_ARC_ADR(base) (ETHER00_TYPE (base + 0x160)) -#define ETHER_ARC_ADR_ARC_LOC_OFST (2) -#define ETHER_ARC_ADR_ARC_LOC_MSK (0xFFC) - -#define ETHER_ARC_DATA(base) (ETHER00_TYPE (base + 0x364)) - -#define ETHER_ARC_ENA(base) (ETHER00_TYPE (base + 0x28)) -#define ETHER_ARC_ENA_MSK (0x1FFFFF) - -#define ETHER_PROM_CTL(base) (ETHER00_TYPE (base + 0x2c)) -#define ETHER_PROM_CTL_PROM_ADDR_OFST (0) -#define ETHER_PROM_CTL_PROM_ADDR_MSK (0x3F) -#define ETHER_PROM_CTL_OPCODE_OFST (13) -#define ETHER_PROM_CTL_OPCODE_MSK (0x6000) -#define ETHER_PROM_CTL_OPCODE_READ_MSK (0x4000) -#define ETHER_PROM_CTL_OPCODE_WRITE_MSK (0x2000) -#define ETHER_PROM_CTL_OPCODE_ERASE_MSK (0x6000) -#define ETHER_PROM_CTL_ENABLE_MSK (0x0030) -#define ETHER_PROM_CTL_DISABLE_MSK (0x0000) -#define ETHER_PROM_CTL_BUSY_OFST (15) -#define ETHER_PROM_CTL_BUSY_MSK (0x8000) - -#define ETHER_PROM_DATA(base) (ETHER00_TYPE (base + 0x30)) - -#define ETHER_MISS_CNT(base) (ETHER00_TYPE (base + 0x3c)) -#define ETHER_MISS_CNT_COUNT_OFST (0) -#define ETHER_MISS_CNT_COUNT_MSK (0xFFFF) - -#define ETHER_CNTDATA(base) (ETHER00_TYPE (base + 0x80)) - -#define ETHER_CNTACC(base) (ETHER00_TYPE (base + 0x84)) -#define ETHER_CNTACC_ADDR_OFST (0) -#define ETHER_CNTACC_ADDR_MSK (0xFF) -#define ETHER_CNTACC_WRRDN_OFST (8) -#define ETHER_CNTACC_WRRDN_MSK (0x100) -#define ETHER_CNTACC_CLEAR_OFST (9) -#define ETHER_CNTACC_CLEAR_MSK (0x200) - -#define ETHER_TXRMINTEN(base) (ETHER00_TYPE (base + 0x88)) -#define ETHER_TXRMINTEN_MSK (0x3FFFFFFF) - -#define ETHER_RXRMINTEN(base) (ETHER00_TYPE (base + 0x8C)) -#define ETHER_RXRMINTEN_MSK (0xFFFFFF) - -/* -* RMON Registers -*/ -#define RMON_COLLISION0 0x0 -#define RMON_COLLISION1 0x1 -#define RMON_COLLISION2 0x2 -#define RMON_COLLISION3 0x3 -#define RMON_COLLISION4 0x4 -#define RMON_COLLISION5 0x5 -#define RMON_COLLISION6 0x6 -#define RMON_COLLISION7 0x7 -#define RMON_COLLISION8 0x8 -#define RMON_COLLISION9 0x9 -#define RMON_COLLISION10 0xa -#define RMON_COLLISION11 0xb -#define RMON_COLLISION12 0xc -#define RMON_COLLISION13 0xd -#define RMON_COLLISION14 0xe -#define RMON_COLLISION15 0xf -#define RMON_COLLISION16 0x10 -#define RMON_FRAMES_WITH_DEFERRED_XMISSIONS 0x11 -#define RMON_LATE_COLLISIONS 0x12 -#define RMON_FRAMES_LOST_DUE_TO_MAC_XMIT 0x13 -#define RMON_CARRIER_SENSE_ERRORS 0x14 -#define RMON_FRAMES_WITH_EXCESSIVE_DEFERAL 0x15 -#define RMON_UNICAST_FRAMES_TRANSMITTED_OK 0x16 -#define RMON_MULTICAST_FRAMES_XMITTED_OK 0x17 -#define RMON_BROADCAST_FRAMES_XMITTED_OK 0x18 -#define RMON_SQE_TEST_ERRORS 0x19 -#define RMON_PAUSE_MACCTRL_FRAMES_XMITTED 0x1A -#define RMON_MACCTRL_FRAMES_XMITTED 0x1B -#define RMON_VLAN_FRAMES_XMITTED 0x1C -#define RMON_OCTETS_XMITTED_OK 0x1D -#define RMON_OCTETS_XMITTED_OK_HI 0x1E - -#define RMON_RX_PACKET_SIZES0 0x40 -#define RMON_RX_PACKET_SIZES1 0x41 -#define RMON_RX_PACKET_SIZES2 0x42 -#define RMON_RX_PACKET_SIZES3 0x43 -#define RMON_RX_PACKET_SIZES4 0x44 -#define RMON_RX_PACKET_SIZES5 0x45 -#define RMON_RX_PACKET_SIZES6 0x46 -#define RMON_RX_PACKET_SIZES7 0x47 -#define RMON_FRAME_CHECK_SEQUENCE_ERRORS 0x48 -#define RMON_ALIGNMENT_ERRORS 0x49 -#define RMON_FRAGMENTS 0x4A -#define RMON_JABBERS 0x4B -#define RMON_FRAMES_LOST_TO_INTMACRCVERR 0x4C -#define RMON_UNICAST_FRAMES_RCVD_OK 0x4D -#define RMON_MULTICAST_FRAMES_RCVD_OK 0x4E -#define RMON_BROADCAST_FRAMES_RCVD_OK 0x4F -#define RMON_IN_RANGE_LENGTH_ERRORS 0x50 -#define RMON_OUT_OF_RANGE_LENGTH_ERRORS 0x51 -#define RMON_VLAN_FRAMES_RCVD 0x52 -#define RMON_PAUSE_MAC_CTRL_FRAMES_RCVD 0x53 -#define RMON_MAC_CTRL_FRAMES_RCVD 0x54 -#define RMON_OCTETS_RCVD_OK 0x55 -#define RMON_OCTETS_RCVD_OK_HI 0x56 -#define RMON_OCTETS_RCVD_OTHER 0x57 -#define RMON_OCTETS_RCVD_OTHER_HI 0x58 - -#endif /* __ETHER00_H */ diff --git a/include/asm-arm/arch-epxa10db/excalibur.h b/include/asm-arm/arch-epxa10db/excalibur.h deleted file mode 100644 index 5c91dd6d782..00000000000 --- a/include/asm-arm/arch-epxa10db/excalibur.h +++ /dev/null @@ -1,91 +0,0 @@ -/* megafunction wizard: %ARM-Based Excalibur% - GENERATION: STANDARD - VERSION: WM1.0 - MODULE: ARM-Based Excalibur - PROJECT: excalibur - ============================================================ - File Name: v:\embedded\linux\bootldr\excalibur.h - Megafunction Name(s): ARM-Based Excalibur - ============================================================ - - ************************************************************ - THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! - ************************************************************/ - -#ifndef EXCALIBUR_H_INCLUDED -#define EXCALIBUR_H_INCLUDED - -#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN -#define EXC_DEFINE_BOOT_FROM_FLASH - -#define EXC_INPUT_CLK_FREQUENCY (50000000) -#define EXC_AHB1_CLK_FREQUENCY (150000000) -#define EXC_AHB2_CLK_FREQUENCY (75000000) -#define EXC_SDRAM_CLK_FREQUENCY (75000000) - -/* Registers Block */ -#define EXC_REGISTERS_BASE (0x7fffc000) -#define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000) -#define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040) -#define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080) -#define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140) -#define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200) -#define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00) -#define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300) -#define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00) -#define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280) -#define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380) -#define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400) -#define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800) -#define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100) -#define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100) - -#define EXC_REGISTERS_SIZE (0x00004000) - -/* EBI Block(s) */ -#define EXC_EBI_BLOCK0_BASE (0x40000000) -#define EXC_EBI_BLOCK0_SIZE (0x00400000) -#define EXC_EBI_BLOCK0_WIDTH (8) -#define EXC_EBI_BLOCK0_NON_CACHEABLE -#define EXC_EBI_BLOCK1_BASE (0x40400000) -#define EXC_EBI_BLOCK1_SIZE (0x00400000) -#define EXC_EBI_BLOCK1_WIDTH (16) -#define EXC_EBI_BLOCK1_NON_CACHEABLE -#define EXC_EBI_BLOCK2_BASE (0x40800000) -#define EXC_EBI_BLOCK2_SIZE (0x00400000) -#define EXC_EBI_BLOCK2_WIDTH (16) -#define EXC_EBI_BLOCK2_NON_CACHEABLE -#define EXC_EBI_BLOCK3_BASE (0x40c00000) -#define EXC_EBI_BLOCK3_SIZE (0x00400000) -#define EXC_EBI_BLOCK3_WIDTH (16) -#define EXC_EBI_BLOCK3_NON_CACHEABLE - -/* SDRAM Block(s) */ -#define EXC_SDRAM_BLOCK0_BASE (0x00000000) -#define EXC_SDRAM_BLOCK0_SIZE (0x04000000) -#define EXC_SDRAM_BLOCK0_WIDTH (32) -#define EXC_SDRAM_BLOCK1_BASE (0x04000000) -#define EXC_SDRAM_BLOCK1_SIZE (0x04000000) -#define EXC_SDRAM_BLOCK1_WIDTH (32) - -/* Single Port SRAM Block(s) */ -#define EXC_SPSRAM_BLOCK0_BASE (0x08000000) -#define EXC_SPSRAM_BLOCK0_SIZE (0x00020000) -#define EXC_SPSRAM_BLOCK1_BASE (0x08020000) -#define EXC_SPSRAM_BLOCK1_SIZE (0x00020000) - -/* PLD Block(s) */ -#define EXC_PLD_BLOCK0_BASE (0x80000000) -#define EXC_PLD_BLOCK0_SIZE (0x00004000) -#define EXC_PLD_BLOCK0_NON_CACHEABLE -#define EXC_PLD_BLOCK1_BASE (0xf000000) -#define EXC_PLD_BLOCK1_SIZE (0x00004000) -#define EXC_PLD_BLOCK1_NON_CACHEABLE -#define EXC_PLD_BLOCK2_BASE (0x80008000) -#define EXC_PLD_BLOCK2_SIZE (0x00004000) -#define EXC_PLD_BLOCK2_NON_CACHEABLE -#define EXC_PLD_BLOCK3_BASE (0x8000c000) -#define EXC_PLD_BLOCK3_SIZE (0x00004000) -#define EXC_PLD_BLOCK3_NON_CACHEABLE - -#endif diff --git a/include/asm-arm/arch-epxa10db/hardware.h b/include/asm-arm/arch-epxa10db/hardware.h deleted file mode 100644 index b992c2924a7..00000000000 --- a/include/asm-arm/arch-epxa10db/hardware.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * linux/include/asm-arm/arch-epxa10/hardware.h - * - * This file contains the hardware definitions of the Integrator. - * - * Copyright (C) 1999 ARM Limited. - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/arch/platform.h> - -/* - * Where in virtual memory the IO devices (timers, system controllers - * and so on) - */ -#define IO_BASE 0xf0000000 // VA of IO -#define IO_SIZE 0x10000000 // How much? -#define IO_START EXC_REGISTERS_BASE // PA of IO -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((x) | 0xf0000000) - -#define FLASH_VBASE 0xFE000000 -#define FLASH_SIZE 0x01000000 -#define FLASH_START EXC_EBI_BLOCK0_BASE -#define FLASH_VADDR(x) ((x)|0xFE000000) -/* - * Similar to above, but for PCI addresses (memory, IO, Config and the - * V3 chip itself). WARNING: this has to mirror definitions in platform.h - */ -#if 0 -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_CONFIG_VADDR 0xec000000 -#define PCI_V3_VADDR 0xed000000 -#define PCI_IO_VADDR 0xee000000 - -#define PCIO_BASE PCI_IO_VADDR -#define PCIMEM_BASE PCI_MEMORY_VADDR - - -#define pcibios_assign_all_busses() 1 - -#define PCIBIOS_MIN_IO 0x6000 -#define PCIBIOS_MIN_MEM 0x00100000 -#endif - - -#endif - diff --git a/include/asm-arm/arch-epxa10db/int_ctrl00.h b/include/asm-arm/arch-epxa10db/int_ctrl00.h deleted file mode 100644 index 23ec864c40b..00000000000 --- a/include/asm-arm/arch-epxa10db/int_ctrl00.h +++ /dev/null @@ -1,288 +0,0 @@ -/* - * - * This file contains the register definitions for the Excalibur - * Timer TIMER00. - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __INT_CTRL00_H -#define __INT_CTRL00_H - -#define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x00 )) -#define INT_MS_FC_MSK (0x10000) -#define INT_MS_FC_OFST (16) -#define INT_MS_M1_MSK (0x8000) -#define INT_MS_M1_OFST (15) -#define INT_MS_M0_MSK (0x4000) -#define INT_MS_M0_OFST (14) -#define INT_MS_AE_MSK (0x2000) -#define INT_MS_AE_OFST (13) -#define INT_MS_PE_MSK (0x1000) -#define INT_MS_PE_OFST (12) -#define INT_MS_EE_MSK (0x0800) -#define INT_MS_EE_OFST (11) -#define INT_MS_PS_MSK (0x0400) -#define INT_MS_PS_OFST (10) -#define INT_MS_T1_MSK (0x0200) -#define INT_MS_T1_OFST (9) -#define INT_MS_T0_MSK (0x0100) -#define INT_MS_T0_OFST (8) -#define INT_MS_UA_MSK (0x0080) -#define INT_MS_UA_OFST (7) -#define INT_MS_IP_MSK (0x0040) -#define INT_MS_IP_OFST (6) -#define INT_MS_P5_MSK (0x0020) -#define INT_MS_P5_OFST (5) -#define INT_MS_P4_MSK (0x0010) -#define INT_MS_P4_OFST (4) -#define INT_MS_P3_MSK (0x0008) -#define INT_MS_P3_OFST (3) -#define INT_MS_P2_MSK (0x0004) -#define INT_MS_P2_OFST (2) -#define INT_MS_P1_MSK (0x0002) -#define INT_MS_P1_OFST (1) -#define INT_MS_P0_MSK (0x0001) -#define INT_MS_P0_OFST (0) - -#define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr + 0x04 )) -#define INT_MC_FC_MSK (0x10000) -#define INT_MC_FC_OFST (16) -#define INT_MC_M1_MSK (0x8000) -#define INT_MC_M1_OFST (15) -#define INT_MC_M0_MSK (0x4000) -#define INT_MC_M0_OFST (14) -#define INT_MC_AE_MSK (0x2000) -#define INT_MC_AE_OFST (13) -#define INT_MC_PE_MSK (0x1000) -#define INT_MC_PE_OFST (12) -#define INT_MC_EE_MSK (0x0800) -#define INT_MC_EE_OFST (11) -#define INT_MC_PS_MSK (0x0400) -#define INT_MC_PS_OFST (10) -#define INT_MC_T1_MSK (0x0200) -#define INT_MC_T1_OFST (9) -#define INT_MC_T0_MSK (0x0100) -#define INT_MC_T0_OFST (8) -#define INT_MC_UA_MSK (0x0080) -#define INT_MC_UA_OFST (7) -#define INT_MC_IP_MSK (0x0040) -#define INT_MC_IP_OFST (6) -#define INT_MC_P5_MSK (0x0020) -#define INT_MC_P5_OFST (5) -#define INT_MC_P4_MSK (0x0010) -#define INT_MC_P4_OFST (4) -#define INT_MC_P3_MSK (0x0008) -#define INT_MC_P3_OFST (3) -#define INT_MC_P2_MSK (0x0004) -#define INT_MC_P2_OFST (2) -#define INT_MC_P1_MSK (0x0002) -#define INT_MC_P1_OFST (1) -#define INT_MC_P0_MSK (0x0001) -#define INT_MC_P0_OFST (0) - -#define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x08 )) -#define INT_SS_FC_SSK (0x8000) -#define INT_SS_FC_OFST (15) -#define INT_SS_M1_SSK (0x8000) -#define INT_SS_M1_OFST (15) -#define INT_SS_M0_SSK (0x4000) -#define INT_SS_M0_OFST (14) -#define INT_SS_AE_SSK (0x2000) -#define INT_SS_AE_OFST (13) -#define INT_SS_PE_SSK (0x1000) -#define INT_SS_PE_OFST (12) -#define INT_SS_EE_SSK (0x0800) -#define INT_SS_EE_OFST (11) -#define INT_SS_PS_SSK (0x0400) -#define INT_SS_PS_OFST (10) -#define INT_SS_T1_SSK (0x0200) -#define INT_SS_T1_OFST (9) -#define INT_SS_T0_SSK (0x0100) -#define INT_SS_T0_OFST (8) -#define INT_SS_UA_SSK (0x0080) -#define INT_SS_UA_OFST (7) -#define INT_SS_IP_SSK (0x0040) -#define INT_SS_IP_OFST (6) -#define INT_SS_P5_SSK (0x0020) -#define INT_SS_P5_OFST (5) -#define INT_SS_P4_SSK (0x0010) -#define INT_SS_P4_OFST (4) -#define INT_SS_P3_SSK (0x0008) -#define INT_SS_P3_OFST (3) -#define INT_SS_P2_SSK (0x0004) -#define INT_SS_P2_OFST (2) -#define INT_SS_P1_SSK (0x0002) -#define INT_SS_P1_OFST (1) -#define INT_SS_P0_SSK (0x0001) -#define INT_SS_P0_OFST (0) - -#define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x0C )) -#define INT_RS_FC_RSK (0x10000) -#define INT_RS_FC_OFST (16) -#define INT_RS_M1_RSK (0x8000) -#define INT_RS_M1_OFST (15) -#define INT_RS_M0_RSK (0x4000) -#define INT_RS_M0_OFST (14) -#define INT_RS_AE_RSK (0x2000) -#define INT_RS_AE_OFST (13) -#define INT_RS_PE_RSK (0x1000) -#define INT_RS_PE_OFST (12) -#define INT_RS_EE_RSK (0x0800) -#define INT_RS_EE_OFST (11) -#define INT_RS_PS_RSK (0x0400) -#define INT_RS_PS_OFST (10) -#define INT_RS_T1_RSK (0x0200) -#define INT_RS_T1_OFST (9) -#define INT_RS_T0_RSK (0x0100) -#define INT_RS_T0_OFST (8) -#define INT_RS_UA_RSK (0x0080) -#define INT_RS_UA_OFST (7) -#define INT_RS_IP_RSK (0x0040) -#define INT_RS_IP_OFST (6) -#define INT_RS_P5_RSK (0x0020) -#define INT_RS_P5_OFST (5) -#define INT_RS_P4_RSK (0x0010) -#define INT_RS_P4_OFST (4) -#define INT_RS_P3_RSK (0x0008) -#define INT_RS_P3_OFST (3) -#define INT_RS_P2_RSK (0x0004) -#define INT_RS_P2_OFST (2) -#define INT_RS_P1_RSK (0x0002) -#define INT_RS_P1_OFST (1) -#define INT_RS_P0_RSK (0x0001) -#define INT_RS_P0_OFST (0) - -#define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr + 0x10 )) -#define INT_ID_ID_MSK (0x3F) -#define INT_ID_ID_OFST (0) - -#define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr + 0x14 )) -#define INT_PLD_PRIORITY_PRI_MSK (0x3F) -#define INT_PLD_PRIORITY_PRI_OFST (0) -#define INT_PLD_PRIORITY_GA_MSK (0x40) -#define INT_PLD_PRIORITY_GA_OFST (6) - -#define INT_MODE(base_addr) (INT_CTRL00_TYPE (base_addr + 0x18 )) -#define INT_MODE_MODE_MSK (0x3) -#define INT_MODE_MODE_OFST (0) - -#define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr + 0x80 )) -#define INT_PRIORITY_P0_PRI_MSK (0x3F) -#define INT_PRIORITY_P0_PRI_OFST (0) -#define INT_PRIORITY_P0_FQ_MSK (0x40) -#define INT_PRIORITY_P0_FQ_OFST (6) - -#define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr + 0x84 )) -#define INT_PRIORITY_P1_PRI_MSK (0x3F) -#define INT_PRIORITY_P1_PRI_OFST (0) -#define INT_PRIORITY_P1_FQ_MSK (0x40) -#define INT_PRIORITY_P1_FQ_OFST (6) - -#define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr + 0x88 )) -#define INT_PRIORITY_P2_PRI_MSK (0x3F) -#define INT_PRIORITY_P2_PRI_OFST (0) -#define INT_PRIORITY_P2_FQ_MSK (0x40) -#define INT_PRIORITY_P2_FQ_OFST (6) - -#define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr + 0x8C )) -#define INT_PRIORITY_P3_PRI_MSK (0x3F) -#define INT_PRIORITY_P3_PRI_OFST (0) -#define INT_PRIORITY_P3_FQ_MSK (0x40) -#define INT_PRIORITY_P3_FQ_OFST (6) - -#define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr + 0x90 )) -#define INT_PRIORITY_P4_PRI_MSK (0x3F) -#define INT_PRIORITY_P4_PRI_OFST (0) -#define INT_PRIORITY_P4_FQ_MSK (0x40) -#define INT_PRIORITY_P4_FQ_OFST (6) - -#define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 )) -#define INT_PRIORITY_P5_PRI_MSK (0x3F) -#define INT_PRIORITY_P5_PRI_OFST (0) -#define INT_PRIORITY_P5_FQ_MSK (0x40) -#define INT_PRIORITY_P5_FQ_OFST (6) - -#define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 )) -#define INT_PRIORITY_IP_PRI_MSK (0x3F) -#define INT_PRIORITY_IP_PRI_OFST (0) -#define INT_PRIORITY_IP_FQ_MSK (0x40) -#define INT_PRIORITY_IP_FQ_OFST (6) - -#define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr + 0x9C )) -#define INT_PRIORITY_UA_PRI_MSK (0x3F) -#define INT_PRIORITY_UA_PRI_OFST (0) -#define INT_PRIORITY_UA_FQ_MSK (0x40) -#define INT_PRIORITY_UA_FQ_OFST (6) - -#define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA0 )) -#define INT_PRIORITY_T0_PRI_MSK (0x3F) -#define INT_PRIORITY_T0_PRI_OFST (0) -#define INT_PRIORITY_T0_FQ_MSK (0x40) -#define INT_PRIORITY_T0_FQ_OFST (6) - -#define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA4 )) -#define INT_PRIORITY_T1_PRI_MSK (0x3F) -#define INT_PRIORITY_T1_PRI_OFST (0) -#define INT_PRIORITY_T1_FQ_MSK (0x40) -#define INT_PRIORITY_T1_FQ_OFST (6) - -#define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA8 )) -#define INT_PRIORITY_PS_PRI_MSK (0x3F) -#define INT_PRIORITY_PS_PRI_OFST (0) -#define INT_PRIORITY_PS_FQ_MSK (0x40) -#define INT_PRIORITY_PS_FQ_OFST (6) - -#define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xAC )) -#define INT_PRIORITY_EE_PRI_MSK (0x3F) -#define INT_PRIORITY_EE_PRI_OFST (0) -#define INT_PRIORITY_EE_FQ_MSK (0x40) -#define INT_PRIORITY_EE_FQ_OFST (6) - -#define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB0 )) -#define INT_PRIORITY_PE_PRI_MSK (0x3F) -#define INT_PRIORITY_PE_PRI_OFST (0) -#define INT_PRIORITY_PE_FQ_MSK (0x40) -#define INT_PRIORITY_PE_FQ_OFST (6) - -#define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB4 )) -#define INT_PRIORITY_AE_PRI_MSK (0x3F) -#define INT_PRIORITY_AE_PRI_OFST (0) -#define INT_PRIORITY_AE_FQ_MSK (0x40) -#define INT_PRIORITY_AE_FQ_OFST (6) - -#define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB8 )) -#define INT_PRIORITY_M0_PRI_MSK (0x3F) -#define INT_PRIORITY_M0_PRI_OFST (0) -#define INT_PRIORITY_M0_FQ_MSK (0x40) -#define INT_PRIORITY_M0_FQ_OFST (6) - -#define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xBC )) -#define INT_PRIORITY_M1_PRI_MSK (0x3F) -#define INT_PRIORITY_M1_PRI_OFST (0) -#define INT_PRIORITY_M1_FQ_MSK (0x40) -#define INT_PRIORITY_M1_FQ_OFST (6) - -#define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr + 0xC0 )) -#define INT_PRIORITY_FC_PRI_MSK (0x3F) -#define INT_PRIORITY_FC_PRI_OFST (0) -#define INT_PRIORITY_FC_FQ_MSK (0x40) -#define INT_PRIORITY_FC_FQ_OFST (6) - -#endif /* __INT_CTRL00_H */ - - diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h deleted file mode 100644 index 9fe100c9d6b..00000000000 --- a/include/asm-arm/arch-epxa10db/io.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * linux/include/asm-arm/arch-epxa10db/io.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include <asm/hardware.h> - -#define IO_SPACE_LIMIT 0xffff - - -/* - * Generic virtual read/write - */ -/*#define outsw __arch_writesw -#define outsl __arch_writesl -#define outsb __arch_writesb -#define insb __arch_readsb -#define insw __arch_readsw -#define insl __arch_readsl*/ - -#define __io(a) ((void __iomem *)(a)) -#define __mem_pci(a) (a) - -#endif diff --git a/include/asm-arm/arch-epxa10db/irqs.h b/include/asm-arm/arch-epxa10db/irqs.h deleted file mode 100644 index c3758a3b5d9..00000000000 --- a/include/asm-arm/arch-epxa10db/irqs.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * linux/include/asm-arm/arch-camelot/irqs.h - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* Use the Excalibur chip definitions */ -#define INT_CTRL00_TYPE -#include "asm/arch/int_ctrl00.h" - - -#define IRQ_PLD0 INT_MS_P0_OFST -#define IRQ_PLD1 INT_MS_P1_OFST -#define IRQ_PLD2 INT_MS_P2_OFST -#define IRQ_PLD3 INT_MS_P3_OFST -#define IRQ_PLD4 INT_MS_P4_OFST -#define IRQ_PLD5 INT_MS_P5_OFST -#define IRQ_EXT INT_MS_IP_OFST -#define IRQ_UART INT_MS_UA_OFST -#define IRQ_TIMER0 INT_MS_T0_OFST -#define IRQ_TIMER1 INT_MS_T1_OFST -#define IRQ_PLL INT_MS_PLL_OFST -#define IRQ_EBI INT_MS_EBI_OFST -#define IRQ_STRIPE_BRIDGE INT_MS_PLL_OFST -#define IRQ_AHB_BRIDGE INT_MS_PLL_OFST -#define IRQ_COMMRX INT_MS_CR_OFST -#define IRQ_COMMTX INT_MS_CT_OFST -#define IRQ_FAST_COMM INT_MS_FC_OFST - -#define NR_IRQS (INT_MS_FC_OFST + 1) - diff --git a/include/asm-arm/arch-epxa10db/mode_ctrl00.h b/include/asm-arm/arch-epxa10db/mode_ctrl00.h deleted file mode 100644 index d8a7efa12e1..00000000000 --- a/include/asm-arm/arch-epxa10db/mode_ctrl00.h +++ /dev/null @@ -1,80 +0,0 @@ -#ifndef __MODE_CTRL00_H -#define __MODE_CTRL00_H - -/* - * Register definitions for the reset and mode control - */ - -/* - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - - - -#define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR )) -#define BOOT_CR_BF_MSK (0x1) -#define BOOT_CR_BF_OFST (0) -#define BOOT_CR_HM_MSK (0x2) -#define BOOT_CR_HM_OFST (1) -#define BOOT_CR_RE_MSK (0x4) -#define BOOT_CR_RE_OFST (2) - -#define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x4 )) -#define RESET_SR_WR_MSK (0x1) -#define RESET_SR_WR_OFST (0) -#define RESET_SR_CR_MSK (0x2) -#define RESET_SR_CR_OFST (1) -#define RESET_SR_JT_MSK (0x4) -#define RESET_SR_JT_OFST (2) -#define RESET_SR_ER_MSK (0x8) -#define RESET_SR_ER_OFST (3) - -#define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x08 )) - -#define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x20 )) -#define SRAM0_SR_SIZE_MSK (0xFFFFF000) -#define SRAM0_SR_SIZE_OFST (12) - -#define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x24 )) -#define SRAM1_SR_SIZE_MSK (0xFFFFF000) -#define SRAM1_SR_SIZE_OFST (12) - -#define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x30 )) - -#define DPSRAM0_SR_MODE_MSK (0xF) -#define DPSRAM0_SR_MODE_OFST (0) -#define DPSRAM0_SR_GLBL_MSK (0x30) -#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000) -#define DPSRAM0_SR_SIZE_OFST (12) - -#define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x34 )) -#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0) -#define DPSRAM0_LCR_LCKADDR_OFST (4) - -#define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x38 )) -#define DPSRAM1_SR_MODE_MSK (0xF) -#define DPSRAM1_SR_MODE_OFST (0) -#define DPSRAM1_SR_GLBL_MSK (0x30) -#define DPSRAM1_SR_GLBL_OFST (4) -#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000) -#define DPSRAM1_SR_SIZE_OFST (12) - -#define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x3C )) -#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0) -#define DPSRAM1_LCR_LCKADDR_OFST (4) - -#endif /* __MODE_CTRL00_H */ diff --git a/include/asm-arm/arch-epxa10db/platform.h b/include/asm-arm/arch-epxa10db/platform.h deleted file mode 100644 index 129bb0f212a..00000000000 --- a/include/asm-arm/arch-epxa10db/platform.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef PLATFORM_H -#define PLATFORM_H -#include "excalibur.h" - -#define MAXIRQNUM 15 -#endif - diff --git a/include/asm-arm/arch-epxa10db/pld_conf00.h b/include/asm-arm/arch-epxa10db/pld_conf00.h deleted file mode 100644 index 7af2c38dacc..00000000000 --- a/include/asm-arm/arch-epxa10db/pld_conf00.h +++ /dev/null @@ -1,73 +0,0 @@ -#ifndef __PLD_CONF00_H -#define __PLD_CONF00_H - -/* - * Register definitions for the PLD Configuration Logic - */ - -/* - * - * This file contains the register definitions for the Excalibur - * Interrupt controller INT_CTRL00. - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#define CONFIG_CONTROL(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR)) -#define CONFIG_CONTROL_LK_MSK (0x1) -#define CONFIG_CONTROL_LK_OFST (0) -#define CONFIG_CONTROL_CO_MSK (0x2) -#define CONFIG_CONTROL_CO_OFST (1) -#define CONFIG_CONTROL_B_MSK (0x4) -#define CONFIG_CONTROL_B_OFST (2) -#define CONFIG_CONTROL_PC_MSK (0x8) -#define CONFIG_CONTROL_PC_OFST (3) -#define CONFIG_CONTROL_E_MSK (0x10) -#define CONFIG_CONTROL_E_OFST (4) -#define CONFIG_CONTROL_ES_MSK (0xE0) -#define CONFIG_CONTROL_ES_OFST (5) -#define CONFIG_CONTROL_ES_0_MSK (0x20) -#define CONFIG_CONTROL_ES_1_MSK (0x40) -#define CONFIG_CONTROL_ES_2_MSK (0x80) - -#define CONFIG_CONTROL_CLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x4 )) -#define CONFIG_CONTROL_CLOCK_RATIO_MSK (0xFFFF) -#define CONFIG_CONTROL_CLOCK_RATIO_OFST (0) - -#define CONFIG_CONTROL_DATA(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x8 )) -#define CONFIG_CONTROL_DATA_MSK (0xFFFFFFFF) -#define CONFIG_CONTROL_DATA_OFST (0) - -#define CONFIG_UNLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0xC )) -#define CONFIG_UNLOCK_MSK (0xFFFFFFFF) -#define CONFIG_UNLOCK_OFST (0) - -#define CONFIG_UNLOCK_MAGIC (0x554E4C4B) - -#endif /* __PLD_CONF00_H */ - - - - - - - - - - - - diff --git a/include/asm-arm/arch-epxa10db/tdkphy.h b/include/asm-arm/arch-epxa10db/tdkphy.h deleted file mode 100644 index 5e107bd4e10..00000000000 --- a/include/asm-arm/arch-epxa10db/tdkphy.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * linux/drivers/tdkphy.h - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __TDKPHY_H -#define __TDKPHY_H - -/* - * Register definitions for the TDK 78Q2120 PHY - * which is on the Camelot board - */ - -/* - * Copyright (c) Altera Corporation 2000. - * All rights reserved. - */ -#define PHY_CONTROL (0) -#define PHY_CONTROL_COLT_MSK (0x80) -#define PHY_CONTROL_COLT_OFST (7) -#define PHY_CONTROL_DUPLEX_MSK (0x100) -#define PHY_CONTROL_DUPLEX_OFST (8) -#define PHY_CONTROL_RANEG_MSK (0x200) -#define PHY_CONTROL_RANEG_OFST (9) -#define PHY_CONTROL_ISO_MSK (0x400) -#define PHY_CONTROL_ISO_OFST (10) -#define PHY_CONTROL_PWRDN_MSK (0x800) -#define PHY_CONTROL_PWRDN_OFST (11) -#define PHY_CONTROL_ANEGEN_MSK (0x1000) -#define PHY_CONTROL_ANEGEN_OFST (12) -#define PHY_CONTROL_SPEEDSL_MSK (0x2000) -#define PHY_CONTROL_SPEEDSL_OFST (13) -#define PHY_CONTROL_LOOPBK_MSK (0x4000) -#define PHY_CONTROL_LOOPBK_OFST (14) -#define PHY_CONTROL_RESET_MSK (0x8000) -#define PHY_CONTROL_RESET_OFST (15) - -#define PHY_STATUS (1) -#define PHY_STATUS_ETXD_MSK (0x1) -#define PHY_STATUS_EXTD_OFST (0) -#define PHY_STATUS_JAB_MSK (0x2) -#define PHY_STATUS_JAB_OFST (1) -#define PHY_STATUS_LINK_MSK (0x4) -#define PHY_STATUS_LINK_OFST (2) -#define PHY_STATUS_ANEGA_MSK (0x8) -#define PHY_STATUS_ANEGA_OFST (3) -#define PHY_STATUS_RFAULT_MSK (0x10) -#define PHY_STATUS_RFAULT_OFST (4) -#define PHY_STATUS_ANEGC_MSK (0x20) -#define PHY_STATUS_ANEGC_OFST (5) -#define PHY_STATUS_10T_H_MSK (0x800) -#define PHY_STATUS_10T_H_OFST (11) -#define PHY_STATUS_10T_F_MSK (0x1000) -#define PHY_STATUS_10T_F_OFST (12) -#define PHY_STATUS_100_X_H_MSK (0x2000) -#define PHY_STATUS_100_X_H_OFST (13) -#define PHY_STATUS_100_X_F_MSK (0x4000) -#define PHY_STATUS_100_X_F_OFST (14) -#define PHY_STATUS_100T4_MSK (0x8000) -#define PHY_STATUS_100T4_OFST (15) - -#define PHY_ID1 (2) -#define PHY_ID1_OUI_MSK (0xFFFF) -#define PHY_ID1_OUI_OFST (0) - -#define PHY_ID2 (3) -#define PHY_ID2_RN_MSK (0xF) -#define PHY_ID2_RN_OFST (0) -#define PHY_ID2_MN_MSK (0x3F0) -#define PHY_ID2_MN_OFST (4) -#define PHY_ID2_OUI_MSK (0xFC00) -#define PHY_ID2_OUI_OFST (10) - -#define PHY_AUTO_NEG_ADVERTISEMENT (4) -#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_MSK (0x1F) -#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_OFST (0) -#define PHY_AUTO_NEG_ADVERTISEMENT_A0_MSK (0x20) -#define PHY_AUTO_NEG_ADVERTISEMENT_A0_OFST (5) -#define PHY_AUTO_NEG_ADVERTISEMENT_A1_MSK (0x40) -#define PHY_AUTO_NEG_ADVERTISEMENT_A1_OFST (6) -#define PHY_AUTO_NEG_ADVERTISEMENT_A2_MSK (0x80) -#define PHY_AUTO_NEG_ADVERTISEMENT_A2_OFST (7) -#define PHY_AUTO_NEG_ADVERTISEMENT_A3_MSK (0x100) -#define PHY_AUTO_NEG_ADVERTISEMENT_A3_OFST (8) -#define PHY_AUTO_NEG_ADVERTISEMENT_A4_MSK (0x200) -#define PHY_AUTO_NEG_ADVERTISEMENT_A4_OFST (9) -#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_MSK (0x1FE0) -#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_OFST (5) -#define PHY_AUTO_NEG_ADVERTISEMENT_RF_MSK (0x2000) -#define PHY_AUTO_NEG_ADVERTISEMENT_RF_OFST (13) -#define PHY_AUTO_NEG_ADVERTISEMENT_RSVD_MSK (0x4000) -#define PHY_AUTO_NEG_ADVERTISEMENT_RVSD_OFST (14) -#define PHY_AUTO_NEG_ADVERTISEMENT_NP_MSK (0x8000) -#define PHY_AUTO_NEG_ADVERTISEMENT_NP_OFST (15) - -#define PHY_AUTO_NEG_LINK_PARTNER (5) -#define PHY_AUTO_NEG_LINK_PARTNER_S4_MSK (0x1F) -#define PHY_AUTO_NEG_LINK_PARTNER_S4_OFST (0) -#define PHY_AUTO_NEG_LINK_PARTNER_A7_MSK (0x1FE0) -#define PHY_AUTO_NEG_LINK_PARTNER_A7_OFST (5) -#define PHY_AUTO_NEG_LINK_PARTNER_RF_MSK (0x2000) -#define PHY_AUTO_NEG_LINK_PARTNER_RF_OFST (13) -#define PHY_AUTO_NEG_LINK_PARTNER_ACK_MSK (0x4000) -#define PHY_AUTO_NEG_LINK_PARTNER_ACK_OFST (14) -#define PHY_AUTO_NEG_LINK_PARTNER_NP_MSK (0x8000) -#define PHY_AUTO_NEG_LINK_PARTNER_NP_OFST (15) - -#define PHY_AUTO_NEG_EXPANSION (6) -#define PHY_AUTO_NEG_EXPANSION_LPANEGA_MSK (0x1) -#define PHY_AUTO_NEG_EXPANSION_LPANEGA_OFST (0) -#define PHY_AUTO_NEG_EXPANSION_PRX_MSK (0x2) -#define PHY_AUTO_NEG_EXPANSION_PRX_OFST (1) -#define PHY_AUTO_NEG_EXPANSION_NPA_MSK (0x4) -#define PHY_AUTO_NEG_EXPANSION_NPA_OFST (2) -#define PHY_AUTO_NEG_EXPANSION_LPNPA_MSK (0x8) -#define PHY_AUTO_NEG_EXPANSION_LPNPA_OFST (3) -#define PHY_AUTO_NEG_EXPANSION_PDF_MSK (0x10) -#define PHY_AUTO_NEG_EXPANSION_PDF_OFST (4) - -#define PHY_VENDOR_SPECIFIC (16) -#define PHY_VENDOR_SPECIFIC_RXCC_MSK (0x1) -#define PHY_VENDOR_SPECIFIC_RXCC_OFST (0) -#define PHY_VENDOR_SPECIFIC_PCSBP_MSK (0x2) -#define PHY_VENDOR_SPECIFIC_PCSBP_OFST (1) -#define PHY_VENDOR_SPECIFIC_RVSPOL_MSK (0x10) -#define PHY_VENDOR_SPECIFIC_RVSPOL_OFST (4) -#define PHY_VENDOR_SPECIFIC_APOL_MSK (0x20) -#define PHY_VENDOR_SPECIFIC_APOL_OFST (5) -#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_MSK (0x40) -#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_OFST (6) -#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_MSK (0x80) -#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_OFST (7) -#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_MSK (0x100) -#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_OFST (8) -#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_MSK (0x200) -#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_OFST (9) -#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_MSK (0x400) -#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_OFST (10) -#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_MSK (0x800) -#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_OFST (11) -#define PHY_VENDOR_SPECIFIC_TXHIM_MSK (0x1000) -#define PHY_VENDOR_SPECIFIC_TXHIM_OFST (12) -#define PHY_VENDOR_SPECIFIC_INT_LEVEL_MSK (0x4000) -#define PHY_VENDOR_SPECIFIC_INT_LEVEL_OFST (14) -#define PHY_VENDOR_SPECIFIC_RPTR_MSK (0x8000) -#define PHY_VENDOR_SPECIFIC_RPTR_OFST (15) - -#define PHY_IRQ_CONTROL (17) -#define PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK (0x1) -#define PHY_IRQ_CONTROL_ANEG_COMP_INT_OFST (0) -#define PHY_IRQ_CONTROL_RFAULT_INT_MSK (0x2) -#define PHY_IRQ_CONTROL_RFAULT_INT_OFST (1) -#define PHY_IRQ_CONTROL_LS_CHG_INT_MSK (0x4) -#define PHY_IRQ_CONTROL_LS_CHG_INT_OFST (2) -#define PHY_IRQ_CONTROL_LP_ACK_INT_MSK (0x8) -#define PHY_IRQ_CONTROL_LP_ACK_INT_OFST (3) -#define PHY_IRQ_CONTROL_PDF_INT_MSK (0x10) -#define PHY_IRQ_CONTROL_PDF_INT_OFST (4) -#define PHY_IRQ_CONTROL_PRX_INT_MSK (0x20) -#define PHY_IRQ_CONTROL_PRX_INT_OFST (5) -#define PHY_IRQ_CONTROL_RXER_INT_MSK (0x40) -#define PHY_IRQ_CONTROL_RXER_INT_OFST (6) -#define PHY_IRQ_CONTROL_JABBER_INT_MSK (0x80) -#define PHY_IRQ_CONTROL_JABBER_INT_OFST (7) -#define PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK (0x100) -#define PHY_IRQ_CONTROL_ANEG_COMP_IE_OFST (8) -#define PHY_IRQ_CONTROL_RFAULT_IE_MSK (0x200) -#define PHY_IRQ_CONTROL_RFAULT_IE_OFST (9) -#define PHY_IRQ_CONTROL_LS_CHG_IE_MSK (0x400) -#define PHY_IRQ_CONTROL_LS_CHG_IE_OFST (10) -#define PHY_IRQ_CONTROL_LP_ACK_IE_MSK (0x800) -#define PHY_IRQ_CONTROL_LP_ACK_IE_OFST (11) -#define PHY_IRQ_CONTROL_PDF_IE_MSK (0x1000) -#define PHY_IRQ_CONTROL_PDF_IE_OFST (12) -#define PHY_IRQ_CONTROL_PRX_IE_MSK (0x2000) -#define PHY_IRQ_CONTROL_PRX_IE_OFST (13) -#define PHY_IRQ_CONTROL_RXER_IE_MSK (0x4000) -#define PHY_IRQ_CONTROL_RXER_IE_OFST (14) -#define PHY_IRQ_CONTROL_JABBER_IE_MSK (0x8000) -#define PHY_IRQ_CONTROL_JABBER_IE_OFST (15) - -#define PHY_DIAGNOSTIC (18) -#define PHY_DIAGNOSTIC_RX_LOCK_MSK (0x100) -#define PHY_DIAGNOSTIC_RX_LOCK_OFST (8) -#define PHY_DIAGNOSTIC_RX_PASS_MSK (0x200) -#define PHY_DIAGNOSTIC_RX_PASS_OFST (9) -#define PHY_DIAGNOSTIC_RATE_MSK (0x400) -#define PHY_DIAGNOSTIC_RATE_OFST (10) -#define PHY_DIAGNOSTIC_DPLX_MSK (0x800) -#define PHY_DIAGNOSTIC_DPLX_OFST (11) -#define PHY_DIAGNOSTIC_ANEGF_MSK (0x1000) -#define PHY_DIAGNOSTIC_ANEGF_OFST (12) - -#endif /* __TDKPHY_H */ diff --git a/include/asm-arm/arch-epxa10db/timer00.h b/include/asm-arm/arch-epxa10db/timer00.h deleted file mode 100644 index 52a3fb58b59..00000000000 --- a/include/asm-arm/arch-epxa10db/timer00.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * - * This file contains the register definitions for the Excalibur - * Timer TIMER00. - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __TIMER00_H -#define __TIMER00_H - -/* - * Register definitions for the timers - */ - - -#define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 )) -#define TIMER0_CR_B_MSK (0x20) -#define TIMER0_CR_B_OFST (0x5) -#define TIMER0_CR_S_MSK (0x10) -#define TIMER0_CR_S_OFST (0x4) -#define TIMER0_CR_CI_MSK (0x08) -#define TIMER0_CR_CI_OFST (0x3) -#define TIMER0_CR_IE_MSK (0x04) -#define TIMER0_CR_IE_OFST (0x2) -#define TIMER0_CR_MODE_MSK (0x3) -#define TIMER0_CR_MODE_OFST (0) -#define TIMER0_CR_MODE_FREE (0) -#define TIMER0_CR_MODE_ONE (1) -#define TIMER0_CR_MODE_INTVL (2) - -#define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 )) -#define TIMER0_SR_B_MSK (0x20) -#define TIMER0_SR_B_OFST (0x5) -#define TIMER0_SR_S_MSK (0x10) -#define TIMER0_SR_S_OFST (0x4) -#define TIMER0_SR_CI_MSK (0x08) -#define TIMER0_SR_CI_OFST (0x3) -#define TIMER0_SR_IE_MSK (0x04) -#define TIMER0_SR_IE_OFST (0x2) -#define TIMER0_SR_MODE_MSK (0x3) -#define TIMER0_SR_MODE_OFST (0) -#define TIMER0_SR_MODE_FREE (0) -#define TIMER0_SR_MODE_ONE (1) -#define TIMER0_SR_MODE_INTVL (2) - -#define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x010 )) -#define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x020 )) -#define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x030 )) - -#define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 )) -#define TIMER1_CR_B_MSK (0x20) -#define TIMER1_CR_B_OFST (0x5) -#define TIMER1_CR_S_MSK (0x10) -#define TIMER1_CR_S_OFST (0x4) -#define TIMER1_CR_CI_MSK (0x08) -#define TIMER1_CR_CI_OFST (0x3) -#define TIMER1_CR_IE_MSK (0x04) -#define TIMER1_CR_IE_OFST (0x2) -#define TIMER1_CR_MODE_MSK (0x3) -#define TIMER1_CR_MODE_OFST (0) -#define TIMER1_CR_MODE_FREE (0) -#define TIMER1_CR_MODE_ONE (1) -#define TIMER1_CR_MODE_INTVL (2) - -#define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 )) -#define TIMER1_SR_B_MSK (0x20) -#define TIMER1_SR_B_OFST (0x5) -#define TIMER1_SR_S_MSK (0x10) -#define TIMER1_SR_S_OFST (0x4) -#define TIMER1_SR_CI_MSK (0x08) -#define TIMER1_SR_CI_OFST (0x3) -#define TIMER1_SR_IE_MSK (0x04) -#define TIMER1_SR_IE_OFST (0x2) -#define TIMER1_SR_MODE_MSK (0x3) -#define TIMER1_SR_MODE_OFST (0) -#define TIMER1_SR_MODE_FREE (0) -#define TIMER1_SR_MODE_ONE (1) -#define TIMER1_SR_MODE_INTVL (2) - -#define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x050 )) -#define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x060 )) -#define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x070 )) - -#endif /* __TIMER00_H */ diff --git a/include/asm-arm/arch-epxa10db/uart00.h b/include/asm-arm/arch-epxa10db/uart00.h deleted file mode 100644 index 5abd8914d68..00000000000 --- a/include/asm-arm/arch-epxa10db/uart00.h +++ /dev/null @@ -1,181 +0,0 @@ -/* * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __UART00_H -#define __UART00_H - -/* - * Register definitions for the UART - */ - -#define UART_TX_FIFO_SIZE (15) - -#define UART_RSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x00 )) -#define UART_RSR_RX_LEVEL_MSK (0x1f) -#define UART_RSR_RX_LEVEL_OFST (0) -#define UART_RSR_RE_MSK (0x80) -#define UART_RSR_RE_OFST (7) - -#define UART_RDS(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x04 )) -#define UART_RDS_BI_MSK (0x8) -#define UART_RDS_BI_OFST (4) -#define UART_RDS_FE_MSK (0x4) -#define UART_RDS_FE_OFST (2) -#define UART_RDS_PE_MSK (0x2) -#define UART_RDS_PE_OFST (1) -#define UART_RDS_OE_MSK (0x1) -#define UART_RDS_OE_OFST (0) - -#define UART_RD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x08 )) -#define UART_RD_RX_DATA_MSK (0xff) -#define UART_RD_RX_DATA_OFST (0) - -#define UART_TSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x0c )) -#define UART_TSR_TX_LEVEL_MSK (0x1f) -#define UART_TSR_TX_LEVEL_OFST (0) -#define UART_TSR_TXI_MSK (0x80) -#define UART_TSR_TXI_OFST (7) - -#define UART_TD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x10 )) -#define UART_TD_TX_DATA_MSK (0xff) -#define UART_TD_TX_DATA_OFST (0) - -#define UART_FCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x14 )) -#define UART_FCR_RX_THR_MSK (0xd0) -#define UART_FCR_RX_THR_OFST (5) -#define UART_FCR_RX_THR_1 (0x00) -#define UART_FCR_RX_THR_2 (0x20) -#define UART_FCR_RX_THR_4 (0x40) -#define UART_FCR_RX_THR_6 (0x60) -#define UART_FCR_RX_THR_8 (0x80) -#define UART_FCR_RX_THR_10 (0xa0) -#define UART_FCR_RX_THR_12 (0xc0) -#define UART_FCR_RX_THR_14 (0xd0) -#define UART_FCR_TX_THR_MSK (0x1c) -#define UART_FCR_TX_THR_OFST (2) -#define UART_FCR_TX_THR_0 (0x00) -#define UART_FCR_TX_THR_2 (0x04) -#define UART_FCR_TX_THR_4 (0x08) -#define UART_FCR_TX_THR_8 (0x0c) -#define UART_FCR_TX_THR_10 (0x10) -#define UART_FCR_TX_THR_12 (0x14) -#define UART_FCR_TX_THR_14 (0x18) -#define UART_FCR_TX_THR_15 (0x1c) -#define UART_FCR_RC_MSK (0x02) -#define UART_FCR_RC_OFST (1) -#define UART_FCR_TC_MSK (0x01) -#define UART_FCR_TC_OFST (0) - -#define UART_IES(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x18 )) -#define UART_IES_ME_MSK (0x8) -#define UART_IES_ME_OFST (3) -#define UART_IES_TIE_MSK (0x4) -#define UART_IES_TIE_OFST (2) -#define UART_IES_TE_MSK (0x2) -#define UART_IES_TE_OFST (1) -#define UART_IES_RE_MSK (0x1) -#define UART_IES_RE_OFST (0) - -#define UART_IEC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x1c )) -#define UART_IEC_ME_MSK (0x8) -#define UART_IEC_ME_OFST (3) -#define UART_IEC_TIE_MSK (0x4) -#define UART_IEC_TIE_OFST (2) -#define UART_IEC_TE_MSK (0x2) -#define UART_IEC_TE_OFST (1) -#define UART_IEC_RE_MSK (0x1) -#define UART_IEC_RE_OFST (0) - -#define UART_ISR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x20 )) -#define UART_ISR_MI_MSK (0x8) -#define UART_ISR_MI_OFST (3) -#define UART_ISR_TII_MSK (0x4) -#define UART_ISR_TII_OFST (2) -#define UART_ISR_TI_MSK (0x2) -#define UART_ISR_TI_OFST (1) -#define UART_ISR_RI_MSK (0x1) -#define UART_ISR_RI_OFST (0) - -#define UART_IID(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x24 )) -#define UART_IID_IID_MSK (0x7) -#define UART_IID_IID_OFST (0) - -#define UART_MC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x28 )) -#define UART_MC_OE_MSK (0x40) -#define UART_MC_OE_OFST (6) -#define UART_MC_SP_MSK (0x20) -#define UART_MC_SP_OFST (5) -#define UART_MC_EP_MSK (0x10) -#define UART_MC_EP_OFST (4) -#define UART_MC_PE_MSK (0x08) -#define UART_MC_PE_OFST (3) -#define UART_MC_ST_MSK (0x04) -#define UART_MC_ST_ONE (0x0) -#define UART_MC_ST_TWO (0x04) -#define UART_MC_ST_OFST (2) -#define UART_MC_CLS_MSK (0x03) -#define UART_MC_CLS_OFST (0) -#define UART_MC_CLS_CHARLEN_5 (0) -#define UART_MC_CLS_CHARLEN_6 (1) -#define UART_MC_CLS_CHARLEN_7 (2) -#define UART_MC_CLS_CHARLEN_8 (3) - -#define UART_MCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x2c )) -#define UART_MCR_AC_MSK (0x80) -#define UART_MCR_AC_OFST (7) -#define UART_MCR_AR_MSK (0x40) -#define UART_MCR_AR_OFST (6) -#define UART_MCR_BR_MSK (0x20) -#define UART_MCR_BR_OFST (5) -#define UART_MCR_LB_MSK (0x10) -#define UART_MCR_LB_OFST (4) -#define UART_MCR_DCD_MSK (0x08) -#define UART_MCR_DCD_OFST (3) -#define UART_MCR_RI_MSK (0x04) -#define UART_MCR_RI_OFST (2) -#define UART_MCR_DTR_MSK (0x02) -#define UART_MCR_DTR_OFST (1) -#define UART_MCR_RTS_MSK (0x01) -#define UART_MCR_RTS_OFST (0) - -#define UART_MSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x30 )) -#define UART_MSR_DCD_MSK (0x80) -#define UART_MSR_DCD_OFST (7) -#define UART_MSR_RI_MSK (0x40) -#define UART_MSR_RI_OFST (6) -#define UART_MSR_DSR_MSK (0x20) -#define UART_MSR_DSR_OFST (5) -#define UART_MSR_CTS_MSK (0x10) -#define UART_MSR_CTS_OFST (4) -#define UART_MSR_DDCD_MSK (0x08) -#define UART_MSR_DDCD_OFST (3) -#define UART_MSR_TERI_MSK (0x04) -#define UART_MSR_TERI_OFST (2) -#define UART_MSR_DDSR_MSK (0x02) -#define UART_MSR_DDSR_OFST (1) -#define UART_MSR_DCTS_MSK (0x01) -#define UART_MSR_DCTS_OFST (0) - -#define UART_DIV_LO(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x34 )) -#define UART_DIV_LO_DIV_MSK (0xff) -#define UART_DIV_LO_DIV_OFST (0) - -#define UART_DIV_HI(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x38 )) -#define UART_DIV_HI_DIV_MSK (0xff) -#define UART_DIV_HI_DIV_OFST (0) - -#endif /* __UART00_H */ diff --git a/include/asm-arm/arch-epxa10db/uncompress.h b/include/asm-arm/arch-epxa10db/uncompress.h deleted file mode 100644 index fdfe0e6848f..00000000000 --- a/include/asm-arm/arch-epxa10db/uncompress.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * linux/include/asm-arm/arch-epxa10db/uncompress.h - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include "asm/arch/platform.h" -#include "asm/hardware.h" -#define UART00_TYPE (volatile unsigned int*) -#include "asm/arch/uart00.h" - -/* - * This does not append a newline - */ -static void putstr(const char *s) -{ - while (*s) { - while ((*UART_TSR(EXC_UART00_BASE) & - UART_TSR_TX_LEVEL_MSK)==15) - barrier(); - - *UART_TD(EXC_UART00_BASE) = *s; - - if (*s == '\n') { - while ((*UART_TSR(EXC_UART00_BASE) & - UART_TSR_TX_LEVEL_MSK)==15) - barrier(); - - *UART_TD(EXC_UART00_BASE) = '\r'; - } - s++; - } -} - -/* - * nothing to do - */ -#define arch_decomp_setup() - -#define arch_decomp_wdog() diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h index f72b63309bc..3d7283d8440 100644 --- a/include/asm-arm/atomic.h +++ b/include/asm-arm/atomic.h @@ -175,6 +175,8 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) #endif /* __LINUX_ARM_ARCH__ */ +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + static inline int atomic_add_unless(atomic_t *v, int a, int u) { int c, old; diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index 0cf4d4f9960..fd0147e52db 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -56,7 +56,12 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); /* * Architecture ioremap implementation. + * + * __ioremap takes CPU physical address. + * + * __ioremap_pfn takes a Page Frame Number and an offset into that page */ +extern void __iomem * __ioremap_pfn(unsigned long, unsigned long, size_t, unsigned long); extern void __iomem * __ioremap(unsigned long, size_t, unsigned long); extern void __iounmap(void __iomem *addr); @@ -261,6 +266,7 @@ out: * * ioremap takes a PCI memory address, as specified in * Documentation/IO-mapping.txt. + * */ #ifndef __arch_ioremap #define ioremap(cookie,size) __ioremap(cookie,size,0) diff --git a/include/asm-arm/mach/map.h b/include/asm-arm/mach/map.h index b338936bde4..3351b77fab3 100644 --- a/include/asm-arm/mach/map.h +++ b/include/asm-arm/mach/map.h @@ -27,9 +27,6 @@ struct meminfo; #define MT_ROM 6 #define MT_IXP2000_DEVICE 7 -#define __phys_to_pfn(paddr) ((paddr) >> PAGE_SHIFT) -#define __pfn_to_phys(pfn) ((pfn) << PAGE_SHIFT) - extern void create_memmap_holes(struct meminfo *); extern void memtable_init(struct meminfo *); extern void iotable_init(struct map_desc *, int); diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index 3e572364ee7..3d7f08bd903 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h @@ -58,6 +58,12 @@ #endif /* + * Convert a physical address to a Page Frame Number and back + */ +#define __phys_to_pfn(paddr) ((paddr) >> PAGE_SHIFT) +#define __pfn_to_phys(pfn) ((pfn) << PAGE_SHIFT) + +/* * The module space lives between the addresses given by TASK_SIZE * and PAGE_OFFSET - it must be within 32MB of the kernel text. */ diff --git a/include/asm-arm/mutex.h b/include/asm-arm/mutex.h new file mode 100644 index 00000000000..6caa59f1f59 --- /dev/null +++ b/include/asm-arm/mutex.h @@ -0,0 +1,128 @@ +/* + * include/asm-arm/mutex.h + * + * ARM optimized mutex locking primitives + * + * Please look into asm-generic/mutex-xchg.h for a formal definition. + */ +#ifndef _ASM_MUTEX_H +#define _ASM_MUTEX_H + +#if __LINUX_ARM_ARCH__ < 6 +/* On pre-ARMv6 hardware the swp based implementation is the most efficient. */ +# include <asm-generic/mutex-xchg.h> +#else + +/* + * Attempting to lock a mutex on ARMv6+ can be done with a bastardized + * atomic decrement (it is not a reliable atomic decrement but it satisfies + * the defined semantics for our purpose, while being smaller and faster + * than a real atomic decrement or atomic swap. The idea is to attempt + * decrementing the lock value only once. If once decremented it isn't zero, + * or if its store-back fails due to a dispute on the exclusive store, we + * simply bail out immediately through the slow path where the lock will be + * reattempted until it succeeds. + */ +#define __mutex_fastpath_lock(count, fail_fn) \ +do { \ + int __ex_flag, __res; \ + \ + typecheck(atomic_t *, count); \ + typecheck_fn(fastcall void (*)(atomic_t *), fail_fn); \ + \ + __asm__ ( \ + "ldrex %0, [%2] \n" \ + "sub %0, %0, #1 \n" \ + "strex %1, %0, [%2] \n" \ + \ + : "=&r" (__res), "=&r" (__ex_flag) \ + : "r" (&(count)->counter) \ + : "cc","memory" ); \ + \ + if (unlikely(__res || __ex_flag)) \ + fail_fn(count); \ +} while (0) + +#define __mutex_fastpath_lock_retval(count, fail_fn) \ +({ \ + int __ex_flag, __res; \ + \ + typecheck(atomic_t *, count); \ + typecheck_fn(fastcall int (*)(atomic_t *), fail_fn); \ + \ + __asm__ ( \ + "ldrex %0, [%2] \n" \ + "sub %0, %0, #1 \n" \ + "strex %1, %0, [%2] \n" \ + \ + : "=&r" (__res), "=&r" (__ex_flag) \ + : "r" (&(count)->counter) \ + : "cc","memory" ); \ + \ + __res |= __ex_flag; \ + if (unlikely(__res != 0)) \ + __res = fail_fn(count); \ + __res; \ +}) + +/* + * Same trick is used for the unlock fast path. However the original value, + * rather than the result, is used to test for success in order to have + * better generated assembly. + */ +#define __mutex_fastpath_unlock(count, fail_fn) \ +do { \ + int __ex_flag, __res, __orig; \ + \ + typecheck(atomic_t *, count); \ + typecheck_fn(fastcall void (*)(atomic_t *), fail_fn); \ + \ + __asm__ ( \ + "ldrex %0, [%3] \n" \ + "add %1, %0, #1 \n" \ + "strex %2, %1, [%3] \n" \ + \ + : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag) \ + : "r" (&(count)->counter) \ + : "cc","memory" ); \ + \ + if (unlikely(__orig || __ex_flag)) \ + fail_fn(count); \ +} while (0) + +/* + * If the unlock was done on a contended lock, or if the unlock simply fails + * then the mutex remains locked. + */ +#define __mutex_slowpath_needs_to_unlock() 1 + +/* + * For __mutex_fastpath_trylock we use another construct which could be + * described as a "single value cmpxchg". + * + * This provides the needed trylock semantics like cmpxchg would, but it is + * lighter and less generic than a true cmpxchg implementation. + */ +static inline int +__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) +{ + int __ex_flag, __res, __orig; + + __asm__ ( + + "1: ldrex %0, [%3] \n" + "subs %1, %0, #1 \n" + "strexeq %2, %1, [%3] \n" + "movlt %0, #0 \n" + "cmpeq %2, #0 \n" + "bgt 1b \n" + + : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag) + : "r" (&count->counter) + : "cc", "memory" ); + + return __orig; +} + +#endif +#endif diff --git a/include/asm-arm26/atomic.h b/include/asm-arm26/atomic.h index 3074b0e7634..1552c865399 100644 --- a/include/asm-arm26/atomic.h +++ b/include/asm-arm26/atomic.h @@ -76,6 +76,8 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new) return ret; } +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + static inline int atomic_add_unless(atomic_t *v, int a, int u) { int ret; diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h index 2df2c7aa19b..0b51a87e553 100644 --- a/include/asm-cris/atomic.h +++ b/include/asm-cris/atomic.h @@ -136,6 +136,8 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new) return ret; } +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + static inline int atomic_add_unless(atomic_t *v, int a, int u) { int ret; diff --git a/include/asm-cris/mutex.h b/include/asm-cris/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-cris/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-frv/atomic.h b/include/asm-frv/atomic.h index 9c9e9499cfd..a59f684b4f3 100644 --- a/include/asm-frv/atomic.h +++ b/include/asm-frv/atomic.h @@ -328,6 +328,7 @@ extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new); #endif #define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new)) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) #define atomic_add_unless(v, a, u) \ ({ \ diff --git a/include/asm-frv/mutex.h b/include/asm-frv/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-frv/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-generic/mutex-dec.h b/include/asm-generic/mutex-dec.h new file mode 100644 index 00000000000..74b18cda169 --- /dev/null +++ b/include/asm-generic/mutex-dec.h @@ -0,0 +1,110 @@ +/* + * asm-generic/mutex-dec.h + * + * Generic implementation of the mutex fastpath, based on atomic + * decrement/increment. + */ +#ifndef _ASM_GENERIC_MUTEX_DEC_H +#define _ASM_GENERIC_MUTEX_DEC_H + +/** + * __mutex_fastpath_lock - try to take the lock by moving the count + * from 1 to a 0 value + * @count: pointer of type atomic_t + * @fail_fn: function to call if the original value was not 1 + * + * Change the count from 1 to a value lower than 1, and call <fail_fn> if + * it wasn't 1 originally. This function MUST leave the value lower than + * 1 even when the "1" assertion wasn't true. + */ +#define __mutex_fastpath_lock(count, fail_fn) \ +do { \ + if (unlikely(atomic_dec_return(count) < 0)) \ + fail_fn(count); \ + else \ + smp_mb(); \ +} while (0) + +/** + * __mutex_fastpath_lock_retval - try to take the lock by moving the count + * from 1 to a 0 value + * @count: pointer of type atomic_t + * @fail_fn: function to call if the original value was not 1 + * + * Change the count from 1 to a value lower than 1, and call <fail_fn> if + * it wasn't 1 originally. This function returns 0 if the fastpath succeeds, + * or anything the slow path function returns. + */ +static inline int +__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) +{ + if (unlikely(atomic_dec_return(count) < 0)) + return fail_fn(count); + else { + smp_mb(); + return 0; + } +} + +/** + * __mutex_fastpath_unlock - try to promote the count from 0 to 1 + * @count: pointer of type atomic_t + * @fail_fn: function to call if the original value was not 0 + * + * Try to promote the count from 0 to 1. If it wasn't 0, call <fail_fn>. + * In the failure case, this function is allowed to either set the value to + * 1, or to set it to a value lower than 1. + * + * If the implementation sets it to a value of lower than 1, then the + * __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs + * to return 0 otherwise. + */ +#define __mutex_fastpath_unlock(count, fail_fn) \ +do { \ + smp_mb(); \ + if (unlikely(atomic_inc_return(count) <= 0)) \ + fail_fn(count); \ +} while (0) + +#define __mutex_slowpath_needs_to_unlock() 1 + +/** + * __mutex_fastpath_trylock - try to acquire the mutex, without waiting + * + * @count: pointer of type atomic_t + * @fail_fn: fallback function + * + * Change the count from 1 to a value lower than 1, and return 0 (failure) + * if it wasn't 1 originally, or return 1 (success) otherwise. This function + * MUST leave the value lower than 1 even when the "1" assertion wasn't true. + * Additionally, if the value was < 0 originally, this function must not leave + * it to 0 on failure. + * + * If the architecture has no effective trylock variant, it should call the + * <fail_fn> spinlock-based trylock variant unconditionally. + */ +static inline int +__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) +{ + /* + * We have two variants here. The cmpxchg based one is the best one + * because it never induce a false contention state. It is included + * here because architectures using the inc/dec algorithms over the + * xchg ones are much more likely to support cmpxchg natively. + * + * If not we fall back to the spinlock based variant - that is + * just as efficient (and simpler) as a 'destructive' probing of + * the mutex state would be. + */ +#ifdef __HAVE_ARCH_CMPXCHG + if (likely(atomic_cmpxchg(count, 1, 0)) == 1) { + smp_mb(); + return 1; + } + return 0; +#else + return fail_fn(count); +#endif +} + +#endif diff --git a/include/asm-generic/mutex-null.h b/include/asm-generic/mutex-null.h new file mode 100644 index 00000000000..5cf8b7ce0c4 --- /dev/null +++ b/include/asm-generic/mutex-null.h @@ -0,0 +1,24 @@ +/* + * asm-generic/mutex-null.h + * + * Generic implementation of the mutex fastpath, based on NOP :-) + * + * This is used by the mutex-debugging infrastructure, but it can also + * be used by architectures that (for whatever reason) want to use the + * spinlock based slowpath. + */ +#ifndef _ASM_GENERIC_MUTEX_NULL_H +#define _ASM_GENERIC_MUTEX_NULL_H + +/* extra parameter only needed for mutex debugging: */ +#ifndef __IP__ +# define __IP__ +#endif + +#define __mutex_fastpath_lock(count, fail_fn) fail_fn(count __RET_IP__) +#define __mutex_fastpath_lock_retval(count, fail_fn) fail_fn(count __RET_IP__) +#define __mutex_fastpath_unlock(count, fail_fn) fail_fn(count __RET_IP__) +#define __mutex_fastpath_trylock(count, fail_fn) fail_fn(count) +#define __mutex_slowpath_needs_to_unlock() 1 + +#endif diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h new file mode 100644 index 00000000000..1d24f47e6c4 --- /dev/null +++ b/include/asm-generic/mutex-xchg.h @@ -0,0 +1,117 @@ +/* + * asm-generic/mutex-xchg.h + * + * Generic implementation of the mutex fastpath, based on xchg(). + * + * NOTE: An xchg based implementation is less optimal than an atomic + * decrement/increment based implementation. If your architecture + * has a reasonable atomic dec/inc then you should probably use + * asm-generic/mutex-dec.h instead, or you could open-code an + * optimized version in asm/mutex.h. + */ +#ifndef _ASM_GENERIC_MUTEX_XCHG_H +#define _ASM_GENERIC_MUTEX_XCHG_H + +/** + * __mutex_fastpath_lock - try to take the lock by moving the count + * from 1 to a 0 value + * @count: pointer of type atomic_t + * @fail_fn: function to call if the original value was not 1 + * + * Change the count from 1 to a value lower than 1, and call <fail_fn> if it + * wasn't 1 originally. This function MUST leave the value lower than 1 + * even when the "1" assertion wasn't true. + */ +#define __mutex_fastpath_lock(count, fail_fn) \ +do { \ + if (unlikely(atomic_xchg(count, 0) != 1)) \ + fail_fn(count); \ + else \ + smp_mb(); \ +} while (0) + + +/** + * __mutex_fastpath_lock_retval - try to take the lock by moving the count + * from 1 to a 0 value + * @count: pointer of type atomic_t + * @fail_fn: function to call if the original value was not 1 + * + * Change the count from 1 to a value lower than 1, and call <fail_fn> if it + * wasn't 1 originally. This function returns 0 if the fastpath succeeds, + * or anything the slow path function returns + */ +static inline int +__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) +{ + if (unlikely(atomic_xchg(count, 0) != 1)) + return fail_fn(count); + else { + smp_mb(); + return 0; + } +} + +/** + * __mutex_fastpath_unlock - try to promote the mutex from 0 to 1 + * @count: pointer of type atomic_t + * @fail_fn: function to call if the original value was not 0 + * + * try to promote the mutex from 0 to 1. if it wasn't 0, call <function> + * In the failure case, this function is allowed to either set the value to + * 1, or to set it to a value lower than one. + * If the implementation sets it to a value of lower than one, the + * __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs + * to return 0 otherwise. + */ +#define __mutex_fastpath_unlock(count, fail_fn) \ +do { \ + smp_mb(); \ + if (unlikely(atomic_xchg(count, 1) != 0)) \ + fail_fn(count); \ +} while (0) + +#define __mutex_slowpath_needs_to_unlock() 0 + +/** + * __mutex_fastpath_trylock - try to acquire the mutex, without waiting + * + * @count: pointer of type atomic_t + * @fail_fn: spinlock based trylock implementation + * + * Change the count from 1 to a value lower than 1, and return 0 (failure) + * if it wasn't 1 originally, or return 1 (success) otherwise. This function + * MUST leave the value lower than 1 even when the "1" assertion wasn't true. + * Additionally, if the value was < 0 originally, this function must not leave + * it to 0 on failure. + * + * If the architecture has no effective trylock variant, it should call the + * <fail_fn> spinlock-based trylock variant unconditionally. + */ +static inline int +__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) +{ + int prev = atomic_xchg(count, 0); + + if (unlikely(prev < 0)) { + /* + * The lock was marked contended so we must restore that + * state. If while doing so we get back a prev value of 1 + * then we just own it. + * + * [ In the rare case of the mutex going to 1, to 0, to -1 + * and then back to 0 in this few-instructions window, + * this has the potential to trigger the slowpath for the + * owner's unlock path needlessly, but that's not a problem + * in practice. ] + */ + prev = atomic_xchg(count, prev); + if (prev < 0) + prev = 0; + } + smp_mb(); + + return prev; +} + +#endif diff --git a/include/asm-h8300/atomic.h b/include/asm-h8300/atomic.h index d891541e89c..21f54428c86 100644 --- a/include/asm-h8300/atomic.h +++ b/include/asm-h8300/atomic.h @@ -95,6 +95,8 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new) return ret; } +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + static inline int atomic_add_unless(atomic_t *v, int a, int u) { int ret; diff --git a/include/asm-h8300/mutex.h b/include/asm-h8300/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-h8300/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-i386/atomic.h b/include/asm-i386/atomic.h index 7a5472d7709..de649d3aa2d 100644 --- a/include/asm-i386/atomic.h +++ b/include/asm-i386/atomic.h @@ -216,6 +216,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t *v) } #define atomic_cmpxchg(v, old, new) ((int)cmpxchg(&((v)->counter), old, new)) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) /** * atomic_add_unless - add unless the number is a given value diff --git a/include/asm-i386/mutex.h b/include/asm-i386/mutex.h new file mode 100644 index 00000000000..4e5e3de1b9a --- /dev/null +++ b/include/asm-i386/mutex.h @@ -0,0 +1,124 @@ +/* + * Assembly implementation of the mutex fastpath, based on atomic + * decrement/increment. + * + * started by Ingo Molnar: + * + * Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar <mingo@redhat.com> + */ +#ifndef _ASM_MUTEX_H +#define _ASM_MUTEX_H + +/** + * __mutex_fastpath_lock - try to take the lock by moving the count + * from 1 to a 0 value + * @count: pointer of type atomic_t + * @fn: function to call if the original value was not 1 + * + * Change the count from 1 to a value lower than 1, and call <fn> if it + * wasn't 1 originally. This function MUST leave the value lower than 1 + * even when the "1" assertion wasn't true. + */ +#define __mutex_fastpath_lock(count, fail_fn) \ +do { \ + unsigned int dummy; \ + \ + typecheck(atomic_t *, count); \ + typecheck_fn(fastcall void (*)(atomic_t *), fail_fn); \ + \ + __asm__ __volatile__( \ + LOCK " decl (%%eax) \n" \ + " js "#fail_fn" \n" \ + \ + :"=a" (dummy) \ + : "a" (count) \ + : "memory", "ecx", "edx"); \ +} while (0) + + +/** + * __mutex_fastpath_lock_retval - try to take the lock by moving the count + * from 1 to a 0 value + * @count: pointer of type atomic_t + * @fail_fn: function to call if the original value was not 1 + * + * Change the count from 1 to a value lower than 1, and call <fail_fn> if it + * wasn't 1 originally. This function returns 0 if the fastpath succeeds, + * or anything the slow path function returns + */ +static inline int +__mutex_fastpath_lock_retval(atomic_t *count, + int fastcall (*fail_fn)(atomic_t *)) +{ + if (unlikely(atomic_dec_return(count) < 0)) + return fail_fn(count); + else + return 0; +} + +/** + * __mutex_fastpath_unlock - try to promote the mutex from 0 to 1 + * @count: pointer of type atomic_t + * @fail_fn: function to call if the original value was not 0 + * + * try to promote the mutex from 0 to 1. if it wasn't 0, call <fail_fn>. + * In the failure case, this function is allowed to either set the value + * to 1, or to set it to a value lower than 1. + * + * If the implementation sets it to a value of lower than 1, the + * __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs + * to return 0 otherwise. + */ +#define __mutex_fastpath_unlock(count, fail_fn) \ +do { \ + unsigned int dummy; \ + \ + typecheck(atomic_t *, count); \ + typecheck_fn(fastcall void (*)(atomic_t *), fail_fn); \ + \ + __asm__ __volatile__( \ + LOCK " incl (%%eax) \n" \ + " jle "#fail_fn" \n" \ + \ + :"=a" (dummy) \ + : "a" (count) \ + : "memory", "ecx", "edx"); \ +} while (0) + +#define __mutex_slowpath_needs_to_unlock() 1 + +/** + * __mutex_fastpath_trylock - try to acquire the mutex, without waiting + * + * @count: pointer of type atomic_t + * @fail_fn: fallback function + * + * Change the count from 1 to a value lower than 1, and return 0 (failure) + * if it wasn't 1 originally, or return 1 (success) otherwise. This function + * MUST leave the value lower than 1 even when the "1" assertion wasn't true. + * Additionally, if the value was < 0 originally, this function must not leave + * it to 0 on failure. + */ +static inline int +__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) +{ + /* + * We have two variants here. The cmpxchg based one is the best one + * because it never induce a false contention state. It is included + * here because architectures using the inc/dec algorithms over the + * xchg ones are much more likely to support cmpxchg natively. + * + * If not we fall back to the spinlock based variant - that is + * just as efficient (and simpler) as a 'destructive' probing of + * the mutex state would be. + */ +#ifdef __HAVE_ARCH_CMPXCHG + if (likely(atomic_cmpxchg(count, 1, 0)) == 1) + return 1; + return 0; +#else + return fail_fn(count); +#endif +} + +#endif diff --git a/include/asm-ia64/atomic.h b/include/asm-ia64/atomic.h index 15cf7984c48..d3e0dfa99e1 100644 --- a/include/asm-ia64/atomic.h +++ b/include/asm-ia64/atomic.h @@ -89,6 +89,7 @@ ia64_atomic64_sub (__s64 i, atomic64_t *v) } #define atomic_cmpxchg(v, old, new) ((int)cmpxchg(&((v)->counter), old, new)) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) #define atomic_add_unless(v, a, u) \ ({ \ diff --git a/include/asm-ia64/mutex.h b/include/asm-ia64/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-ia64/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-m32r/atomic.h b/include/asm-m32r/atomic.h index 70761278b6c..3122fe106f0 100644 --- a/include/asm-m32r/atomic.h +++ b/include/asm-m32r/atomic.h @@ -243,6 +243,7 @@ static __inline__ int atomic_dec_return(atomic_t *v) #define atomic_add_negative(i,v) (atomic_add_return((i), (v)) < 0) #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) /** * atomic_add_unless - add unless the number is a given value diff --git a/include/asm-m32r/mutex.h b/include/asm-m32r/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-m32r/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-m68k/atomic.h b/include/asm-m68k/atomic.h index b8a4e75d679..a4a84d5c65d 100644 --- a/include/asm-m68k/atomic.h +++ b/include/asm-m68k/atomic.h @@ -140,6 +140,7 @@ static inline void atomic_set_mask(unsigned long mask, unsigned long *v) } #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) #define atomic_add_unless(v, a, u) \ ({ \ diff --git a/include/asm-m68k/mutex.h b/include/asm-m68k/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-m68k/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-m68knommu/atomic.h b/include/asm-m68knommu/atomic.h index 1702dbe9318..6c4e4b63e45 100644 --- a/include/asm-m68knommu/atomic.h +++ b/include/asm-m68knommu/atomic.h @@ -129,6 +129,7 @@ static inline int atomic_sub_return(int i, atomic_t * v) } #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) #define atomic_add_unless(v, a, u) \ ({ \ diff --git a/include/asm-m68knommu/mutex.h b/include/asm-m68knommu/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-m68knommu/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 92256e43a93..94a95872d72 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -289,6 +289,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) } #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) /** * atomic_add_unless - add unless the number is a given value diff --git a/include/asm-mips/mutex.h b/include/asm-mips/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-mips/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-parisc/atomic.h b/include/asm-parisc/atomic.h index 64ebd086c40..2ca56d34aaa 100644 --- a/include/asm-parisc/atomic.h +++ b/include/asm-parisc/atomic.h @@ -165,6 +165,7 @@ static __inline__ int atomic_read(const atomic_t *v) /* exported interface */ #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) /** * atomic_add_unless - add unless the number is a given value diff --git a/include/asm-parisc/mutex.h b/include/asm-parisc/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-parisc/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-powerpc/atomic.h b/include/asm-powerpc/atomic.h index ae395a0632a..248f9aec959 100644 --- a/include/asm-powerpc/atomic.h +++ b/include/asm-powerpc/atomic.h @@ -165,6 +165,7 @@ static __inline__ int atomic_dec_return(atomic_t *v) } #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) /** * atomic_add_unless - add unless the number is a given value diff --git a/include/asm-powerpc/mutex.h b/include/asm-powerpc/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-powerpc/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-powerpc/smu.h b/include/asm-powerpc/smu.h index 134c2b5be0f..82ce4760777 100644 --- a/include/asm-powerpc/smu.h +++ b/include/asm-powerpc/smu.h @@ -22,7 +22,7 @@ /* * Partition info commands * - * These commands are used to retreive the sdb-partition-XX datas from + * These commands are used to retrieve the sdb-partition-XX datas from * the SMU. The lenght is always 2. First byte is the subcommand code * and second byte is the partition ID. * @@ -225,7 +225,7 @@ * * SMU_CMD_MISC_ee_GET_DATABLOCK_REC is used, among others, to * transfer blocks of data from the SMU. So far, I've decrypted it's - * usage to retreive partition data. In order to do that, you have to + * usage to retrieve partition data. In order to do that, you have to * break your transfer in "chunks" since that command cannot transfer * more than a chunk at a time. The chunk size used by OF is 0xe bytes, * but it seems that the darwin driver will let you do 0x1e bytes if @@ -556,7 +556,7 @@ struct smu_user_cmd_hdr __u32 cmdtype; #define SMU_CMDTYPE_SMU 0 /* SMU command */ #define SMU_CMDTYPE_WANTS_EVENTS 1 /* switch fd to events mode */ -#define SMU_CMDTYPE_GET_PARTITION 2 /* retreive an sdb partition */ +#define SMU_CMDTYPE_GET_PARTITION 2 /* retrieve an sdb partition */ __u8 cmd; /* SMU command byte */ __u8 pad[3]; /* padding */ diff --git a/include/asm-s390/atomic.h b/include/asm-s390/atomic.h index d82aedf616f..be6fefe223d 100644 --- a/include/asm-s390/atomic.h +++ b/include/asm-s390/atomic.h @@ -75,6 +75,8 @@ static __inline__ void atomic_set_mask(unsigned long mask, atomic_t * v) __CS_LOOP(v, mask, "or"); } +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + static __inline__ int atomic_cmpxchg(atomic_t *v, int old, int new) { __asm__ __volatile__(" cs %0,%3,0(%2)\n" diff --git a/include/asm-s390/mutex.h b/include/asm-s390/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-s390/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-sh/atomic.h b/include/asm-sh/atomic.h index 618d8e0de34..fb627de217f 100644 --- a/include/asm-sh/atomic.h +++ b/include/asm-sh/atomic.h @@ -101,6 +101,8 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new) return ret; } +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + static inline int atomic_add_unless(atomic_t *v, int a, int u) { int ret; diff --git a/include/asm-sh/mutex.h b/include/asm-sh/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-sh/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-sh64/atomic.h b/include/asm-sh64/atomic.h index f3ce5c0df13..28f2ea9b567 100644 --- a/include/asm-sh64/atomic.h +++ b/include/asm-sh64/atomic.h @@ -113,6 +113,8 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new) return ret; } +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + static inline int atomic_add_unless(atomic_t *v, int a, int u) { int ret; diff --git a/include/asm-sh64/mutex.h b/include/asm-sh64/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-sh64/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-sparc/atomic.h b/include/asm-sparc/atomic.h index accb4967e9d..e1033170bd3 100644 --- a/include/asm-sparc/atomic.h +++ b/include/asm-sparc/atomic.h @@ -20,6 +20,7 @@ typedef struct { volatile int counter; } atomic_t; extern int __atomic_add_return(int, atomic_t *); extern int atomic_cmpxchg(atomic_t *, int, int); +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) extern int atomic_add_unless(atomic_t *, int, int); extern void atomic_set(atomic_t *, int); diff --git a/include/asm-sparc/mutex.h b/include/asm-sparc/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-sparc/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-sparc64/atomic.h b/include/asm-sparc64/atomic.h index 11f5aa5d108..25256bdc8aa 100644 --- a/include/asm-sparc64/atomic.h +++ b/include/asm-sparc64/atomic.h @@ -72,6 +72,7 @@ extern int atomic64_sub_ret(int, atomic64_t *); #define atomic64_add_negative(i, v) (atomic64_add_ret(i, v) < 0) #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) #define atomic_add_unless(v, a, u) \ ({ \ diff --git a/include/asm-sparc64/mutex.h b/include/asm-sparc64/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-sparc64/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-um/mutex.h b/include/asm-um/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-um/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-v850/atomic.h b/include/asm-v850/atomic.h index f5b9ab6f4e7..166df00457e 100644 --- a/include/asm-v850/atomic.h +++ b/include/asm-v850/atomic.h @@ -104,6 +104,8 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new) return ret; } +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + static inline int atomic_add_unless(atomic_t *v, int a, int u) { int ret; diff --git a/include/asm-v850/mutex.h b/include/asm-v850/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-v850/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/asm-x86_64/atomic.h b/include/asm-x86_64/atomic.h index 72eb071488c..6b540237a2f 100644 --- a/include/asm-x86_64/atomic.h +++ b/include/asm-x86_64/atomic.h @@ -389,6 +389,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t *v) #define atomic64_dec_return(v) (atomic64_sub_return(1,v)) #define atomic_cmpxchg(v, old, new) ((int)cmpxchg(&((v)->counter), old, new)) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) /** * atomic_add_unless - add unless the number is a given value diff --git a/include/asm-x86_64/mutex.h b/include/asm-x86_64/mutex.h new file mode 100644 index 00000000000..818abfd262d --- /dev/null +++ b/include/asm-x86_64/mutex.h @@ -0,0 +1,113 @@ +/* + * Assembly implementation of the mutex fastpath, based on atomic + * decrement/increment. + * + * started by Ingo Molnar: + * + * Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar <mingo@redhat.com> + */ +#ifndef _ASM_MUTEX_H +#define _ASM_MUTEX_H + +/** + * __mutex_fastpath_lock - decrement and call function if negative + * @v: pointer of type atomic_t + * @fail_fn: function to call if the result is negative + * + * Atomically decrements @v and calls <fail_fn> if the result is negative. + */ +#define __mutex_fastpath_lock(v, fail_fn) \ +do { \ + unsigned long dummy; \ + \ + typecheck(atomic_t *, v); \ + typecheck_fn(fastcall void (*)(atomic_t *), fail_fn); \ + \ + __asm__ __volatile__( \ + LOCK " decl (%%rdi) \n" \ + " js 2f \n" \ + "1: \n" \ + \ + LOCK_SECTION_START("") \ + "2: call "#fail_fn" \n" \ + " jmp 1b \n" \ + LOCK_SECTION_END \ + \ + :"=D" (dummy) \ + : "D" (v) \ + : "rax", "rsi", "rdx", "rcx", \ + "r8", "r9", "r10", "r11", "memory"); \ +} while (0) + +/** + * __mutex_fastpath_lock_retval - try to take the lock by moving the count + * from 1 to a 0 value + * @count: pointer of type atomic_t + * @fail_fn: function to call if the original value was not 1 + * + * Change the count from 1 to a value lower than 1, and call <fail_fn> if + * it wasn't 1 originally. This function returns 0 if the fastpath succeeds, + * or anything the slow path function returns + */ +static inline int +__mutex_fastpath_lock_retval(atomic_t *count, + int fastcall (*fail_fn)(atomic_t *)) +{ + if (unlikely(atomic_dec_return(count) < 0)) + return fail_fn(count); + else + return 0; +} + +/** + * __mutex_fastpath_unlock - increment and call function if nonpositive + * @v: pointer of type atomic_t + * @fail_fn: function to call if the result is nonpositive + * + * Atomically increments @v and calls <fail_fn> if the result is nonpositive. + */ +#define __mutex_fastpath_unlock(v, fail_fn) \ +do { \ + unsigned long dummy; \ + \ + typecheck(atomic_t *, v); \ + typecheck_fn(fastcall void (*)(atomic_t *), fail_fn); \ + \ + __asm__ __volatile__( \ + LOCK " incl (%%rdi) \n" \ + " jle 2f \n" \ + "1: \n" \ + \ + LOCK_SECTION_START("") \ + "2: call "#fail_fn" \n" \ + " jmp 1b \n" \ + LOCK_SECTION_END \ + \ + :"=D" (dummy) \ + : "D" (v) \ + : "rax", "rsi", "rdx", "rcx", \ + "r8", "r9", "r10", "r11", "memory"); \ +} while (0) + +#define __mutex_slowpath_needs_to_unlock() 1 + +/** + * __mutex_fastpath_trylock - try to acquire the mutex, without waiting + * + * @count: pointer of type atomic_t + * @fail_fn: fallback function + * + * Change the count from 1 to 0 and return 1 (success), or return 0 (failure) + * if it wasn't 1 originally. [the fallback function is never used on + * x86_64, because all x86_64 CPUs have a CMPXCHG instruction.] + */ +static inline int +__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) +{ + if (likely(atomic_cmpxchg(count, 1, 0)) == 1) + return 1; + else + return 0; +} + +#endif diff --git a/include/asm-xtensa/atomic.h b/include/asm-xtensa/atomic.h index e2ce06b101a..fe105a12392 100644 --- a/include/asm-xtensa/atomic.h +++ b/include/asm-xtensa/atomic.h @@ -224,6 +224,7 @@ static inline int atomic_sub_return(int i, atomic_t * v) #define atomic_add_negative(i,v) (atomic_add_return((i),(v)) < 0) #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) /** * atomic_add_unless - add unless the number is a given value diff --git a/include/asm-xtensa/mutex.h b/include/asm-xtensa/mutex.h new file mode 100644 index 00000000000..458c1f7fbc1 --- /dev/null +++ b/include/asm-xtensa/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include <asm-generic/mutex-dec.h> diff --git a/include/linux/compat_ioctl.h b/include/linux/compat_ioctl.h index 119f9d064cc..339878952f1 100644 --- a/include/linux/compat_ioctl.h +++ b/include/linux/compat_ioctl.h @@ -218,32 +218,6 @@ COMPATIBLE_IOCTL(VT_RESIZE) COMPATIBLE_IOCTL(VT_RESIZEX) COMPATIBLE_IOCTL(VT_LOCKSWITCH) COMPATIBLE_IOCTL(VT_UNLOCKSWITCH) -/* Little v */ -/* Little v, the video4linux ioctls (conflict?) */ -COMPATIBLE_IOCTL(VIDIOCGCAP) -COMPATIBLE_IOCTL(VIDIOCGCHAN) -COMPATIBLE_IOCTL(VIDIOCSCHAN) -COMPATIBLE_IOCTL(VIDIOCGPICT) -COMPATIBLE_IOCTL(VIDIOCSPICT) -COMPATIBLE_IOCTL(VIDIOCCAPTURE) -COMPATIBLE_IOCTL(VIDIOCKEY) -COMPATIBLE_IOCTL(VIDIOCGAUDIO) -COMPATIBLE_IOCTL(VIDIOCSAUDIO) -COMPATIBLE_IOCTL(VIDIOCSYNC) -COMPATIBLE_IOCTL(VIDIOCMCAPTURE) -COMPATIBLE_IOCTL(VIDIOCGMBUF) -COMPATIBLE_IOCTL(VIDIOCGUNIT) -COMPATIBLE_IOCTL(VIDIOCGCAPTURE) -COMPATIBLE_IOCTL(VIDIOCSCAPTURE) -/* BTTV specific... */ -COMPATIBLE_IOCTL(_IOW('v', BASE_VIDIOCPRIVATE+0, char [256])) -COMPATIBLE_IOCTL(_IOR('v', BASE_VIDIOCPRIVATE+1, char [256])) -COMPATIBLE_IOCTL(_IOR('v' , BASE_VIDIOCPRIVATE+2, unsigned int)) -COMPATIBLE_IOCTL(_IOW('v' , BASE_VIDIOCPRIVATE+3, char [16])) /* struct bttv_pll_info */ -COMPATIBLE_IOCTL(_IOR('v' , BASE_VIDIOCPRIVATE+4, int)) -COMPATIBLE_IOCTL(_IOR('v' , BASE_VIDIOCPRIVATE+5, int)) -COMPATIBLE_IOCTL(_IOR('v' , BASE_VIDIOCPRIVATE+6, int)) -COMPATIBLE_IOCTL(_IOR('v' , BASE_VIDIOCPRIVATE+7, int)) /* Little p (/dev/rtc, /dev/envctrl, etc.) */ COMPATIBLE_IOCTL(RTC_AIE_ON) COMPATIBLE_IOCTL(RTC_AIE_OFF) diff --git a/include/linux/crypto.h b/include/linux/crypto.h index 3c89df6e776..d88bf8aa8b4 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h @@ -3,6 +3,7 @@ * * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> * Copyright (c) 2002 David S. Miller (davem@redhat.com) + * Copyright (c) 2005 Herbert Xu <herbert@gondor.apana.org.au> * * Portions derived from Cryptoapi, by Alexander Kjeldaas <astor@fast.no> * and Nettle, by Niels Möller. @@ -126,7 +127,11 @@ struct crypto_alg { unsigned int cra_blocksize; unsigned int cra_ctxsize; unsigned int cra_alignmask; + + int cra_priority; + const char cra_name[CRYPTO_MAX_ALG_NAME]; + const char cra_driver_name[CRYPTO_MAX_ALG_NAME]; union { struct cipher_alg cipher; diff --git a/include/linux/dvb/frontend.h b/include/linux/dvb/frontend.h index d41df7047ed..c8cbd90ba37 100644 --- a/include/linux/dvb/frontend.h +++ b/include/linux/dvb/frontend.h @@ -240,6 +240,15 @@ struct dvb_frontend_event { }; +/** + * When set, this flag will disable any zigzagging or other "normal" tuning + * behaviour. Additionally, there will be no automatic monitoring of the lock + * status, and hence no frontend events will be generated. If a frontend device + * is closed, this flag will be automatically turned off when the device is + * reopened read-write. + */ +#define FE_TUNE_MODE_ONESHOT 0x01 + #define FE_GET_INFO _IOR('o', 61, struct dvb_frontend_info) @@ -260,6 +269,7 @@ struct dvb_frontend_event { #define FE_SET_FRONTEND _IOW('o', 76, struct dvb_frontend_parameters) #define FE_GET_FRONTEND _IOR('o', 77, struct dvb_frontend_parameters) +#define FE_SET_FRONTEND_TUNE_MODE _IO('o', 81) /* unsigned int */ #define FE_GET_EVENT _IOR('o', 78, struct dvb_frontend_event) #define FE_DISHNETWORK_SEND_LEGACY_CMD _IO('o', 80) /* unsigned int */ diff --git a/include/linux/elevator.h b/include/linux/elevator.h index 4a6f50e31c7..23fe746a1d5 100644 --- a/include/linux/elevator.h +++ b/include/linux/elevator.h @@ -66,7 +66,7 @@ struct elevator_type }; /* - * each queue has an elevator_queue assoicated with it + * each queue has an elevator_queue associated with it */ struct elevator_queue { diff --git a/include/linux/ext3_fs_i.h b/include/linux/ext3_fs_i.h index 2914f7b0715..e71dd98dbca 100644 --- a/include/linux/ext3_fs_i.h +++ b/include/linux/ext3_fs_i.h @@ -87,7 +87,7 @@ struct ext3_inode_info { #ifdef CONFIG_EXT3_FS_XATTR /* * Extended attributes can be read independently of the main file - * data. Taking i_sem even when reading would cause contention + * data. Taking i_mutex even when reading would cause contention * between readers of EAs and writers of regular file data, so * instead we synchronize on xattr_sem when reading or changing * EAs. diff --git a/include/linux/fs.h b/include/linux/fs.h index 4c82219b0fa..92ae3e2067b 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -219,6 +219,7 @@ extern int dir_notify_enable; #include <linux/prio_tree.h> #include <linux/init.h> #include <linux/sched.h> +#include <linux/mutex.h> #include <asm/atomic.h> #include <asm/semaphore.h> @@ -484,7 +485,7 @@ struct inode { unsigned long i_blocks; unsigned short i_bytes; spinlock_t i_lock; /* i_blocks, i_bytes, maybe i_size */ - struct semaphore i_sem; + struct mutex i_mutex; struct rw_semaphore i_alloc_sem; struct inode_operations *i_op; struct file_operations *i_fop; /* former ->i_op->default_file_ops */ @@ -820,7 +821,7 @@ struct super_block { unsigned long s_magic; struct dentry *s_root; struct rw_semaphore s_umount; - struct semaphore s_lock; + struct mutex s_lock; int s_count; int s_syncing; int s_need_sync_fs; @@ -892,13 +893,13 @@ static inline int has_fs_excl(void) static inline void lock_super(struct super_block * sb) { get_fs_excl(); - down(&sb->s_lock); + mutex_lock(&sb->s_lock); } static inline void unlock_super(struct super_block * sb) { put_fs_excl(); - up(&sb->s_lock); + mutex_unlock(&sb->s_lock); } /* @@ -1191,7 +1192,7 @@ int sync_inode(struct inode *inode, struct writeback_control *wbc); * directory. The name should be stored in the @name (with the * understanding that it is already pointing to a a %NAME_MAX+1 sized * buffer. get_name() should return %0 on success, a negative error code - * or error. @get_name will be called without @parent->i_sem held. + * or error. @get_name will be called without @parent->i_mutex held. * * get_parent: * @get_parent should find the parent directory for the given @child which @@ -1213,7 +1214,7 @@ int sync_inode(struct inode *inode, struct writeback_control *wbc); * nfsd_find_fh_dentry() in either the @obj or @parent parameters. * * Locking rules: - * get_parent is called with child->d_inode->i_sem down + * get_parent is called with child->d_inode->i_mutex down * get_name is not (which is possibly inconsistent) */ diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h index fb46f8d5699..6ff2d365895 100644 --- a/include/linux/i2c-id.h +++ b/include/linux/i2c-id.h @@ -103,6 +103,7 @@ #define I2C_DRIVERID_SAA711X 73 /* saa711x video encoders */ #define I2C_DRIVERID_AKITAIOEXP 74 /* IO Expander on Sharp SL-C1000 */ #define I2C_DRIVERID_INFRARED 75 /* I2C InfraRed on Video boards */ +#define I2C_DRIVERID_TVP5150 76 /* TVP5150 video decoder */ #define I2C_DRIVERID_I2CDEV 900 #define I2C_DRIVERID_ARP 902 /* SMBus ARP Client */ diff --git a/include/linux/ide.h b/include/linux/ide.h index ef8d0cbb832..9a8c05dbe4f 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -18,6 +18,7 @@ #include <linux/bio.h> #include <linux/device.h> #include <linux/pci.h> +#include <linux/completion.h> #include <asm/byteorder.h> #include <asm/system.h> #include <asm/io.h> @@ -638,7 +639,7 @@ typedef struct ide_drive_s { int crc_count; /* crc counter to reduce drive speed */ struct list_head list; struct device gendev; - struct semaphore gendev_rel_sem; /* to deal with device release() */ + struct completion gendev_rel_comp; /* to deal with device release() */ } ide_drive_t; #define to_ide_device(dev)container_of(dev, ide_drive_t, gendev) @@ -794,7 +795,7 @@ typedef struct hwif_s { unsigned sg_mapped : 1; /* sg_table and sg_nents are ready */ struct device gendev; - struct semaphore gendev_rel_sem; /* To deal with device release() */ + struct completion gendev_rel_comp; /* To deal with device release() */ void *hwif_data; /* extra hwif data */ diff --git a/include/linux/jffs2_fs_i.h b/include/linux/jffs2_fs_i.h index ef85ab56302..ad565bf9dcc 100644 --- a/include/linux/jffs2_fs_i.h +++ b/include/linux/jffs2_fs_i.h @@ -8,11 +8,11 @@ #include <asm/semaphore.h> struct jffs2_inode_info { - /* We need an internal semaphore similar to inode->i_sem. + /* We need an internal mutex similar to inode->i_mutex. Unfortunately, we can't used the existing one, because either the GC would deadlock, or we'd have to release it before letting GC proceed. Or we'd have to put ugliness - into the GC code so it didn't attempt to obtain the i_sem + into the GC code so it didn't attempt to obtain the i_mutex for the inode(s) which are already locked */ struct semaphore sem; diff --git a/include/linux/kernel.h b/include/linux/kernel.h index ca7ff8fdd09..d0e6ca3b00e 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -286,6 +286,15 @@ extern void dump_stack(void); 1; \ }) +/* + * Check at compile time that 'function' is a certain type, or is a pointer + * to that type (needs to use typedef for the function type.) + */ +#define typecheck_fn(type,function) \ +({ typeof(type) __tmp = function; \ + (void)__tmp; \ +}) + #endif /* __KERNEL__ */ #define SI_LOAD_SHIFT 16 diff --git a/include/linux/loop.h b/include/linux/loop.h index 40f63c9879d..f96506782eb 100644 --- a/include/linux/loop.h +++ b/include/linux/loop.h @@ -58,9 +58,9 @@ struct loop_device { struct bio *lo_bio; struct bio *lo_biotail; int lo_state; - struct semaphore lo_sem; + struct completion lo_done; + struct completion lo_bh_done; struct semaphore lo_ctl_mutex; - struct semaphore lo_bh_mutex; int lo_pending; request_queue_t *lo_queue; diff --git a/include/linux/mm.h b/include/linux/mm.h index df80e63903b..3f1fafc0245 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -13,6 +13,7 @@ #include <linux/rbtree.h> #include <linux/prio_tree.h> #include <linux/fs.h> +#include <linux/mutex.h> struct mempolicy; struct anon_vma; @@ -1024,6 +1025,9 @@ static inline void vm_stat_account(struct mm_struct *mm, static inline void kernel_map_pages(struct page *page, int numpages, int enable) { + if (!PageHighMem(page) && !enable) + mutex_debug_check_no_locks_freed(page_address(page), + page_address(page + numpages)); } #endif diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h index aef6042f8f0..ccd3e13de1e 100644 --- a/include/linux/mmc/mmc.h +++ b/include/linux/mmc/mmc.h @@ -27,14 +27,15 @@ struct mmc_command { #define MMC_RSP_MASK (3 << 0) #define MMC_RSP_CRC (1 << 3) /* expect valid crc */ #define MMC_RSP_BUSY (1 << 4) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 5) /* response contains opcode */ /* * These are the response types, and correspond to valid bit * patterns of the above flags. One additional valid pattern * is all zeros, which means we don't expect a response. */ -#define MMC_RSP_R1 (MMC_RSP_SHORT|MMC_RSP_CRC) -#define MMC_RSP_R1B (MMC_RSP_SHORT|MMC_RSP_CRC|MMC_RSP_BUSY) +#define MMC_RSP_R1 (MMC_RSP_SHORT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R1B (MMC_RSP_SHORT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) #define MMC_RSP_R2 (MMC_RSP_LONG|MMC_RSP_CRC) #define MMC_RSP_R3 (MMC_RSP_SHORT) #define MMC_RSP_R6 (MMC_RSP_SHORT|MMC_RSP_CRC) @@ -64,6 +65,7 @@ struct mmc_data { #define MMC_DATA_WRITE (1 << 8) #define MMC_DATA_READ (1 << 9) #define MMC_DATA_STREAM (1 << 10) +#define MMC_DATA_MULTI (1 << 11) unsigned int bytes_xfered; diff --git a/include/linux/mutex-debug.h b/include/linux/mutex-debug.h new file mode 100644 index 00000000000..0ccd8f983b5 --- /dev/null +++ b/include/linux/mutex-debug.h @@ -0,0 +1,21 @@ +#ifndef __LINUX_MUTEX_DEBUG_H +#define __LINUX_MUTEX_DEBUG_H + +/* + * Mutexes - debugging helpers: + */ + +#define __DEBUG_MUTEX_INITIALIZER(lockname) \ + , .held_list = LIST_HEAD_INIT(lockname.held_list), \ + .name = #lockname , .magic = &lockname + +#define mutex_init(sem) __mutex_init(sem, __FUNCTION__) + +extern void FASTCALL(mutex_destroy(struct mutex *lock)); + +extern void mutex_debug_show_all_locks(void); +extern void mutex_debug_show_held_locks(struct task_struct *filter); +extern void mutex_debug_check_no_locks_held(struct task_struct *task); +extern void mutex_debug_check_no_locks_freed(const void *from, const void *to); + +#endif diff --git a/include/linux/mutex.h b/include/linux/mutex.h new file mode 100644 index 00000000000..9bce0fee68d --- /dev/null +++ b/include/linux/mutex.h @@ -0,0 +1,119 @@ +/* + * Mutexes: blocking mutual exclusion locks + * + * started by Ingo Molnar: + * + * Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar <mingo@redhat.com> + * + * This file contains the main data structure and API definitions. + */ +#ifndef __LINUX_MUTEX_H +#define __LINUX_MUTEX_H + +#include <linux/list.h> +#include <linux/spinlock_types.h> + +#include <asm/atomic.h> + +/* + * Simple, straightforward mutexes with strict semantics: + * + * - only one task can hold the mutex at a time + * - only the owner can unlock the mutex + * - multiple unlocks are not permitted + * - recursive locking is not permitted + * - a mutex object must be initialized via the API + * - a mutex object must not be initialized via memset or copying + * - task may not exit with mutex held + * - memory areas where held locks reside must not be freed + * - held mutexes must not be reinitialized + * - mutexes may not be used in irq contexts + * + * These semantics are fully enforced when DEBUG_MUTEXES is + * enabled. Furthermore, besides enforcing the above rules, the mutex + * debugging code also implements a number of additional features + * that make lock debugging easier and faster: + * + * - uses symbolic names of mutexes, whenever they are printed in debug output + * - point-of-acquire tracking, symbolic lookup of function names + * - list of all locks held in the system, printout of them + * - owner tracking + * - detects self-recursing locks and prints out all relevant info + * - detects multi-task circular deadlocks and prints out all affected + * locks and tasks (and only those tasks) + */ +struct mutex { + /* 1: unlocked, 0: locked, negative: locked, possible waiters */ + atomic_t count; + spinlock_t wait_lock; + struct list_head wait_list; +#ifdef CONFIG_DEBUG_MUTEXES + struct thread_info *owner; + struct list_head held_list; + unsigned long acquire_ip; + const char *name; + void *magic; +#endif +}; + +/* + * This is the control structure for tasks blocked on mutex, + * which resides on the blocked task's kernel stack: + */ +struct mutex_waiter { + struct list_head list; + struct task_struct *task; +#ifdef CONFIG_DEBUG_MUTEXES + struct mutex *lock; + void *magic; +#endif +}; + +#ifdef CONFIG_DEBUG_MUTEXES +# include <linux/mutex-debug.h> +#else +# define __DEBUG_MUTEX_INITIALIZER(lockname) +# define mutex_init(mutex) __mutex_init(mutex, NULL) +# define mutex_destroy(mutex) do { } while (0) +# define mutex_debug_show_all_locks() do { } while (0) +# define mutex_debug_show_held_locks(p) do { } while (0) +# define mutex_debug_check_no_locks_held(task) do { } while (0) +# define mutex_debug_check_no_locks_freed(from, to) do { } while (0) +#endif + +#define __MUTEX_INITIALIZER(lockname) \ + { .count = ATOMIC_INIT(1) \ + , .wait_lock = SPIN_LOCK_UNLOCKED \ + , .wait_list = LIST_HEAD_INIT(lockname.wait_list) \ + __DEBUG_MUTEX_INITIALIZER(lockname) } + +#define DEFINE_MUTEX(mutexname) \ + struct mutex mutexname = __MUTEX_INITIALIZER(mutexname) + +extern void fastcall __mutex_init(struct mutex *lock, const char *name); + +/*** + * mutex_is_locked - is the mutex locked + * @lock: the mutex to be queried + * + * Returns 1 if the mutex is locked, 0 if unlocked. + */ +static inline int fastcall mutex_is_locked(struct mutex *lock) +{ + return atomic_read(&lock->count) != 1; +} + +/* + * See kernel/mutex.c for detailed documentation of these APIs. + * Also see Documentation/mutex-design.txt. + */ +extern void fastcall mutex_lock(struct mutex *lock); +extern int fastcall mutex_lock_interruptible(struct mutex *lock); +/* + * NOTE: mutex_trylock() follows the spin_trylock() convention, + * not the down_trylock() convention! + */ +extern int fastcall mutex_trylock(struct mutex *lock); +extern void fastcall mutex_unlock(struct mutex *lock); + +#endif diff --git a/include/linux/nfsd/nfsfh.h b/include/linux/nfsd/nfsfh.h index bb842ea4103..0798b7781a6 100644 --- a/include/linux/nfsd/nfsfh.h +++ b/include/linux/nfsd/nfsfh.h @@ -294,7 +294,7 @@ fill_post_wcc(struct svc_fh *fhp) /* * Lock a file handle/inode * NOTE: both fh_lock and fh_unlock are done "by hand" in - * vfs.c:nfsd_rename as it needs to grab 2 i_sem's at once + * vfs.c:nfsd_rename as it needs to grab 2 i_mutex's at once * so, any changes here should be reflected there. */ static inline void @@ -317,7 +317,7 @@ fh_lock(struct svc_fh *fhp) } inode = dentry->d_inode; - down(&inode->i_sem); + mutex_lock(&inode->i_mutex); fill_pre_wcc(fhp); fhp->fh_locked = 1; } @@ -333,7 +333,7 @@ fh_unlock(struct svc_fh *fhp) if (fhp->fh_locked) { fill_post_wcc(fhp); - up(&fhp->fh_dentry->d_inode->i_sem); + mutex_unlock(&fhp->fh_dentry->d_inode->i_mutex); fhp->fh_locked = 0; } } diff --git a/include/linux/pipe_fs_i.h b/include/linux/pipe_fs_i.h index 1767073df26..b12e59c7575 100644 --- a/include/linux/pipe_fs_i.h +++ b/include/linux/pipe_fs_i.h @@ -37,7 +37,7 @@ struct pipe_inode_info { memory allocation, whereas PIPE_BUF makes atomicity guarantees. */ #define PIPE_SIZE PAGE_SIZE -#define PIPE_SEM(inode) (&(inode).i_sem) +#define PIPE_MUTEX(inode) (&(inode).i_mutex) #define PIPE_WAIT(inode) (&(inode).i_pipe->wait) #define PIPE_READERS(inode) ((inode).i_pipe->readers) #define PIPE_WRITERS(inode) ((inode).i_pipe->writers) diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h index 001ab82df05..e276c5ba2bb 100644 --- a/include/linux/reiserfs_fs.h +++ b/include/linux/reiserfs_fs.h @@ -1857,7 +1857,7 @@ void padd_item(char *item, int total_length, int length); #define GET_BLOCK_CREATE 1 /* add anything you need to find block */ #define GET_BLOCK_NO_HOLE 2 /* return -ENOENT for file holes */ #define GET_BLOCK_READ_DIRECT 4 /* read the tail if indirect item not found */ -#define GET_BLOCK_NO_ISEM 8 /* i_sem is not held, don't preallocate */ +#define GET_BLOCK_NO_IMUX 8 /* i_mutex is not held, don't preallocate */ #define GET_BLOCK_NO_DANGLE 16 /* don't leave any transactions running */ int restart_transaction(struct reiserfs_transaction_handle *th, diff --git a/include/linux/sched.h b/include/linux/sched.h index 78eb92ae4d9..85b53f87c70 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -817,6 +817,11 @@ struct task_struct { /* Protection of proc_dentry: nesting proc_lock, dcache_lock, write_lock_irq(&tasklist_lock); */ spinlock_t proc_lock; +#ifdef CONFIG_DEBUG_MUTEXES + /* mutex deadlock detection */ + struct mutex_waiter *blocked_on; +#endif + /* journalling filesystem info */ void *journal_info; diff --git a/include/linux/video_decoder.h b/include/linux/video_decoder.h index 0e9e48b83e3..121e26da2c1 100644 --- a/include/linux/video_decoder.h +++ b/include/linux/video_decoder.h @@ -1,6 +1,8 @@ #ifndef _LINUX_VIDEO_DECODER_H #define _LINUX_VIDEO_DECODER_H +#define HAVE_VIDEO_DECODER 1 + struct video_decoder_capability { /* this name is too long */ __u32 flags; #define VIDEO_DECODER_PAL 1 /* can decode PAL signal */ diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h index 1cded681eb6..ce40675324b 100644 --- a/include/linux/videodev2.h +++ b/include/linux/videodev2.h @@ -642,6 +642,12 @@ typedef __u64 v4l2_std_id; #define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000) #define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000) +/* some merged standards */ +#define V4L2_STD_MN (V4L2_STD_PAL_M|V4L2_STD_PAL_N|V4L2_STD_PAL_Nc|V4L2_STD_NTSC) +#define V4L2_STD_B (V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_SECAM_B) +#define V4L2_STD_GH (V4L2_STD_PAL_G|V4L2_STD_PAL_H|V4L2_STD_SECAM_G|V4L2_STD_SECAM_H) +#define V4L2_STD_DK (V4L2_STD_PAL_DK|V4L2_STD_SECAM_DK) + /* some common needed stuff */ #define V4L2_STD_PAL_BG (V4L2_STD_PAL_B |\ V4L2_STD_PAL_B1 |\ @@ -662,7 +668,8 @@ typedef __u64 v4l2_std_id; V4L2_STD_SECAM_G |\ V4L2_STD_SECAM_H |\ V4L2_STD_SECAM_DK |\ - V4L2_STD_SECAM_L) + V4L2_STD_SECAM_L |\ + V4L2_STD_SECAM_LC) #define V4L2_STD_525_60 (V4L2_STD_PAL_M |\ V4L2_STD_PAL_60 |\ @@ -888,7 +895,6 @@ struct v4l2_audio /* Flags for the 'mode' field */ #define V4L2_AUDMODE_AVL 0x00001 -#define V4L2_AUDMODE_32BITS 0x00002 struct v4l2_audioout { @@ -1110,7 +1116,6 @@ int v4l2_prio_check(struct v4l2_prio_state *global, enum v4l2_priority *local); /* names for fancy debug output */ extern char *v4l2_field_names[]; extern char *v4l2_type_names[]; -extern char *v4l2_ioctl_names[]; /* Compatibility layer interface -- v4l1-compat module */ typedef int (*v4l2_kioctl)(struct inode *inode, struct file *file, @@ -1118,6 +1123,11 @@ typedef int (*v4l2_kioctl)(struct inode *inode, struct file *file, int v4l_compat_translate_ioctl(struct inode *inode, struct file *file, int cmd, void *arg, v4l2_kioctl driver_ioctl); +/* 32 Bits compatibility layer for 64 bits processors */ +extern long v4l_compat_ioctl32(struct file *file, unsigned int cmd, + unsigned long arg); + + #endif /* __KERNEL__ */ #endif /* __LINUX_VIDEODEV2_H */ diff --git a/include/media/audiochip.h b/include/media/audiochip.h index b7d4b093040..295d256ee81 100644 --- a/include/media/audiochip.h +++ b/include/media/audiochip.h @@ -23,11 +23,6 @@ enum audiochip { /* ---------------------------------------------------------------------- */ -/* v4l device was opened in Radio mode */ -#define AUDC_SET_RADIO _IO('m',2) -/* select from TV,radio,extern,MUTE */ -#define AUDC_SET_INPUT _IOW('m',17,int) - /* audio inputs */ #define AUDIO_TUNER 0x00 #define AUDIO_RADIO 0x01 @@ -40,15 +35,4 @@ enum audiochip { #define AUDIO_MUTE 0x80 #define AUDIO_UNMUTE 0x81 -/* all the stuff below is obsolete and just here for reference. I'll - * remove it once the driver is tested and works fine. - * - * Instead creating alot of tiny API's for all kinds of different - * chips, we'll just pass throuth the v4l ioctl structs (v4l2 not - * yet...). It is a bit less flexible, but most/all used i2c chips - * make sense in v4l context only. So I think that's acceptable... - */ - -/* misc stuff to pass around config info to i2c chips */ -#define AUDC_CONFIG_PINNACLE _IOW('m',32,int) #endif /* AUDIOCHIP_H */ diff --git a/include/media/saa7146_vv.h b/include/media/saa7146_vv.h index 16af9299315..e5e749e984e 100644 --- a/include/media/saa7146_vv.h +++ b/include/media/saa7146_vv.h @@ -178,6 +178,8 @@ struct saa7146_ext_vv struct saa7146_extension_ioctls *ioctls; int (*ioctl)(struct saa7146_fh*, unsigned int cmd, void *arg); + + struct file_operations vbi_fops; }; struct saa7146_use_ops { diff --git a/include/media/tuner.h b/include/media/tuner.h index b37cde60669..7674b121ce8 100644 --- a/include/media/tuner.h +++ b/include/media/tuner.h @@ -82,9 +82,9 @@ #define TUNER_PHILIPS_FM1236_MK3 43 #define TUNER_PHILIPS_4IN1 44 /* ATI TV Wonder Pro - Conexant */ -/* Microtune mergeged with Temic 12/31/1999 partially financed by Alps - these may be similar to Temic */ +/* Microtune merged with Temic 12/31/1999 partially financed by Alps - these may be similar to Temic */ #define TUNER_MICROTUNE_4049FM5 45 -#define TUNER_MICROTUNE_4042_FI5 46 +#define TUNER_PANASONIC_VP27 46 #define TUNER_LG_NTSC_TAPE 47 #define TUNER_TNF_8831BGFF 48 @@ -102,7 +102,7 @@ #define TUNER_YMEC_TVF_8531MF 58 #define TUNER_YMEC_TVF_5533MF 59 /* Pixelview Pro Ultra NTSC */ -#define TUNER_THOMSON_DTT7611 60 /* DViCO FusionHDTV 3 Gold-T */ +#define TUNER_THOMSON_DTT761X 60 /* DTT 7611 7611A 7612 7613 7613A 7614 7615 7615A */ #define TUNER_TENA_9533_DI 61 #define TUNER_TEA5767 62 /* Only FM Radio Tuner */ #define TUNER_PHILIPS_FMD1216ME_MK3 63 @@ -115,47 +115,26 @@ #define TUNER_PHILIPS_TUV1236D 68 /* ATI HDTV Wonder */ #define TUNER_TNF_5335MF 69 /* Sabrent Bt848 */ -#define NOTUNER 0 -#define PAL 1 /* PAL_BG */ -#define PAL_I 2 -#define NTSC 3 -#define SECAM 4 -#define ATSC 5 -#define RADIO 6 - -#define NoTuner 0 -#define Philips 1 -#define TEMIC 2 -#define Sony 3 -#define Alps 4 -#define LGINNOTEK 5 -#define SHARP 6 -#define Samsung 7 -#define Microtune 8 -#define HITACHI 9 -#define Panasonic 10 -#define TCL 11 -#define THOMSON 12 - -#define TUNER_SET_TYPE_ADDR _IOW('T',3,int) -#define TUNER_SET_STANDBY _IOW('T',4,int) -#define TDA9887_SET_CONFIG _IOW('t',5,int) - /* tv card specific */ -# define TDA9887_PRESENT (1<<0) -# define TDA9887_PORT1_INACTIVE (1<<1) -# define TDA9887_PORT2_INACTIVE (1<<2) -# define TDA9887_QSS (1<<3) -# define TDA9887_INTERCARRIER (1<<4) -# define TDA9887_PORT1_ACTIVE (1<<5) -# define TDA9887_PORT2_ACTIVE (1<<6) -# define TDA9887_INTERCARRIER_NTSC (1<<7) +#define TDA9887_PRESENT (1<<0) +#define TDA9887_PORT1_INACTIVE (1<<1) +#define TDA9887_PORT2_INACTIVE (1<<2) +#define TDA9887_QSS (1<<3) +#define TDA9887_INTERCARRIER (1<<4) +#define TDA9887_PORT1_ACTIVE (1<<5) +#define TDA9887_PORT2_ACTIVE (1<<6) +#define TDA9887_INTERCARRIER_NTSC (1<<7) +/* Tuner takeover point adjustment, in dB, -16 <= top <= 15 */ +#define TDA9887_TOP_MASK (0x3f << 8) +#define TDA9887_TOP_SET (1 << 13) +#define TDA9887_TOP(top) (TDA9887_TOP_SET | (((16 + (top)) & 0x1f) << 8)) + /* config options */ -# define TDA9887_DEEMPHASIS_MASK (3<<16) -# define TDA9887_DEEMPHASIS_NONE (1<<16) -# define TDA9887_DEEMPHASIS_50 (2<<16) -# define TDA9887_DEEMPHASIS_75 (3<<16) -# define TDA9887_AUTOMUTE (1<<18) +#define TDA9887_DEEMPHASIS_MASK (3<<16) +#define TDA9887_DEEMPHASIS_NONE (1<<16) +#define TDA9887_DEEMPHASIS_50 (2<<16) +#define TDA9887_DEEMPHASIS_75 (3<<16) +#define TDA9887_AUTOMUTE (1<<18) #ifdef __KERNEL__ @@ -167,10 +146,26 @@ enum tuner_mode { T_STANDBY = 1 << 31 }; +/* Older boards only had a single tuner device. Nowadays multiple tuner + devices may be present on a single board. Using TUNER_SET_TYPE_ADDR + to pass the tuner_setup structure it is possible to setup each tuner + device in turn. + + Since multiple devices may be present it is no longer sufficient to + send a command to a single i2c device. Instead you should broadcast + the command to all i2c devices. + + By setting the mode_mask correctly you can select which commands are + accepted by a specific tuner device. For example, set mode_mask to + T_RADIO if the device is a radio-only tuner. That specific tuner will + only accept commands when the tuner is in radio mode and ignore them + when the tuner is set to TV mode. + */ + struct tuner_setup { - unsigned short addr; - unsigned int type; - unsigned int mode_mask; + unsigned short addr; /* I2C address */ + unsigned int type; /* Tuner type */ + unsigned int mode_mask; /* Allowed tuner modes */ }; struct tuner { @@ -207,7 +202,6 @@ struct tuner { void (*standby)(struct i2c_client *c); }; -extern unsigned int tuner_debug; extern unsigned const int tuner_count; extern int microtune_init(struct i2c_client *c); @@ -219,15 +213,15 @@ extern int tea5767_autodetection(struct i2c_client *c); #define tuner_warn(fmt, arg...) do {\ printk(KERN_WARNING "%s %d-%04x: " fmt, t->i2c.driver->driver.name, \ - t->i2c.adapter->nr, t->i2c.addr , ##arg); } while (0) + i2c_adapter_id(t->i2c.adapter), t->i2c.addr , ##arg); } while (0) #define tuner_info(fmt, arg...) do {\ printk(KERN_INFO "%s %d-%04x: " fmt, t->i2c.driver->driver.name, \ - t->i2c.adapter->nr, t->i2c.addr , ##arg); } while (0) + i2c_adapter_id(t->i2c.adapter), t->i2c.addr , ##arg); } while (0) #define tuner_dbg(fmt, arg...) do {\ - if (tuner_debug) \ - printk(KERN_DEBUG "%s %d-%04x: " fmt, \ - t->i2c.driver->driver.name, \ - t->i2c.adapter->nr, t->i2c.addr , ##arg); } while (0) + extern int debug; \ + if (debug) \ + printk(KERN_DEBUG "%s %d-%04x: " fmt, t->i2c.driver->driver.name, \ + i2c_adapter_id(t->i2c.adapter), t->i2c.addr , ##arg); } while (0) #endif /* __KERNEL__ */ diff --git a/include/media/v4l2-common.h b/include/media/v4l2-common.h index d3fd48157eb..3cc3132f391 100644 --- a/include/media/v4l2-common.h +++ b/include/media/v4l2-common.h @@ -26,12 +26,57 @@ #ifndef V4L2_COMMON_H_ #define V4L2_COMMON_H_ -/* VIDIOC_INT_AUDIO_CLOCK_FREQ */ -enum v4l2_audio_clock_freq { - V4L2_AUDCLK_32_KHZ = 32000, - V4L2_AUDCLK_441_KHZ = 44100, - V4L2_AUDCLK_48_KHZ = 48000, -}; +/* v4l debugging and diagnostics */ + +/* Common printk constucts for v4l-i2c drivers. These macros create a unique + prefix consisting of the driver name, the adapter number and the i2c + address. */ +#define v4l_printk(level, name, adapter, addr, fmt, arg...) \ + printk(level "%s %d-%04x: " fmt, name, i2c_adapter_id(adapter), addr , ## arg) + +#define v4l_client_printk(level, client, fmt, arg...) \ + v4l_printk(level, (client)->driver->driver.name, (client)->adapter, \ + (client)->addr, fmt , ## arg) + +#define v4l_err(client, fmt, arg...) \ + v4l_client_printk(KERN_ERR, client, fmt , ## arg) + +#define v4l_warn(client, fmt, arg...) \ + v4l_client_printk(KERN_WARNING, client, fmt , ## arg) + +#define v4l_info(client, fmt, arg...) \ + v4l_client_printk(KERN_INFO, client, fmt , ## arg) + +/* These three macros assume that the debug level is set with a module + parameter called 'debug'. */ +#define v4l_dbg(level, client, fmt, arg...) \ + do { \ + extern int debug; \ + if (debug >= (level)) \ + v4l_client_printk(KERN_DEBUG, client, fmt , ## arg); \ + } while (0) + +/* Prints the ioctl in a human-readable format */ +extern void v4l_printk_ioctl(unsigned int cmd); + +/* Use this macro for non-I2C drivers. Pass the driver name as the first arg. */ +#define v4l_print_ioctl(name, cmd) \ + do { \ + printk(KERN_DEBUG "%s: ", name); \ + v4l_printk_ioctl(cmd); \ + } while (0) + +/* Use this macro in I2C drivers where 'client' is the struct i2c_client + pointer */ +#define v4l_i2c_print_ioctl(client, cmd) \ + do { \ + v4l_client_printk(KERN_DEBUG, client, ""); \ + v4l_printk_ioctl(cmd); \ + } while (0) + +/* ------------------------------------------------------------------------- */ + +/* Internal ioctls */ /* VIDIOC_INT_G_REGISTER and VIDIOC_INT_S_REGISTER */ struct v4l2_register { @@ -70,6 +115,20 @@ enum v4l2_chip_ident { V4L2_IDENT_CX25843 = 243, }; +/* audio ioctls */ +/* v4l device was opened in Radio mode */ +#define AUDC_SET_RADIO _IO('d',88) +/* select from TV,radio,extern,MUTE */ +#define AUDC_SET_INPUT _IOW('d',89,int) + +/* tuner ioctls */ +/* Sets tuner type and its I2C addr */ +#define TUNER_SET_TYPE_ADDR _IOW('d',90,int) +/* Puts tuner on powersaving state, disabling it, except for i2c */ +#define TUNER_SET_STANDBY _IOW('d',91,int) +/* Sets tda9887 specific stuff, like port1, port2 and qss */ +#define TDA9887_SET_CONFIG _IOW('d',92,int) + /* only implemented if CONFIG_VIDEO_ADV_DEBUG is defined */ #define VIDIOC_INT_S_REGISTER _IOR ('d', 100, struct v4l2_register) #define VIDIOC_INT_G_REGISTER _IOWR('d', 101, struct v4l2_register) @@ -77,10 +136,12 @@ enum v4l2_chip_ident { /* Reset the I2C chip */ #define VIDIOC_INT_RESET _IO ('d', 102) -/* Set the frequency of the audio clock output. +/* Set the frequency (in Hz) of the audio clock output. Used to slave an audio processor to the video decoder, ensuring that audio - and video remain synchronized. */ -#define VIDIOC_INT_AUDIO_CLOCK_FREQ _IOR ('d', 103, enum v4l2_audio_clock_freq) + and video remain synchronized. + Usual values for the frequency are 48000, 44100 or 32000 Hz. + If the frequency is not supported, then -EINVAL is returned. */ +#define VIDIOC_INT_AUDIO_CLOCK_FREQ _IOW ('d', 103, u32) /* Video decoders that support sliced VBI need to implement this ioctl. Field p of the v4l2_sliced_vbi_line struct is set to the start of the VBI @@ -107,4 +168,10 @@ enum v4l2_chip_ident { be made. */ #define VIDIOC_INT_G_CHIP_IDENT _IOR ('d', 107, enum v4l2_chip_ident *) +/* Sets I2S speed in bps. This is used to provide a standard way to select I2S + clock used by driving digital audio streams at some board designs. + Usual values for the frequency are 1024000 and 2048000. + If the frequency is not supported, then -EINVAL is returned. */ +#define VIDIOC_INT_I2S_CLOCK_FREQ _IOW ('d', 108, u32) + #endif /* V4L2_COMMON_H_ */ diff --git a/include/net/act_api.h b/include/net/act_api.h index b55eb7c7f03..11e9eaf79f5 100644 --- a/include/net/act_api.h +++ b/include/net/act_api.h @@ -63,7 +63,7 @@ struct tc_action_ops __u32 type; /* TBD to match kind */ __u32 capab; /* capabilities includes 4 bit version */ struct module *owner; - int (*act)(struct sk_buff **, struct tc_action *, struct tcf_result *); + int (*act)(struct sk_buff *, struct tc_action *, struct tcf_result *); int (*get_stats)(struct sk_buff *, struct tc_action *); int (*dump)(struct sk_buff *, struct tc_action *,int , int); int (*cleanup)(struct tc_action *, int bind); diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h index 6492e7363d8..b94d1ad92c4 100644 --- a/include/net/pkt_sched.h +++ b/include/net/pkt_sched.h @@ -1,6 +1,7 @@ #ifndef __NET_PKT_SCHED_H #define __NET_PKT_SCHED_H +#include <linux/jiffies.h> #include <net/sch_generic.h> struct qdisc_walker @@ -59,8 +60,8 @@ typedef struct timeval psched_time_t; typedef long psched_tdiff_t; #define PSCHED_GET_TIME(stamp) do_gettimeofday(&(stamp)) -#define PSCHED_US2JIFFIE(usecs) (((usecs)+(1000000/HZ-1))/(1000000/HZ)) -#define PSCHED_JIFFIE2US(delay) ((delay)*(1000000/HZ)) +#define PSCHED_US2JIFFIE(usecs) usecs_to_jiffies(usecs) +#define PSCHED_JIFFIE2US(delay) jiffies_to_usecs(delay) #else /* !CONFIG_NET_SCH_CLK_GETTIMEOFDAY */ @@ -123,9 +124,9 @@ do { \ default: \ __delta = 0; \ case 2: \ - __delta += 1000000; \ + __delta += USEC_PER_SEC; \ case 1: \ - __delta += 1000000; \ + __delta += USEC_PER_SEC; \ } \ } \ __delta; \ @@ -136,9 +137,9 @@ psched_tod_diff(int delta_sec, int bound) { int delta; - if (bound <= 1000000 || delta_sec > (0x7FFFFFFF/1000000)-1) + if (bound <= USEC_PER_SEC || delta_sec > (0x7FFFFFFF/USEC_PER_SEC)-1) return bound; - delta = delta_sec * 1000000; + delta = delta_sec * USEC_PER_SEC; if (delta > bound || delta < 0) delta = bound; return delta; @@ -152,9 +153,9 @@ psched_tod_diff(int delta_sec, int bound) default: \ __delta = psched_tod_diff(__delta_sec, bound); break; \ case 2: \ - __delta += 1000000; \ + __delta += USEC_PER_SEC; \ case 1: \ - __delta += 1000000; \ + __delta += USEC_PER_SEC; \ case 0: \ if (__delta > bound || __delta < 0) \ __delta = bound; \ @@ -170,15 +171,15 @@ psched_tod_diff(int delta_sec, int bound) ({ \ int __delta = (tv).tv_usec + (delta); \ (tv_res).tv_sec = (tv).tv_sec; \ - if (__delta > 1000000) { (tv_res).tv_sec++; __delta -= 1000000; } \ + if (__delta > USEC_PER_SEC) { (tv_res).tv_sec++; __delta -= USEC_PER_SEC; } \ (tv_res).tv_usec = __delta; \ }) #define PSCHED_TADD(tv, delta) \ ({ \ (tv).tv_usec += (delta); \ - if ((tv).tv_usec > 1000000) { (tv).tv_sec++; \ - (tv).tv_usec -= 1000000; } \ + if ((tv).tv_usec > USEC_PER_SEC) { (tv).tv_sec++; \ + (tv).tv_usec -= USEC_PER_SEC; } \ }) /* Set/check that time is in the "past perfect"; |