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2006-03-20[SPARC64]: Use different cache sizing defaults on SUN4V.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Make lack of interrupt-map-* a fatal error on SUN4V.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix sun4v_intr_setenabled() return value check in enable_irq().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Explicitly init *nregs to 0 in find_device_prom_node().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Restrict PCI bus scanning on SUN4V.David S. Miller
On the PBM's first bus number, only allow device 0, function 0, to be poked at with PCI config space accesses. For some reason, this single device responds to all device numbers. Also, reduce the verbiage of the debugging log printk's for PCI cfg space accesses in the SUN4V PCI controller driver, so that it doesn't overwhelm the slow SUN4V hypervisor console. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix C-function name called by sun4v_mna trap code.David S. Miller
The trap code was calling itself :-) Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Don't printk() any messaages in sun4v_build_irq().David S. Miller
It just clutters up the log. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: INO is never fully specified already on SUN4V.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Kill sun4v_register_fault_status() on SMP.David S. Miller
That now gets done as a side effect of taking over the trap table from OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix gcc-3.3.x warnings.David S. Miller
It doesn't like const variables being passed into "i" constraing asm operations. It's a bug, but there is nothing we can really do but work around it. Based upon a report from Andrew Morton. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: arch/sparc64/kernel/trampoline.S needs asm/cpudata.hDavid S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Make error codes available from sun4v_intr_get*().David S. Miller
And check for errors at call sites. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Pass correct ino to sun4v_intr_*().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Use TRAP_LOAD_IRQ_WORK() in sun4v device mondo handler.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix IOMMU mapping on sun4v.David S. Miller
We should dynamically allocate the per-cpu pglist not use an in-kernel-image datum, since __pa() does not work on such addresses. Also, consistently use "u32" for devhandle. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Trim down sun4v IRQ translation kernel log message.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64] sunhv: Bug fixes.David S. Miller
Add udelay to polling console write loop, and increment the loop limit. Name the device "ttyHV" and pass that to add_preferred_console() when we're using hypervisor console. Kill sunhv_console_setup(), it's empty. Handle the case where we don't want to use hypervisor console. (ie. we have a head attached to a sun4v machine) Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix comment typo in asm/hypervisor.hDavid S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64] sunhv: Use virtual-devices layer to get interrupt.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Probe virtual-devices root node on sun4v.David S. Miller
This is where we learn how to get the interrupts for things like the hypervisor console device. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Kill spurious semicolon in sun4v_pci_init().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Prevent registering wrong serial console.David S. Miller
If the console is not for a particular Sun serial controller, set the drv->cons to NULL. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Program IRQ registers correctly on sun4v.David S. Miller
Need to use hypervisor calls instead of direct register accesses. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Generic sun4v_build_irq().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: More SUN4V PCI work.David S. Miller
Get bus range from child of PCI controller root nexus. This is actually a hack, but the PCI-E bridge sitting at the top of the PCI tree responds to PCI config cycles for every device number, so best to just ignore it for now. Preliminary PCI irq routing, needs lots of work. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Log faulting vaddr when bogus kernel PC detected.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Implement rest of generic interrupt hypervisor calls.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Move devino_to_sysino out of pci_sun4v_asm.SDavid S. Miller
It is not PCI specific, it is for all system interrupts. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Range check bus number in SUN4V PCI controller driver.David S. Miller
It has to be somewhere in the range from pbm->pci_first_busno to pbm->pci_last_busno, inclusive. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Missing 'return' statement in sun4v_pci_init().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Implement basic pci_sun4v_scan_bus().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: PCI-SUN4V fixes.David S. Miller
Clear top 8-bits of physical addresses in "ranges" property. This gives the actual physical address. Detect PBM-A vs. PBM-B by checking bit 0x40 of the devhandle. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Use inline patching for critical PTE operations.David S. Miller
This handles the SUN4U vs SUN4V PTE layout differences with near zero performance cost. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Move PTE field definitions back into asm/pgtable.hDavid S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Don't expect cfg space in PCI PBM ranges on SUN4V.David S. Miller
PCI cfg space is accessed transparently through the Hypervisor and not through direct cpu PIO operations. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix branch signedness bug in all code patching.David S. Miller
The bug that hit SUN4V TLB patching exists elsewhere. Make sure we cure all such cases. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Recognize "virtual-console" as input and output console device.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Do not try to synchronize %stick registers on SUN4V.David S. Miller
Writes by privileged code are not allowed. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Do not try to write to %tick or %stick on SUN4V.David S. Miller
Writes by privileged code are disallowed. The hypervisor manages the non-privileged bit. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix mondo queue allocations.David S. Miller
We have to use bootmem during init_IRQ and page alloc for sibling cpu calls. Also, fix incorrect hypervisor call return value checks in the hypervisor SMP cpu mondo send code. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Deal with PTE layout differences in SUN4V.David S. Miller
Yes, you heard it right, they changed the PTE layout for SUN4V. Ho hum... This is the simple and inefficient way to support this. It'll get optimized, don't worry. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Register kernel TSB with hypervisor.David S. Miller
We do this right after we take over the trap table from OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix some SUN4V TLB miss bugs.David S. Miller
Code patching did not sign extend negative branch offsets correctly. Kernel TLB miss path needs patching and %g4 register preservation in order to handle SUN4V correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix typo in sun4v_patch().David S. Miller
Second instruction offset is '4' not '3'. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix sun4v early bootup.David S. Miller
prom_sun4v_name should be "sun4v" not "SUNW,sun4v" Also, this is too early to make use of the .sun4v_Xinsn_patch code patching, so just check things manually. This gets us at least to prom_init() on Niagara. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix some Niagara memcpy() bugs.David S. Miller
We need to restore the %asi register properly. For the kernel this means get_fs(), for user this means ASI_PNF. Also, NGcopy_to_user.S was including U3memcpy.S instead of NGmemcpy.S, oops :-) Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Handle hypervisor case correctly in copy_tsb().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Add SUN4V Hypervisor Console driver.David S. Miller
Since it can do things like BREAK and HUP, we implement this as a serial uart driver. This still needs interrupt probing code, as I haven't figured out how interrupts will work or be probed for on SUN4V yet. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fetch bootup time of day from Hypervisor.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Simplify sun4v TLB handling using macros.David S. Miller
There was also a bug in sun4v_itlb_miss, it loaded the MMU Fault Status base into %g3 instead of %g2. This pointed out a fast path for TSB miss processing, since we have %g2 with the MMU Fault Status base, we can use that to quickly load up the PGD phys address. Signed-off-by: David S. Miller <davem@davemloft.net>
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