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2008-10-10r8169: change default behavior for mildly identified 8168c chipsetsFrancois Romieu
The addition of a new device has so far implied a specialization of these masks. While they identify 8168c devices, they can be expected to be further refined as they have been by Realtek so far. The change should bring the driver closer to the version 8.006.00 of Realtek's 8168 driver. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
2008-10-10r8169: add a new 8168cp flavorFrancois Romieu
Taken from Realtek's 8.006.00 r8168 driver. I have left some bits related to jumbo frame aside for now. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
2008-10-10r8169: add a new 8168c flavor (bis)Francois Romieu
Taken from Realtek's 8.006.00 r8168 driver. I have left some bits related to jumbo frame aside for now. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
2008-10-10r8169: add a new 8168c flavorFrancois Romieu
Taken from Realtek's 8.006.00 r8168 driver. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
2008-10-10r8169: sync existing 8168 device hardware start sequences with vendor driverFrancois Romieu
This part of the driver should be reasonably in line with Realtek's 8.006.00 driver. I have left some bits related to jumbo frame and optional features aside for now. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
2008-10-10r8169: 8168b Tx performance tweakFrancois Romieu
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
2008-10-10r8169: make room for more specific 8168 hardware start procedureFrancois Romieu
Broadly speaking the 8168c* share some common code which will be factored in __rtl_hw_start_8168cp. The 8168b* share some code too but it will be a bit different. Any change of behavior should be confined to the currently unidentified 8168 chipsets. They will not be applied the Tx performance tweak and will emit a warning instead. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
2008-10-10r8169: shuffle some registers handling around (8168 operation only)Francois Romieu
I can not argue strongly for (or against) a specific ordering on a purely technical ground but the patch avoids to swallow Realtek's changes in one big, hard-to-read gulp. Let aside the way the RxConfig register is written (see rtl_set_rx_tx_config_registers / RxConfig / rtl_set_rx_mode), this change brings the registers write ordering closer with Realtek's driver one (version 8.006.00) for the 8168 chipsets. More 8168 specific code which touches the Configx registers will be added in the section covered by Cfg9346_UnLock / Cfg9346_Lock. This code should not be the cause of regression for 810x and 8110 users. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
2008-10-10r8169: new phy init parameters for the 8168bFrancois Romieu
The new parameters are synced with Realtek's driver version 8.006.00. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
2008-10-10r8169: update phy init parametersFrancois Romieu
The modified parameters are synced with Realtek's driver version 8.006.00. The change should only be noticeable with some 8168c. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
2008-10-10r8169: wake up the PHY of the 8168Francois Romieu
This is typically needed when some other OS puts the PHY to sleep due to the disabling of WOL options in the BIOS of the system. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Tested-by: Chiaki Ishikawa <chiaki.ishikawa@ubin.jp> Cc: Edward Hsu <edward_hsu@realtek.com.tw> Cc: RyanKao <ryankao@realtek.com.tw>
2008-10-09r8169: fix early spinlock useFrancois Romieu
rtl8169_init_one -> rtl_init_mac_address -> rtl_rar_set -> spin_lock_irq(&tp->lock); [...] -> spin_lock_init(&tp->lock); Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09smsc95xx: fix usb usage on big endian platformsSteve Glendinning
Fix warnings caught by David Miller on sparc64 Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09sctp: update SNMP statiscts when T5 timer expired.Vlad Yasevich
The T5 timer is the timer for the over-all shutdown procedure. If this timer expires, then shutdown procedure has not completed and we ABORT the association. We should update SCTP_MIB_ABORTED and SCTP_MIB_CURRESTAB when aborting. Signed-off-by: Vlad Yasevich <vladislav.yasevich@hp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09sctp: Fix SNMP number of SCTP_MIB_ABORTED during violation handling.Vlad Yasevich
If ABORT chunks require authentication and a protocol violation is triggered, we do not tear down the association. Subsequently, we should not increment SCTP_MIB_ABORTED. Signed-off-by: Vlad Yasevich <vladislav.yasevich@hp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09sctp: Fix the SNMP number of SCTP_MIB_CURRESTABWei Yongjun
RFC3873 defined SCTP_MIB_CURRESTAB: sctpCurrEstab OBJECT-TYPE SYNTAX Gauge32 MAX-ACCESS read-only STATUS current DESCRIPTION "The number of associations for which the current state is either ESTABLISHED, SHUTDOWN-RECEIVED or SHUTDOWN-PENDING." REFERENCE "Section 4 in RFC2960 covers the SCTP Association state diagram." If the T4 RTO timer expires many times(timeout), the association will enter CLOSED state, so we should dec the number of SCTP_MIB_CURRESTAB, not inc the number of SCTP_MIB_CURRESTAB. Signed-off-by: Wei Yongjun <yjwei@cn.fujitsu.com> Signed-off-by: Vlad Yasevich <vladislav.yasevich@hp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09myri10ge: remove over-paranoid queue number modulusBrice Goglin
No need to modulus the queue number in ->hard_start_xmit() since the core is going to do that for you modulus ->real_num_tx_queues. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09e1000: don't generate bad checksums for tcp packets with 0 csumDave Graham
When offloading transmit checksums only, the driver was not correctly configuring the hardware to handle the case of a zero checksum. For UDP the correct behavior is to leave it alone, but for tcp the checksum must be changed from 0x0000 to 0xFFFF. The hardware takes care of this case but only if it is told the packet is tcp. same patch as e1000e Signed-off-by: Dave Graham <david.graham@intel.com> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09e1000e: don't generate bad checksums for tcp packets with 0 csumDave Graham
When offloading transmit checksums only, the driver was not correctly configuring the hardware to handle the case of a zero checksum. For UDP the correct behavior is to leave it alone, but for tcp the checksum must be changed from 0x0000 to 0xFFFF. The hardware takes care of this case but only if it is told the packet is tcp. Signed-off-by: Dave Graham <david.graham@intel.com> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09bnx2: Update version to 1.8.1.Michael Chan
Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09bnx2: Handle DMA mapping errors.Benjamin Li
Before, the driver would not care about the return codes from pci_map_* functions. This could be potentially dangerous if a mapping failed. Now, we will check all pci_map_* calls. On the transmit side, we switch to use the new function skb_dma_map(). On the receive side, we add pci_dma_mapping_error(). Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09bnx2: Eliminate TSO header modifications.Michael Chan
This is now possible with updated firmware. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09bnx2: Update 5706/5708 firmware.Michael Chan
With this new firmware, the driver no longer has to modify the TCP/IP header fields when transmitting TSO packets. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09bnx2: Check netif_running() in all ethtool operations.Michael Chan
We need to check netif_running() state in most ethtool operations and properly handle the !netif_running() state where the chip is in an uninitailzed state or low power state that may not accept any MMIO. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09bnx2: Add bnx2_shutdown_chip().Michael Chan
This logic is used in bnx2_close() and bnx2_suspend() and so should be separated out into a separate function. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09inet: Make tunnel RX/TX byte counters more consistentHerbert Xu
This patch makes the RX/TX byte counters for IPIP, GRE and SIT more consistent. Previously we included the external IP headers on the way out but not when the packet is inbound. The new scheme is to count payload only in both directions. For IPIP and SIT this simply means the exclusion of the external IP header. For GRE this means that we exclude the GRE header as well. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09gre: Add Transparent Ethernet BridgingHerbert Xu
This patch adds support for Ethernet over GRE encapsulation. This is exposed to user-space with a new link type of "gretap" instead of "gre". It will create an ARPHRD_ETHER device in lieu of the usual ARPHRD_IPGRE. Note that to preserver backwards compatibility all Transparent Ethernet Bridging packets are passed to an ARPHRD_IPGRE tunnel if its key matches and there is no ARPHRD_ETHER device whose key matches more closely. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09gre: Add netlink interfaceHerbert Xu
This patch adds a netlink interface that will eventually displace the existing ioctl interface. It utilises the elegant rtnl_link_ops mechanism. This also means that user-space no longer needs to rely on the tunnel interface being of type GRE to identify GRE tunnels. The identification can now occur using rtnl_link_ops. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09gre: Move MTU setting out of ipgre_tunnel_bind_devHerbert Xu
This patch moves the dev->mtu setting out of ipgre_tunnel_bind_dev. This is in prepartion of using rtnl_link where we'll need to make the MTU setting conditional on whether the user has supplied an MTU. This also requires the move of the ipgre_tunnel_bind_dev call out of the dev->init function so that we can access the user parameters later. This patch also adds a check to prevent setting the MTU below the minimum of 68. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09gre: Use needed_headroomHerbert Xu
Now that we have dev->needed_headroom, we can use it instead of having a bogus dev->hard_header_len. This also allows us to include dev->hard_header_len in the MTU computation so that when we do have a meaningful hard_harder_len in future it is included automatically in figuring out the MTU. Incidentally, this fixes a bug where we ignored the needed_headroom field of the underlying device in calculating our own hard_header_len. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-09phylib: two dynamic mii_bus allocation fallout fixesLennert Buytenhek
1. arch/powerpc/platforms/pasemi/gpio_mdio.c also needs to be converted over to mdiobus_{alloc,free}(). 2. drivers/net/phy/fixed.c used to embed a struct mii_bus into its struct fixed_mdio_bus and then use container_of() to go from the former to the latter. Since mii bus structures are no longer embedded, we need to do something like use the mii bus private pointer to go from mii_bus to fixed_mdio_bus instead. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08jme: Fix warnings with CONFIG_PM disabled.David S. Miller
drivers/net/jme.c:1598: warning: ‘jme_set_100m_half’ defined but not used drivers/net/jme.c:1618: warning: ‘jme_wait_link’ defined but not used Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08jme: Advances version numberGuo-Fu Tseng
Advances the driver version after modification. Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08jme: Faulty IRQ handle bug fixakeemting
Fix IRQ handle bug when interrupt mode. The driver was incorrectly handled and returned IRQ_HANDLED while the device is not generating the interrupt. It happened due to faulty determination of interrupt status register. Found by: "Ethan" <ethanhsiao@jmicron.com> Fixed by: "akeemting" <akeem@jmicron.com> Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08jme: Added half-duplex mode and IPv6 RSS fixGuo-Fu Tseng
1. Set bit 5 of GPREG1 to 1 to enable hardware workaround for half-duplex mode. Which the MAC processor generates CRS/COL by itself instead of receive it from PHY processor. 2. Set bit 6 of GPREG1 to 1 to enable hardware workaround that masks the MAC processor working right while calculating IPv6 RSS in 10/100 mode. 3. Group the workaround codes all together. Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08cxgb3: Add 1G fiber supportDivy Le Ray
Add support for 1G optical Vitesse PHY. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08cxgb3: Support for Aeluros 2005 PHYDivy Le Ray
Add support for SR PHY. Auto-detect phy module type, and report type changes. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08cxgb3: commnonize LASI phy codeDivy Le Ray
Add generic code to manage interrupt driven PHYs. Do not reset the phy after link parameters update, the new values might get lost. Return early from link change notification when the link parameters remain unchanged. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08cxgb3: More flexible support for PHY interrupts.Divy Le Ray
Do not require PHY interrupts to be connected to GPIs in ascending order. Base interrupt availability both on PHYs supporting them and on GPIs being hooked up. Allows boards to specify interrupt GPIs though the PHYs don't use them. Remove spurious PHY interrupts due to clearing T3DBG interrupts before setting their polarity. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08cxgb3: simplify port type struct and usageDivy Le Ray
Second step in overall phy layer reorganization. Clean up the port_type_info structure. Support coextistence of clause 22 and clause 45 MDIO devices. Select the type of MDIO transaction on a per transaction basis. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08cxgb3: allow for PHY reset statusDivy Le Ray
First step towards overall PHY layering re-organization. Allow a status return when a PHY is reset. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08cxgb3: Allocate multiqueues at init timeDivy Le Ray
Allocate a queue set per core, up to the maximum of available qsets. Share the queue sets on multi port adapters. Rename MSI-X interrupt vectors ethX-N, N being the queue set number. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08cxgb3: reset the adapter on fatal errorDivy Le Ray
when a fatal error occurs, bring ports down, reset the chip, and bring ports back up. Factorize code used for both EEH and fatal error recovery. Fix timer usage when bringing up/resetting sge queue sets. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08dsa: Need to select PHYLIB.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08dsa: add support for the Marvell 88E6060 switch chipLennert Buytenhek
Add support for the Marvell 88E6060 switch chip. This chip only supports the Header and Trailer tagging formats, and we use it in Trailer mode since that mode is slightly easier to handle than Header mode. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Byron Bradley <byron.bbradley@gmail.com> Tested-by: Tim Ellis <tim.ellis@mac.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08dsa: add support for Trailer tagging formatLennert Buytenhek
This adds support for the Trailer switch tagging format. This is another tagging that doesn't explicitly mark tagged packets with a distinct ethertype, so that we need to add a similar hack in the receive path as for the Original DSA tagging format. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Byron Bradley <byron.bbradley@gmail.com> Tested-by: Tim Ellis <tim.ellis@mac.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08dsa: add support for the Marvell 88E6131 switch chipLennert Buytenhek
Add support for the Marvell 88E6131 switch chip. This chip only supports the original (ethertype-less) DSA tagging format. On the 88E6131, there is a PHY Polling Unit (PPU) which has exclusive access to each of the PHYs's MII management registers. If we want to talk to the PHYs from software, we have to disable the PPU and wait for it to complete its current transaction before we can do so, and we need to re-enable the PPU afterwards to make sure that the switch will notice changes in link state and speed on the individual ports as they occur. Since disabling the PPU is rather slow, and since MII management accesses are typically done in bursts, this patch keeps the PPU disabled for 10ms after a software access completes. This makes handling the PPU slightly more complex, but speeds up something like running ethtool on one of the switch slave interfaces from ~300ms to ~30ms on typical hardware. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Nicolas Pitre <nico@marvell.com> Tested-by: Peter van Valderen <linux@ddcrew.com> Tested-by: Dirk Teurlings <dirk@upexia.nl> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08dsa: add support for original DSA tagging formatLennert Buytenhek
Most of the DSA switches currently in the field do not support the Ethertype DSA tagging format that one of the previous patches added support for, but only the original DSA tagging format. The original DSA tagging format carries the same information as the Ethertype DSA tagging format, but with the difference that it does not have an ethertype field. In other words, when receiving a packet that is tagged with an original DSA tag, there is no way of telling in eth_type_trans() that this packet is in fact a DSA-tagged packet. This patch adds a hook into eth_type_trans() which is only compiled in if support for a switch chip that doesn't support Ethertype DSA is selected, and which checks whether there is a DSA switch driver instance attached to this network device which uses the old tag format. If so, it sets the protocol field to ETH_P_DSA without looking at the packet, so that the packet ends up in the right place. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Nicolas Pitre <nico@marvell.com> Tested-by: Peter van Valderen <linux@ddcrew.com> Tested-by: Dirk Teurlings <dirk@upexia.nl> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-08net: Distributed Switch Architecture protocol supportLennert Buytenhek
Distributed Switch Architecture is a protocol for managing hardware switch chips. It consists of a set of MII management registers and commands to configure the switch, and an ethernet header format to signal which of the ports of the switch a packet was received from or is intended to be sent to. The switches that this driver supports are typically embedded in access points and routers, and a typical setup with a DSA switch looks something like this: +-----------+ +-----------+ | | RGMII | | | +-------+ +------ 1000baseT MDI ("WAN") | | | 6-port +------ 1000baseT MDI ("LAN1") | CPU | | ethernet +------ 1000baseT MDI ("LAN2") | |MIImgmt| switch +------ 1000baseT MDI ("LAN3") | +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4") | | | | +-----------+ +-----------+ The switch driver presents each port on the switch as a separate network interface to Linux, polls the switch to maintain software link state of those ports, forwards MII management interface accesses to those network interfaces (e.g. as done by ethtool) to the switch, and exposes the switch's hardware statistics counters via the appropriate Linux kernel interfaces. This initial patch supports the MII management interface register layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and supports the "Ethertype DSA" packet tagging format. (There is no officially registered ethertype for the Ethertype DSA packet format, so we just grab a random one. The ethertype to use is programmed into the switch, and the switch driver uses the value of ETH_P_EDSA for this, so this define can be changed at any time in the future if the one we chose is allocated to another protocol or if Ethertype DSA gets its own officially registered ethertype, and everything will continue to work.) Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Nicolas Pitre <nico@marvell.com> Tested-by: Byron Bradley <byron.bbradley@gmail.com> Tested-by: Tim Ellis <tim.ellis@mac.com> Tested-by: Peter van Valderen <linux@ddcrew.com> Tested-by: Dirk Teurlings <dirk@upexia.nl> Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-088139too: move wmb before TX DMA startAndreas Oberritter
The write barrier should be used before starting a DMA transfer. This fixes a problem, where almost all packets received on another machine had garbled content. Tested with an RTL8100C on a MIPS machine. Signed-off-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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