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Adds the platform device definitions and the architecture specific
support routines (i.e. register initialization and descriptor formats) for the
iop-adma driver.
Changelog:
* added 'descriptor pool size' to the platform data
* add base support for buffer sizes larger than 16MB (hw max)
* build error fix from Kirill A. Shutemov
* rebase for async_tx changes
* add interrupt support
* do not call platform register macros in driver code
* remove unnecessary ARM assembly statement
* checkpatch.pl fixes
* gpl v2 only correction
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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CC arch/arm/mach-iop13xx/setup.o
arch/arm/mach-iop13xx/setup.c: In function 'iq8134x_probe_flash_size':
arch/arm/mach-iop13xx/setup.c:210: warning: implicit declaration of function 'ioremap'
arch/arm/mach-iop13xx/setup.c:210: warning: initialization makes pointer from integer without a cast
arch/arm/mach-iop13xx/setup.c:218: warning: implicit declaration of function 'writew'
arch/arm/mach-iop13xx/setup.c:222: warning: implicit declaration of function 'readb'
arch/arm/mach-iop13xx/setup.c:231: warning: implicit declaration of function 'iounmap'
LD .tmp_vmlinux1
arch/arm/mach-iop13xx/built-in.o: In function `iop13xx_platform_init':
iq81340mc.c:(.init.text+0x150): undefined reference to `ioremap'
iq81340mc.c:(.init.text+0x21c): undefined reference to `writew'
iq81340mc.c:(.init.text+0x24c): undefined reference to `writew'
iq81340mc.c:(.init.text+0x254): undefined reference to `iounmap'
iq81340mc.c:(.init.text+0x2c4): undefined reference to `readb'
iq81340mc.c:(.init.text+0x2e8): undefined reference to `readb'
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The struct resource 'end' field is inclusive, the iop13xx flash
setup code got this wrong.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a
Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory
controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz
PCI-X interface, a x8 PCI-Express interface, and other peripherals to form
a system-on-a-chip RAID subsystem engine.
The iop342 processor replaces the SAS controller with a second Xscale core
for dual core embedded applications.
The iop341 processor is the single core version of iop342.
This patch supports the two Intel customer reference platforms iq81340mc
for external storage and iq81340sc for direct attach (HBA) development.
The developer's manual is available here:
ftp://download.intel.com/design/iio/docs/31503701.pdf
Changelog:
* removed virtual addresses from resource definitions
* cleaned up some unnecessary #include's
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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