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2009-07-05[ARM] export __cpu_flush_dcache_pageRussell King
Now required for libsas: Kernel: arch/arm/boot/Image is ready Kernel: arch/arm/boot/zImage is ready Building modules, stage 2. MODPOST 1096 modules ERROR: "xscale_flush_kern_dcache_page" [drivers/scsi/libsas/libsas.ko] undefined! Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-06-22Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (49 commits) [ARM] idle: clean up pm_idle calling, obey hlt_counter [ARM] S3C: Fix gpio-config off-by-one bug [ARM] S3C64XX: add to_irq() support for EINT() GPIO [ARM] S3C64XX: clock.c: fix typo in usb-host clock ctrlbit [ARM] S3C64XX: fix HCLK gate defines [ARM] Update mach-types [ARM] wire up rt_tgsigqueueinfo and perf_counter_open OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL OMAP3: Add support for DPLL3 divisor values higher than 2 OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers OMAP3 SRAM: add more comments on the SRAM code OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change OMAP3 clock: add a short delay when lowering CORE clk rate OMAP3 clock: initialize SDRC timings at kernel start OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize [ARM] Add old Feroceon support to compressed/head.S [ARM] 5559/1: Limit the stack unwinding caused by a kthread exit [ARM] 5558/1: Add extra checks to ARM unwinder to avoid tracing corrupt stacks [ARM] 5557/1: Discard some ARM.ex*.*exit.text sections when !HOTPLUG or !HOTPLUG_CPU ...
2009-06-21Move FAULT_FLAG_xyz into handle_mm_fault() callersLinus Torvalds
This allows the callers to now pass down the full set of FAULT_FLAG_xyz flags to handle_mm_fault(). All callers have been (mechanically) converted to the new calling convention, there's almost certainly room for architectures to clean up their code and then add FAULT_FLAG_RETRY when that support is added. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-06-19[ARM] 5540/1: 32-bit Thumb-2 {ld,st}{m,rd} alignment fault fixup supportGeorge G. Davis
From: Min Zhang <mzhang@mvista.com> Add alignment fault fixup support for 32-bit Thumb-2 LDM, LDRD, POP, PUSH, STM and STRD instructions. Alignment fault fixup support for the remaining 32-bit Thumb-2 load/store instruction cases is not included since ARMv6 and later processors include hardware support for loads and stores of unaligned words and halfwords. Signed-off-by: Min Zhang <mzhang@mvista.com> Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-06-18Merge branch 'for-rmk' of ↵Russell King
git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel
2009-06-16[ARM] pxa/treo680: initial supportTomas 'Sleep_Walker' Cech
Signed-off-by: Tomáš Čech <sleep_walker@suse.cz> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
2009-06-14Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (417 commits) MAINTAINERS: EB110ATX is not ebsa110 MAINTAINERS: update Eric Miao's email address and status fb: add support of LCD display controller on pxa168/910 (base layer) [ARM] 5552/1: ep93xx get_uart_rate(): use EP93XX_SYSCON_PWRCNT and EP93XX_SYSCON_PWRCN [ARM] pxa/sharpsl_pm: zaurus needs generic pxa suspend/resume routines [ARM] 5544/1: Trust PrimeCell resource sizes [ARM] pxa/sharpsl_pm: cleanup of gpio-related code. [ARM] pxa/sharpsl_pm: drop set_irq_type calls [ARM] pxa/sharpsl_pm: merge pxa-specific code into generic one [ARM] pxa/sharpsl_pm: merge the two sharpsl_pm.c since it's now pxa specific [ARM] sa1100: remove unused collie_pm.c [ARM] pxa: fix the conflicting non-static declarations of global_gpios[] [ARM] 5550/1: Add default configure file for w90p910 platform [ARM] 5549/1: Add clock api for w90p910 platform. [ARM] 5548/1: Add gpio api for w90p910 platform [ARM] 5551/1: Add multi-function pin api for w90p910 platform. [ARM] Make ARM_VIC_NR depend on ARM_VIC [ARM] 5546/1: ARM PL022 SSP/SPI driver v3 ARM: OMAP4: SMP: Update defconfig for OMAP4430 ARM: OMAP4: SMP: Enable SMP support for OMAP4430 ...
2009-06-14Merge branch 'u300' into develRussell King
Conflicts: arch/arm/Makefile Updates: arch/arm/mach-u300/core.c arch/arm/mach-u300/timer.c
2009-06-11Merge branch 'for-rmk' of git://linux-arm.org/linux-2.6 into develRussell King
Conflicts: arch/arm/Kconfig arch/arm/kernel/smp.c arch/arm/mach-realview/Makefile arch/arm/mach-realview/platsmp.c
2009-06-02[ARM] ARMv7 errata: only apply fixes when running on applicable CPURussell King
Currently, whenever an erratum workaround is enabled, it will be applied whether or not the erratum is relevent for the CPU. This patch changes this - we check the variant and revision fields in the main ID register to determine which errata to apply. We also avoid re-applying erratum 460075 if it has already been applied. Applying this fix in non-secure mode results in the kernel failing to boot (or even do anything.) This fixes booting on some ARMv7 based platforms which otherwise silently fail. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-05-31[ARM] Kconfig: remove 'default n'Russell King
Kconfig entries default to n, so there's no need for this to be explicitly specified. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-05-30Add core support for ARMv6/v7 big-endianCatalin Marinas
Starting with ARMv6, the CPUs support the BE-8 variant of big-endian (byte-invariant). This patch adds the core support: - setting of the BE-8 mode via the CPSR.E register for both kernel and user threads - big-endian page table walking - REV used to rotate instructions read from memory during fault processing as they are still little-endian format - Kconfig and Makefile support for BE-8. The --be8 option must be passed to the final linking stage to convert the instructions to little-endian Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-05-30ARMv7: Document the PRRR and NMRR registers settingCatalin Marinas
This patch adds a comment to the proc-v7.S file for the setting of the PRRR and NMRR registers. It also sets the PRRR[13:12] bits to 0 (corresponding to the reserved TEX[0]CB encoding 110) to be consistent with the documentation. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-05-30ARMv7: Enable the SWP instructionCatalin Marinas
The SWP instruction has been deprecated starting with the ARMv6 architecture. On ARMv7 processors with the multiprocessor extensions (like Cortex-A9), this instruction is disabled by default but it can be enabled by setting bit 10 in the System Control register. Note that setting this bit is safe even if the ARMv7 processor has the SWP instruction enabled by default. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-05-30ARMv7: Mark the PTWs inner WBWA on SMP and WB on UPTony Thompson
There are additional bits to set for the ARMv7 SMP extensions in the TTBR registers. The IRGN bits order is counter-intuitive but it allows software built for the ARMv7 base architecture to run on an implementation with the MP extensions. Signed-off-by: Tony Thompson <Anthony.Thompson@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-05-30Check whether the TLB operations need broadcasting on SMP systemsCatalin Marinas
ARMv7 SMP hardware can handle the TLB maintenance operations broadcasting in hardware so that the software can avoid the costly IPIs. This patch adds the necessary checks (the MMFR3 CPUID register) to avoid the broadcasting if already supported by the hardware. (this patch is based on the work done by Tony Thompson @ ARM) Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-05-30RealView: Add support for the RealView/PBX platformColin Tuckley
This is a RealView platform supporting core tiles with ARM11MPCore, Cortex-A8 or Cortex-A9 (multicore) processors. It has support for MMC, CompactFlash, PCI-E. Signed-off-by: Colin Tuckley <colin.tuckley@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2009-05-25Merge branch 'iommu' of ↵Russell King
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git into devel
2009-05-19omap iommu: simple virtual address space managementHiroshi DOYU
This patch provides a device drivers, which has a omap iommu, with address mapping APIs between device virtual address(iommu), physical address and MPU virtual address. There are 4 possible patterns for iommu virtual address(iova/da) mapping. |iova/ mapping iommu_ page | da pa va (d)-(p)-(v) function type --------------------------------------------------------------------------- 1 | c c c 1 - 1 - 1 _kmap() / _kunmap() s 2 | c c,a c 1 - 1 - 1 _kmalloc()/ _kfree() s 3 | c d c 1 - n - 1 _vmap() / _vunmap() s 4 | c d,a c 1 - n - 1 _vmalloc()/ _vfree() n* 'iova': device iommu virtual address 'da': alias of 'iova' 'pa': physical address 'va': mpu virtual address 'c': contiguous memory area 'd': dicontiguous memory area 'a': anonymous memory allocation '()': optional feature 'n': a normal page(4KB) size is used. 's': multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used. '*': not yet, but feasible. Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
2009-05-02Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* master.kernel.org:/home/rmk/linux-2.6-arm: (45 commits) [ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data [ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created [ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch [ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail davinci: DM644x: NAND: update partitioning davinci: update DM644x support in preparation for more SoCs davinci: DM644x: rename board file davinci: update pin-multiplexing support davinci: serial: generalize for more SoCs davinci: DM355 IRQ Definitions davinci: DM646x: add interrupt number and priorities davinci: PSC: Clear bits in MDCTL reg before setting new bits davinci: gpio bugfixes davinci: add EDMA driver davinci: timers: use clk_get_rate() [ARM] pxa/littleton: add missing da9034 touchscreen support [ARM] pxa/zylonite: configure GPIO18/19 correctly, used by 2 GPIO expanders [ARM] pxa/zylonite: fix the issue of unused SDATA_IN_1 pin get AC97 not working [ARM] pxa: make ads7846 on corgi and spitz to sync on HSYNC [ARM] pxa: remove unused CPU_FREQ_PXA Kconfig symbol ...
2009-04-30[ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten ↵Catalin Marinas
with stale data This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It configures the L2 cache auxiliary control register so that the Write Allocate mode for the L2 cache is disabled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-04-30[ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is createdCatalin Marinas
This patch adds a workaround for the 458693 Cortex-A8 (r2p0) erratum. It sets the corresponding bits in the auxiliary control register so that the PLD instruction becomes a NOP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-04-30[ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branchCatalin Marinas
This patch adds the workaround for the 430973 Cortex-A8 (r1p0..r1p2) erratum. The BTAC/BTB is now flushed at every context switch. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-04-30[ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation ↵Catalin Marinas
can fail This patch implements the recommended workaround for erratum 411920 (ARM1136, ARM1156, ARM1176). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-04-28[ARM] 5480/1: U300-v5 integrate into the ARM architectureLinus Walleij
This hooks the U300 support into Kbuild and makes a small hook in mmu.c for supporting an odd memory alignment with shared memory on these systems. This is rebased to RMK:s GIT HEAD. This patch tries to add the Kconfig option in alphabetic order by option text and the Makefile entry after config symbol. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-04-27arm: Use __INIT macro instead of .text.init.Tim Abbott
arm is placing some code in the .text.init section, but it does not reference that section in its linker scripts. This change moves this code from the .text.init section to the .init.text section, which is presumably where it belongs. Signed-off-by: Tim Abbott <tabbott@mit.edu> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-04-04[ARM] pxa: Add support for suspend on PalmTX, T5 and LDMarek Vasut
Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
2009-04-01[ARM] 5439/1: Do not clear bit 10 of DFSR during abort handling on ARMv6Catalin Marinas
Because of an ARM1136 erratum (326103), the current v6_early_abort function needs to set the correct FSR[11] value which determines whether the data abort was caused by a read or write. For legacy reasons (bit 10 not handled by software), bit 10 was also cleared masking out imprecise aborts on ARMv6 CPUs. This patch removes the clearing of bit 10 of FSR. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-28[ARM] Kirkwood: small L2 code cleanupNicolas Pitre
Strictly speaking, a MCR instruction does not produce any output. Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-28[ARM] Kirkwood: invalidate L2 cache before enabling itMaxime Bizon
I get random oopses on my Kirkwood board at startup when L2 cache is enabled. FYI I'm using Marvell uboot version 3.4.16 Each boot produces the same oops, but anything that changes the kernel size (even only changing initramfs) makes the oops different. I noticed that nothing invalidates the L2 cache before enabling it, doing so fixes my problem. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-28Merge branch 'master' into develRussell King
Conflicts: arch/arm/include/asm/elf.h arch/arm/kernel/module.c
2009-03-28[ARM] 5435/1: fix compile warning in sanity_check_meminfo()Mikael Pettersson
Compiling recent 2.6.29-rc kernels for ARM gives me the following warning: arch/arm/mm/mmu.c: In function 'sanity_check_meminfo': arch/arm/mm/mmu.c:697: warning: comparison between pointer and integer This is because commit 3fd9825c42c784a59b3b90bdf073f49d4bb42a8d "[ARM] 5402/1: fix a case of wrap-around in sanity_check_meminfo()" in 2.6.29-rc5-git4 added a comparison of a pointer with PAGE_OFFSET, which is an integer. Fixed by casting PAGE_OFFSET to void *. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Acked-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-26Merge branch 'for-rmk' of git://gitorious.org/linux-gemini/mainline into develRussell King
Conflicts: arch/arm/mm/Kconfig Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-25ARM: Add support for FA526 v2Paulius Zaleckas
Adds support for Faraday FA526 core. This core is used at least by: Cortina Systems Gemini and Centroid family Cavium Networks ECONA family Grain Media GM8120 Pixelplus ImageARM Prolific PL-1029 Faraday IP evaluation boards v2: - move TLB_BTB to separate patch - update copyrights Signed-off-by: Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
2009-03-24Merge branch 'highmem' into develRussell King
2009-03-24Merge branch 'devel' of ↵root
git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel
2009-03-23[ARM] pxa: add base support for Marvell's PXA168 processor lineEric Miao
"""The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: Jason Chagas <chagas@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
2009-03-19Merge branch 'master' of git://git.marvell.com/orion into develRussell King
Conflicts: arch/arm/mach-mx1/devices.c
2009-03-15[ARM] ignore high memory with VIPT aliasing cachesNicolas Pitre
VIPT aliasing caches have issues of their own which are not yet handled. Usage of discard_old_kernel_data() in copypage-v6.c is not highmem ready, kmap/fixmap stuff doesn't take account of cache colouring, etc. If/when those issues are handled then this could be reverted. Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-15[ARM] xsc3: add highmem support to L2 cache handling codeNicolas Pitre
On xsc3, L2 cache ops are possible only on virtual addresses. The code is rearranged so to have a linear progression requiring the least amount of pte setups in the highmem case. To protect the virtual mapping so created, interrupts must be disabled currently up to a page worth of address range. The interrupt disabling is done in a way to minimize the overhead within the inner loop. The alternative would consist in separate code for the highmem and non highmem compilation which is less preferable. Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-15[ARM] Feroceon: add highmem support to L2 cache handling codeNicolas Pitre
The choice is between looping over the physical range and performing single cache line operations, or to map highmem pages somewhere, as cache range ops are possible only on virtual addresses. Because L2 range ops are much faster, we go with the later by factoring the physical-to-virtual address conversion and use a fixmap entry for it in the HIGHMEM case. Possible future optimizations to avoid the pte setup cost: - do the pte setup for highmem pages only - determine a threshold for doing a line-by-line processing on physical addresses when the range is small Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-15[ARM] introduce dma_cache_maint_page()Nicolas Pitre
This is a helper to be used by the DMA mapping API to handle cache maintenance for memory identified by a page structure instead of a virtual address. Those pages may or may not be highmem pages, and when they're highmem pages, they may or may not be virtually mapped. When they're not mapped then there is no L1 cache to worry about. But even in that case the L2 cache must be processed since unmapped highmem pages can still be L2 cached. Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-15[ARM] mem_init(): make highmem pages available for useNicolas Pitre
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-15[ARM] kmap supportNicolas Pitre
The kmap virtual area borrows a 2MB range at the top of the 16MB area below PAGE_OFFSET currently reserved for kernel modules and/or the XIP kernel. This 2MB corresponds to the range covered by 2 consecutive second-level page tables, or a single pmd entry as seen by the Linux page table abstraction. Because XIP kernels are unlikely to be seen on systems needing highmem support, there shouldn't be any shortage of VM space for modules (14 MB for modules is still way more than twice the typical usage). Because the virtual mapping of highmem pages can go away at any moment after kunmap() is called on them, we need to bypass the delayed cache flushing provided by flush_dcache_page() in that case. The atomic kmap versions are based on fixmaps, and __cpuc_flush_dcache_page() is used directly in that case. Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-15[ARM] fixmap supportNicolas Pitre
This is the minimum fixmap interface expected to be implemented by architectures supporting highmem. We have a second level page table already allocated and covering 0xfff00000-0xffffffff because the exception vector page is located at 0xffff0000, and various cache tricks already use some entries above 0xffff0000. Therefore the PTEs covering 0xfff00000-0xfffeffff are free to be used. However the XScale cache flushing code already uses virtual addresses between 0xfffe0000 and 0xfffeffff. So this reserves the 0xfff00000-0xfffdffff range for fixmap stuff. The Documentation/arm/memory.txt information is updated accordingly, including the information about the actual top of DMA memory mapping region which didn't match the code. Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-13Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into develRussell King
Conflicts: arch/arm/mach-at91/gpio.c
2009-03-13[ARM] MX31/MX35: Add l2x0 cache supportSascha Hauer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-03-12[ARM] Fix virtual to physical translation macro corner casesRussell King
The current use of these macros works well when the conversion is entirely linear. In this case, we can be assured that the following holds true: __va(p + s) - s = __va(p) However, this is not always the case, especially when there is a non-linear conversion (eg, when there is a 3.5GB hole in memory.) In this case, if 's' is the size of the region (eg, PAGE_SIZE) and 'p' is the final page, the above is most definitely not true. So, we must ensure that __va() and __pa() are only used with valid kernel direct mapped RAM addresses. This patch tweaks the code to achieve this. Tested-by: Charles Moschel <fred99@carolina.rr.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-12[ARM] 5421/1: ftrace: fix crash due to tracing of __naked functionsUwe Kleine-König
This is a fix for the following crash observed in 2.6.29-rc3: http://lkml.org/lkml/2009/1/29/150 On ARM it doesn't make sense to trace a naked function because then mcount is called without stack and frame pointer being set up and there is no chance to restore the lr register to the value before mcount was called. Reported-by: Matthias Kaehlcke <matthias@kaehlcke.net> Tested-by: Matthias Kaehlcke <matthias@kaehlcke.net> Cc: Abhishek Sagar <sagar.abhishek@gmail.com> Cc: Steven Rostedt <rostedt@home.goodmis.org> Cc: Ingo Molnar <mingo@elte.hu> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-12[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory typePaul Walmsley
This patch adds a Non-cacheable Normal ARM executable memory type, MT_MEMORY_NONCACHED. On OMAP3, this is used for rapid dynamic voltage/frequency scaling in the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the VDD2 voltage domain, and its clock frequency must change along with voltage. The SDRC clock change code cannot run from SDRAM itself, since SDRAM accesses are paused during the clock change. So the current implementation of the DVFS code executes from OMAP on-chip SRAM, aka "OCM RAM." If the OCM RAM pages are marked as Cacheable, the ARM cache controller will attempt to flush dirty cache lines to the SDRC, so it can fill those lines with OCM RAM instruction code. The problem is that the SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU subsystem to hang. TI's original solution to this problem was to mark the OCM RAM sections as Strongly Ordered memory, thus preventing caching. This is overkill: since the memory is marked as non-bufferable, OCM RAM writes become needlessly slow. The idea of "Strongly Ordered SRAM" is also conceptually disturbing. Previous LAKML list discussion is here: http://www.spinics.net/lists/arm-kernel/msg54312.html This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future patch. Cc: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>