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2006-01-09[ARM] 3070/2: Add __ioremap_pfn() APIDeepak Saxena
Patch from Deepak Saxena In working on adding 36-bit addressed supersection support to ioremap(), I came to the conclusion that it would be far simpler to do so by just splitting __ioremap() into a main external interface and adding an __ioremap_pfn() function that takes a pfn + offset into the page that __ioremap() can call. This way existing callers of __ioremap() won't have to change their code and 36-bit systems will just call __ioremap_pfn() and we will not have to deal with unsigned long long variables. Note that __ioremap_pfn() should _NOT_ be called directly by drivers but is reserved for use by arch_ioremap() implementations that map 32-bit resource regions into the real 36-bit address and then call this new function. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-09[ARM] 3240/2: AT91RM9200 support for 2.6 (Core)SAN People
Patch from SAN People Following changes were made to clock.c: 1) Replaced <asm/hardware/clock.h> with <linux/clk.h> 2) Removed old unused clk_enable & clk_disable. 3) Replaced clk_use/clk_unuse with clk_enable/clk_disable. Otherwise it's the same as the previous patch. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-08[ARM] Remove EPXA10DB machine supportRussell King
EPXA10DB seems to be uncared for: - the "PLD" code has never been merged - no one has reported that this platform has been broken since at least 2.6.10 - interest seems to have dried up around March 2003. Therefore, remove EPXA10DB support. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-03[ARM] Cleanup ARM includesRussell King
arch/arm/kernel/entry-armv.S has contained a comment suggesting that asm/hardware.h and asm/arch/irqs.h should be moved into the asm/arch/entry-macro.S include. So move the includes to these two files as required. Add missing includes (asm/hardware.h, asm/io.h) to asm/arch/system.h includes which use those facilities, and remove asm/io.h from kernel/process.c. Remove other unnecessary includes from arch/arm/kernel, arch/arm/mm and arch/arm/mach-footbridge. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-30[ARM SMP] Disable lazy flush_dcache_page for SMPRussell King
Lazy flush_dcache_page() causes userspace instability on SMP platforms, so disable it for now. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-25[ARM] Do not call flush_tlb_kernel_range() with IRQs disabled.Russell King
We must not call TLB maintainence operations with interrupts disabled, otherwise we risk a lockup in the SMP IPI code. This means that consistent_free() can not be called from a context with IRQs disabled. In addition, we must not hold the lock in consistent_free when we call flush_tlb_kernel_range(). However, we must continue to prevent consistent_alloc() from re-using the memory region until we've finished tearing down the mapping and dealing with the TLB. Therefore, leave the vm_region entry in the list, but mark it inactive before dropping the lock and starting the tear-down process. After the mapping has been torn down, re-acquire the lock and remove the entry from the list. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-19[ARM] 3168/1: Update ARM signal delivery and maskingDaniel Jacobowitz
Patch from Daniel Jacobowitz After delivering a signal (creating its stack frame) we must check for additional pending unblocked signals before returning to userspace. Otherwise signals may be delayed past the next syscall or reschedule. Once that was fixed it became obvious that the ARM signal mask manipulation was broken. It was a little bit broken before the recent SA_NODEFER changes, and then very broken after them. We must block the requested signals before starting the handler or the same signal can be delivered again before the handler even gets a chance to run. Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-17[ARM] Fix some corner cases in new mm initialisationRussell King
Document that the VMALLOC_END address must be aligned to 2MB since it must align with a PGD boundary. Allocate the vectors page early so that the flush_cache_all() later will cause any dirty cache lines in the direct mapping will be safely written back. Move the flush_cache_all() to the second local_flush_cache_tlb() and remove the now redundant first local_flush_cache_tlb(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-17[ARM] __ioremap doesn't use 4th argumentRussell King
The "align" argument in ARMs __ioremap is unused and provides a misleading expectation that it might do something. It doesn't. Remove it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-10[ARM] 3145/1: OMAP 3a/5: Add support for omap24xxTony Lindgren
Patch from Tony Lindgren This patch adds support for omap24xx series of processors. The files live in arch/arm/mach-omap2, and share common files with omap15xx and omap16xx processors in arch/arm/plat-omap. Omap24xx support was originally added for 2.6.9 by TI. This code was then improved and integrated to share common code with omap15xx and omap16xx processors by various omap developers, such as Paul Mundt, Juha Yrjola, Imre Deak, Tony Lindgren, Richard Woodruff, Nishant Menon, Komal Shah et al. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-10[ARM] 3141/1: OMAP 1/5: Update omap1 specific filesTony Lindgren
Patch from Tony Lindgren This patch syncs the mainline kernel with linux-omap tree. The highlights of the patch are: - Omap1 serial pport and framebuffer init updates by Imre Deak - Add support for omap310 processor and Palm Tungsten E PDA by Laurent Gonzales, Romain Goyet, et al. Omap310 and omap1510 processors are now handled as omap15xx. - Omap1 specific changes to shared omap clock framework by Tony Lindgren - Omap1 specific changes to shared omap pin mux framework by Tony Lindgren - Other misc fixes, such as update memory timings for smc91x, omap1 specific device initialization etc. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-07[ARM SMP] Add Realview MPcore SMP supportRussell King
Add SMP support for the MPcore tile fitted to the Realview ARM platform. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-07[ARM SMP] Add support for shared memory attributeRussell King
We need to set the shared memory attribute in the page tables on SMP systems to allow the cache coherency to operate. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-03[ARM] Merge SMP treeRussell King
2005-11-03[ARM] 3092/1: remove excessive print format paddingNicolas Pitre
Patch from Nicolas Pitre Using a llx format to print addresses that might possibly be (only) 36 bits wide make sense. However making it a zero padded 16 char wide field is a bit excessive and useless. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-03[ARM SMP] Add configuration option for ARMv6K processorsRussell King
The 'K' extension adds several new instructions to the ARMv6 ISA which are primerily useful for SMP. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-02[ARM] Fix mm initialisation with write buffered write allocate cachesRussell King
It seems that without the extra tlb flush, we may end up faulting during the early kernel initialisation because the TLB can't see the updated page tables. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-31[ARM] Add support for ARM RealView boardCatalin Marinas
Support for RealView EB. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-30[ARM] Make v6 copypage function static and cleanup pgprotsRussell King
We know what pgprot we're going to use, so don't #define it. Also, since we select the nonaliasing/aliasing copypage implementation at run time, there's no point having it globally visible. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-29[PATCH] mm: split page table lockHugh Dickins
Christoph Lameter demonstrated very poor scalability on the SGI 512-way, with a many-threaded application which concurrently initializes different parts of a large anonymous area. This patch corrects that, by using a separate spinlock per page table page, to guard the page table entries in that page, instead of using the mm's single page_table_lock. (But even then, page_table_lock is still used to guard page table allocation, and anon_vma allocation.) In this implementation, the spinlock is tucked inside the struct page of the page table page: with a BUILD_BUG_ON in case it overflows - which it would in the case of 32-bit PA-RISC with spinlock debugging enabled. Splitting the lock is not quite for free: another cacheline access. Ideally, I suppose we would use split ptlock only for multi-threaded processes on multi-cpu machines; but deciding that dynamically would have its own costs. So for now enable it by config, at some number of cpus - since the Kconfig language doesn't support inequalities, let preprocessor compare that with NR_CPUS. But I don't think it's worth being user-configurable: for good testing of both split and unsplit configs, split now at 4 cpus, and perhaps change that to 8 later. There is a benefit even for singly threaded processes: kswapd can be attacking one part of the mm while another part is busy faulting. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29[PATCH] mm: arm ready for split ptlockHugh Dickins
Prepare arm for the split page_table_lock: three issues. Signal handling's preserve and restore of iwmmxt context currently involves reading and writing that context to and from user space, while holding page_table_lock to secure the user page(s) against kswapd. If we split the lock, then the structure might span two pages, secured by to read into and write from a kernel stack buffer, copying that out and in without locking (the structure is 160 bytes in size, and here we're near the top of the kernel stack). Or would the overhead be noticeable? arm_syscall's cmpxchg emulation use pte_offset_map_lock, instead of pte_offset_map and mm-wide page_table_lock; and strictly, it should now also take mmap_sem before descending to pmd, to guard against another thread munmapping, and the page table pulled out beneath this thread. Updated two comments in fault-armv.c. adjust_pte is interesting, since its modification of a pte in one part of the mm depends on the lock held when calling update_mmu_cache for a pte in some other part of that mm. This can't be done with a split page_table_lock (and we've already taken the lowest lock in the hierarchy here): so we'll have to disable split on arm, unless CONFIG_CPU_CACHE_VIPT to ensures adjust_pte never used. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29[PATCH] mm: arches skip ptlockHugh Dickins
Convert those few architectures which are calling pud_alloc, pmd_alloc, pte_alloc_map on a user mm, not to take the page_table_lock first, nor drop it after. Each of these can continue to use pte_alloc_map, no need to change over to pte_alloc_map_lock, they're neither racy nor swappable. In the sparc64 io_remap_pfn_range, flush_tlb_range then falls outside of the page_table_lock: that's okay, on sparc64 it's like flush_tlb_mm, and that has always been called from outside of page_table_lock in dup_mmap. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29[PATCH] mm: init_mm without ptlockHugh Dickins
First step in pushing down the page_table_lock. init_mm.page_table_lock has been used throughout the architectures (usually for ioremap): not to serialize kernel address space allocation (that's usually vmlist_lock), but because pud_alloc,pmd_alloc,pte_alloc_kernel expect caller holds it. Reverse that: don't lock or unlock init_mm.page_table_lock in any of the architectures; instead rely on pud_alloc,pmd_alloc,pte_alloc_kernel to take and drop it when allocating a new one, to check lest a racing task already did. Similarly no page_table_lock in vmalloc's map_vm_area. Some temporary ugliness in __pud_alloc and __pmd_alloc: since they also handle user mms, which are converted only by a later patch, for now they have to lock differently according to whether or not it's init_mm. If sources get muddled, there's a danger that an arch source taking init_mm.page_table_lock will be mixed with common source also taking it (or neither take it). So break the rules and make another change, which should break the build for such a mismatch: remove the redundant mm arg from pte_alloc_kernel (ppc64 scrapped its distinct ioremap_mm in 2.6.13). Exceptions: arm26 used pte_alloc_kernel on user mm, now pte_alloc_map; ia64 used pte_alloc_map on init_mm, now pte_alloc_kernel; parisc had bad args to pmd_alloc and pte_alloc_kernel in unused USE_HPPA_IOREMAP code; ppc64 map_io_page forgot to unlock on failure; ppc mmu_mapin_ram and ppc64 im_free took page_table_lock for no good reason. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29[ARM] 3059/1: fix XIP supportNicolas Pitre
Patch from Nicolas Pitre Fix XIP support after recent bootmem code refactoring. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-28Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
Minor manual fixups for gfp_t clashes.
2005-10-28[PATCH] gfp_t: dma-mapping (arm)Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-28[ARM] 3017/1: Add support for 36-bit addresses to create_mapping()Deepak Saxena
Patch from Deepak Saxena This patch adds support for 36-bit static mapped I/O. While there are no platforms in the tree ATM that use it, it has been tested tested on the IXP2350 NPU and I would like to get the support for that chipset upstream one piece at a time. There are also other Intel chipset ports in development that are waiting on this to go upstream. The patch replaces the print formats for physical addresses with %016llx which will create a bit extraneous output on 32-bit systems, but I think that is cleaner than having #ifdefs, specially since users will only see the output in error cases. Depends on 3016/1. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-28[ARM] 3016/1: Replace map_desc.physical with map_desc.pfnDeepak Saxena
Patch from Deepak Saxena Convert map_desc.physical to map_desc.pfn. This allows us to add support for 36-bit addressed physical devices in the static maps without having to resort to u64 variables. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-28[ARM] Re-jig bootmem initialisationRussell King
Make ARM independent of the way bootmem operates internally. We now map each node as we initialise it, and place the bootmem bitmap inside each node, rather than all in the first node. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-28[ARM] Fix sparse warningsRussell King
Fix sparse warnings in arch/arm/kernel/module.c, arch/arm/mm/consistent.c, drivers/pcmcia/sa1111_generic.c, and platform support files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-28[ARM] 3/4: Remove asm/hardware.h from SA1100 io.hRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-19[ARM] 3024/1: Add cpu_v6_proc_finTony Lindgren
Patch from Tony Lindgren Machine restart calls cpu_proc_fin() to clean and disable cache, and turn off interrupts. This patch adds proper cpu_v6_proc_fin. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-12[ARM] 2969/1: miscellaneous whitespace cleanupGeorge G. Davis
Patch from George G. Davis Fix leading, trailing and other miscellaneous whitespace issues in arch/arm/kernel/alignment.c. Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-10[ARM] 2959/1: Add test for invalid LDRD/STRD Rd cases in ARM alignment handlerGeorge G. Davis
Patch from George G. Davis Add test for invalid LDRD/STRD Rd cases in ARM alignment handler and restore SWP printk KERN_ERR. Signed-off-by: Steve Longerbeam <slongerbeam@mvista.com> Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-05[ARM] 2954/1: Allow D and I cache and branch prediction disabling for ARMv6Catalin Marinas
Patch from Catalin Marinas There is no reason to not allow these config options. They are useful when the hardware has problems. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-02[ARM] 2943/1: Clear the exclusive monitor in v6_early_abortCatalin Marinas
Patch from Catalin Marinas Data abort caused by ldrex/strex can leave the exclusive monitor in an unpredictable state. It is recommended that a clrex/strex is performed to clear this state. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-30[ARM] 2940/1: Fix BTB entry flush in arch/arm/mm/cache-v6.SGen FUKATSU
Patch from Gen FUKATSU Invalidate BTB entry instruction flushes two instruction at a time. Therefore this instruction should be done four times after invalidate instruction cache line. Signed-off-by: Gen Fukatsu Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-30[ARM] 2939/1: Fix compilation error in arch/arm/mm/flush.cCatalin Marinas
Patch from Catalin Marinas When CONFIG_CPU_CACHE_VIPT is defined, the flush_pfn_alias() function is implicitely declared and it later conflicts with its actual definition. This patch moves the function definition to the beginning of the file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-20[ARM] Prevent deadlock in page fault handlerRussell King
As per x86, we may deadlock while trying to get the mmap semaphore. Implement the same fix, which allows (eg) recursive faults to cause an oops instead of deadlocking. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-20[ARM] 2926/1: .proc.info - postfix section with .init for `make buildcheck`Ben Dooks
Patch from Ben Dooks The `make buildcheck` is erroneously reporting that the .proc.info list is referencing items in the .init section as it is not itself postfixed with .init Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-09Merge master.kernel.org:/pub/scm/linux/kernel/git/sam/kbuild Linus Torvalds
2005-09-09kbuild: arm - use generic asm-offsets.h supportSam Ravnborg
Delete obsoleted stuff from arch Makefile and rename constants.h to asm-offsets.h Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2005-09-08[ARM] Fix ARMv6 VIPT cache >= 32KRussell King
This adds the necessary changes to ensure that we flush the caches correctly with aliasing VIPT caches. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-04[ARM] 2875/1: Data Abort fixesTimothy Baldwin
Patch from Timothy Baldwin All data aborts are treated as read accesses. The existing code updates the wrong bit of r1, also the comments are wrong in that the sense of the L bit is inverted. Signed-off-by: Timothy E. Baldwin <T.E.Baldwin99@members.leeds.ac.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-01[ARM] Fix ARMv6 page table bitsRussell King
We weren't explicitly setting the page table bits we desired in user_prot in the protection table, which resulted in the user mappings for v6 CPUs being marked global. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-01[ARM] Simplify setup_mm_for_reboot()Russell King
No point checking what CPU architecture level we have each time within the loop, so precompute the base PMD flags outside the loop. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-01[ARM] Convert open-coded __pmd_populate to use inline functionRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-31[ARM] 2867/2: unaligned ldrd/strd fixupsSteve Longerbeam
Patch from Steve Longerbeam Adds an implementation of unaligned LDRD and STRD fixups. Also fixes a bug where do_alignment() would misinterpret and fixup an unaligned LDRD/STRD as LDRH/STRH, causing memory corruption. This is the same as Patch #2867/1, but with minor whitespace and comments changes, plus a check for arch-level >= v5TE before printing ai_dword count in proc_alignment_read(). Signed-off-by: Steve Longerbeam <stevel@mwwireless.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-29[ARM] 2853/1: Make alloc_init_supersection() work with 36-bit mappingsDeepak Saxena
Patch from Deepak Saxena Working on adding support for 36-bit static mappings for ARMv6 and Intel's XSC3 core and noticed that alloc_init_supersection currently increments the phys addr by 1MB on each of the 16 iterations and then forces alignment to supersection size (16MB). This is really uneeded b/c we have already forced the phys address to be 16MB aligned in create_mapping(). Furthermore, this breaks 36-bit addressing b/c bits [23:20] of the PMD contain bits [35:32] of the physical address and the masking causes us to loose those bits thus ending up with an incorrect virt -> phys translation. The other option is to have an alloc_init_supersection36. Tested on Intel IXP2350 CPU with 36-bit static I/O mappings. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-17[ARM] 2852/1: Correct the mistake in arch/arm/mm/Kconfig fileSean Lee
Patch from Sean Lee In the arch/arm/mm/Kconfig file, the CPU_DCACHE_WRITETHROUGH option is depend on the CPU_DISABLE_DCACHE, but the "Disable D-Cache" option is configured as CPU_DCACHE_DISABLE. The CPU_DISABLE_DCACHE should be CPU_DCACHE_DISABLE Signed-off-by: Sean Lee <beginner2arm@eyou.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>