aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/include/asm
AgeCommit message (Collapse)Author
2009-08-17Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: MIPS: Fix HPAGE_SIZE redefinition
2009-08-17MIPS: Fix HPAGE_SIZE redefinitionAtsushi Nemoto
This patch fixes warnings like this: CC fs/proc/meminfo.o In file included from /work/linux/include/linux/mmzone.h:20, from /work/linux/include/linux/gfp.h:4, from /work/linux/include/linux/mm.h:8, from /work/linux/fs/proc/meminfo.c:5: /work/linux/arch/mips/include/asm/page.h:36:1: warning: "HPAGE_SIZE" redefined In file included from /work/linux/fs/proc/meminfo.c:2: /work/linux/include/linux/hugetlb.h:107:1: warning: this is the location of the previous definition Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-08-03MIPS: Wire up accept4 syscall.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-08-03MIPS: MSPxxxx: define MIPS34K_MISSED_ITLB_WAR for other PMC-Sierra SoCFlorian Fainelli
Trying to build a PMC-Sierra MSP4200 VoIP gateway defconfig will not work since MIPS34K_MISSED_ITLB_WAR is not defined for all boards supported within pmc-serria/msp71xx. This patch defines MIPS34K_MISSED_ITLB_WAR to prevent such build failures: CHK include/linux/version.h CHK include/linux/utsrelease.h SYMLINK include/asm -> include/asm-mips CC arch/mips/kernel/asm-offsets.s In file included fromlinux-msp71xx/linux-2.6.29/arch/mips/include/asm/bitops.h:24, from include/linux/bitops.h:17, from include/linux/kernel.h:15, from include/linux/sched.h:52, from arch/mips/kernel/asm-offsets.c:13: linux-msp71xx/linux-2.6.29/arch/mips/include/asm/war.h:241:2: error: #error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform This fixes a compile error when building for the MSP4200 boards. Identical patches to fix this were send by Florian Fainelli <florian@openwrt.org> Shane McDonald <mcdonald.shane@gmail.com> Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-08-03MIPS: Avoid clobbering struct pt_regs in kthreadsDavid Daney
The resume() implementation octeon_switch.S examines the saved cp0_status register. We were clobbering the entire pt_regs structure in kernel threads leading to random crashes. When switching away from a kernel thread, the saved cp0_status is examined and if bit 30 is set it is cleared and the CP2 state saved into the pt_regs structure. Since the kernel thread stack overlaid the pt_regs structure this resulted in a corrupt stack. When the kthread with the corrupt stack was resumed, it could crash if it used any of the data in the stack that was clobbered. We fix it by moving the kernel thread stack down so it doesn't overlay pt_regs. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-08-03MIPS: Fix compile for !CONFIG_SMPAlexander Clouter
Commit fc03bc1715ca0ad4ccfe97aab16bcc9e7129c1a4 breaks compiling MIPS with SMP disabled. This patch fixes that. Signed-off-by: Alexander Clouter <alex@digriz.org.uk> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-08-03MIPS: Eleminate filenames from commentsRalf Baechle
They tend to get not updated when files are moved around or copied and lack any obvious use. While at it zap some only too obvious comments and as per Shinya's suggestion, add a copyright header to extable.c. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Acked-by: Thadeu Lima de Souza Cascardo <cascardo@holoscopio.com>
2009-07-27mm: Remove duplicate definitions in MIPS and SHBenjamin Herrenschmidt
Those definitions are already provided by asm-generic Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-07-27mm: Pass virtual address to [__]p{te,ud,md}_free_tlb()Benjamin Herrenschmidt
mm: Pass virtual address to [__]p{te,ud,md}_free_tlb() Upcoming paches to support the new 64-bit "BookE" powerpc architecture will need to have the virtual address corresponding to PTE page when freeing it, due to the way the HW table walker works. Basically, the TLB can be loaded with "large" pages that cover the whole virtual space (well, sort-of, half of it actually) represented by a PTE page, and which contain an "indirect" bit indicating that this TLB entry RPN points to an array of PTEs from which the TLB can then create direct entries. Thus, in order to invalidate those when PTE pages are deleted, we need the virtual address to pass to tlbilx or tlbivax instructions. The old trick of sticking it somewhere in the PTE page struct page sucks too much, the address is almost readily available in all call sites and almost everybody implemets these as macros, so we may as well add the argument everywhere. I added it to the pmd and pud variants for consistency. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: David Howells <dhowells@redhat.com> [MN10300 & FRV] Acked-by: Nick Piggin <npiggin@suse.de> Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> [s390] Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-07-10sched: INIT_PREEMPT_COUNTPeter Zijlstra
Pull the initial preempt_count value into a single definition site. Maintainers for: alpha, ia64 and m68k, please have a look, your arch code is funny. The header magic is a bit odd, but similar to the KERNEL_DS one, CPP waits with expanding these macros until the INIT_THREAD_INFO macro itself is expanded, which is in arch/*/kernel/init_task.c where we've already included sched.h so we're good. Cc: tony.luck@intel.com Cc: rth@twiddle.net Cc: geert@linux-m68k.org Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Matt Mackall <mpm@selenic.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-07-03MIPS: Fix CONFIG_FLATMEM version of pfn_valid()Ralf Baechle
For systems which do not define PHYS_OFFSET as 0 pfn_valid() may falsely have returned 0 on most configurations. Bug introduced by commit 752fbeb2e3555c0d236e992f1195fd7ce30e728d (linux-mips.org) rsp. 6f284a2ce7b8bc49cb8455b1763357897a899abb (kernel.org) titled "[MIPS] FLATMEM: introduce PHYS_OFFSET." Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03MIPS: Reorganize Cavium OCTEON PCI support.David Daney
Move the cavium PCI files to the arch/mips/pci directory. Also cleanup comment formatting and code layout. Code from pci-common.c, was moved into other files. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03Update Yoichi Yuasa's e-mail addressYoichi Yuasa
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03MIPS: 64-bit: Fix o32 core dumpYong Zhang
If an o32 process generates a core dump on a 64 bit kernel, the core file will not be correctly recognized. This is because ELF_CORE_COPY_REGS and ELF_CORE_COPY_TASK_REGS are not correctly defined for o32 and will use the default register set which would be CONFIG_64BIT in asm/elf.h. So we'll switch to use the right register defines in this situation by checking for WANT_COMPAT_REG_H and use the right defines of ELF_CORE_COPY_REGS and ELF_CORE_COPY_TASK_REGS. [Ralf: made ELF_CORE_COPY_TASK_REGS() bullet-proof against funny arguments.] Signed-off-by: Yong Zhang <yong.zhang@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03MIPS: CMP: Move gcmp_probe to before the SMP opsTim Anderson
This is to move the gcmp_probe call to before the use of and selection of the smp_ops functions. This allows malta with 1004K to work. Signed-off-by: Tim Anderson <tanderson@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03MIPS: CMP: activate CMP supportTim Anderson
Most of the CMP support was added before, this mostly correct compile problems but adds a platform specific translation for the interrupt number based on cpu number. Signed-off-by: Tim Anderson <tanderson@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03MIPS: CMP: Extend the GIC IPI interrupts beyond 32Tim Anderson
This patch extends the GIC interrupt handling beyond the current 32 bit range as well as extending the number of interrupts based on the number of CPUs. Signed-off-by: Tim Anderson <tanderson@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03MIPS: Define __arch_swab64 for all mips r2 cpusDavid Daney
Some CPUs implement mipsr2, but because they are a super-set of mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into this category. We would still like to use the optimized implementation, so since we have already checked for CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of CONFIG_CPU_MIPS64_R2 is sufficient. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03MIPS: Update VR41xx GPIO driver to use gpiolibYoichi Yuasa
Signed-off-by: Yoichi Yuasa <yyuasa@linux.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03MIPS: Hookup new syscalls sys_rt_tgsigqueueinfo and sys_perf_counter_open.David Daney
[Ralf: I fixed up the numbering in the comment in scall64-n32.S.] Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-07-03MIPS: Add support for Texas Instruments AR7 System-on-a-ChipFlorian Fainelli
This patch adds support for the Texas Instruments AR7 System-on-a-Chip. It supports the TNETD7100, 7200 and 7300 versions of the SoC. Signed-off-by: Matteo Croce <matteo@openwrt.org> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Eugene Konev <ejka@openwrt.org> Signed-off-by: Nicolas Thill <nico@openwrt.org> Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24MIPS: Cavium: Add CPU hotplugging code.Ralf Baechle
Thanks to Cavium Inc. for the code contribution and help. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24MIPS: Add arch generic CPU hotplugRalf Baechle
Each platform has to add support for CPU hotplugging itself by providing suitable definitions for the cpu_disable and cpu_die of the smp_ops methods and setting SYS_SUPPORTS_HOTPLUG_CPU. A platform should only set SYS_SUPPORTS_HOTPLUG_CPU once all it's smp_ops definitions have the necessary changes. This patch contains the changes to the dummy smp_ops definition for uni-processor systems. Parts of the code contributed by Cavium Inc. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.Ralf Baechle
Some of the were relying into smp.h being dragged in by another header which of course is fragile. <asm/cpu-info.h> uses smp_processor_id() only in macros and including smp.h there leads to an include loop, so don't change cpu-info.h. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24MIPS: bug.h Build fix - include <linux/compiler.h>.Ralf Baechle
In the past this file somehow used to be dragged in. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17Delete pcibios_select_rootMatthew Wilcox
This function was only used by pci_claim_resource(), and the last commit deleted that use. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-06-17MIPS: Add hibernation supportWu Zhangjin
[Ralf: SMP support requires CPU hotplugging which MIPS currently doesn't support. As implemented in this patch cache and tlb flushing will also be invoked with interrupts disabled so smp_call_function() will blow up in charming ways. So limit to !SMP.] Reviewed-by: Pavel Machek <pavel@ucw.cz> Reviewed-by: Yan Hua <yanh@lemote.com> Reviewed-by: Arnaud Patard <apatard@mandriva.com> Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Wu Zhangjin <wuzj@lemote.com> Signed-off-by: Hu Hongbing <huhb@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.hDavid Daney
We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove it to mach-cavium-octeon/cpu-feature-overrides.h Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.David Daney
Some CPUs have implementation dependent rdhwr registers. Allow them to be enabled on a per CPU basis. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Add hugetlbfs page defines.David Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Add support files for hugetlbfs.David Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Cavium-Octeon: Add more chip specific feature tests.David Daney
The octeon-ethernet driver needs to check for additional chip specific features, we add them to the octeon_has_feature() framework. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Cavium-Octeon: Add more board type constants.David Daney
The bootloader now uses additional board type constants. The octeon-ethernet driver needs some of the new values. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Add named alloc functions to OCTEON boot monitor memory allocator.David Daney
The various Octeon ethernet drivers use these new functions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Alchemy: Rewrite GPIO support.Manuel Lauss
The current in-kernel Alchemy GPIO support is far too inflexible for all my use cases. To address this, the following changes are made: * create generic functions which deal with manipulating the on-chip GPIO1/2 blocks. Such functions are universally useful. * Macros for GPIO2 shared interrupt management and block control. * support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros. If CONFIG_GPIOLIB is not enabled, provide linux gpio framework compatibility by directly inlining the GPIO1/2 functions. GPIO access is limited to on-chip ones and they can be accessed as documented in the datasheets (GPIO0-31 and 200-215). If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and one for GPIO2, are registered. GPIOs can still be accessed by using the numberspace established in the databooks. However this is not yet flexible enough for my uses: My Alchemy systems have a documented "external" gpio interface (fixed, different numberspace) and can support a variety of baseboards, some of which are equipped with I2C gpio expanders. I want to be able to provide the default 16 GPIOs of the CPU board numbered as 0..15 and also support gpio expanders, if present, starting as gpio16. To achieve this, a new Kconfig symbol for Alchemy is introduced, CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal that they don't want the Alchemy numberspace exposed to the outside world, but instead want to provide their own. Boards are now respon- sible for providing the linux gpio interface glue code (either in a custom gpio.h header (in board include directory) or with gpio_chips). To make the board-specific inlined gpio functions work, the MIPS Makefile must be changed so that the mach-au1x00/gpio.h header is included _after_ the board headers, by moving the inclusion of the mach-au1x00/ to the end of the header list. See arch/mips/include/asm/mach-au1x00/gpio.h for more info. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Acked-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Alchemy: Remove unused au1000_gpio.h headerManuel Lauss
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: BCM47xx: Fix gpio_direction_outputMatthieu Castet
gpio_direction_output should also set an output value according to the API. Signed-off-by: Matthieu CASTET <castet.matthieu@free.fr> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: ioctl.h: Cleanup.Ralf Baechle
o Rewrite to use <asm-generic/ioctl.h>. Cuts down the file from 40 to 16 lines. o Delete _IOC_VOID, _IOC_OUT, _IOC_IN and _IOC_INOUT. They were added for 2.1.14 but I was not able to find any user - not even historical ones. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: TXx9: Add TX4939 RNG supportAtsushi Nemoto
Add platform support for RNG of TX4939 SoC. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: TXx9: Add SRAMC supportAtsushi Nemoto
Add a sysdev to access SRAM in TXx9 SoCs via sysfs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: RB532: Cleanup cpu-features-overridesFlorian Fainelli
Remove commented out definitions. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Remove execution hazard barriers for Octeon.David Daney
The Octeon has no execution hazards, so we can remove them and save an instruction per TLB handler invocation. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Reviewed by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.David Daney
Some CPUs do not need ehb instructions after writing CP0 registers. By allowing ehb generation to be overridden in cpu-feature-overrides.h, we can save a few instructions in the TLB handler hot paths. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: TXx9: Add ACLC supportAtsushi Nemoto
Add platform support for ACLC of TXx9 SoCs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Add Cavium OCTEON PCI support.David Daney
This patch adds support for PCI and PCIe to the base Cavium OCTEON processor support. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Add register definitions for PCI.David Daney
Here we add the register definitions for the processor blocks used by the following PCI support patch. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: TXx9: Add DMAC supportAtsushi Nemoto
Add platform support for DMAC of TXx9 SoCs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17DMA: TXx9 Soc DMA Controller driverAtsushi Nemoto
This patch adds support for the integrated DMAC of the TXx9 family. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Support 64-byte D-cache line sizeKevin Cernekee
Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Pass struct device to plat_dma_addr_to_phys()Kevin Cernekee
Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>