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path: root/arch/mips/kernel/cpu-probe.c
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2008-01-29[MIPS] Alchemy: Au1210/Au1250 CPU supportManuel Lauss
This patch adds IDs for new Au1200 variants: Au1210 and Au1250. They are essentially identical to the Au1200 except for the Au1210 which has a different SoC-ID in the PRId register [bits 31:24]. The Au1250 is a "Au1200 V0.2". Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15[MIPS] Fix shadow register support.Ralf Baechle
Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add BUG_ON assertion for attempt to run kernel on the wrong CPU type.Franck Bui-Huu
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle
So far /proc/cpuinfo has been the only user but human readable processor name are more useful than that for proc. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add support for BCM47XX CPUs.Aurelien Jarno
Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-09-14[MIPS] 20Kc: Disable use of WAIT instruction.Ralf Baechle
Another issue with 20Kc's WAIT, waiting for more details. With the 2.6.23 release immindent simply disable the use of WAIT instead of a more fancy workaround. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-20[MIPS] Workaround for RM7000 WAIT instruction aka erratum 38Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] PMC MSP71xx mips commonMarc St-Jean
Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] Enable support for the userlocal hardware registerRalf Baechle
Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-06[MIPS] Fix scheduling latency issue on 24K, 34K and 74K coresRalf Baechle
The idle loop goes to sleep using the WAIT instruction if !need_resched(). This has is suffering from from a race condition that if if just after need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but we've just completed the test so go to sleep anyway. This would be trivial to fix by just disabling interrupts during that sequence as in: local_irq_disable(); if (!need_resched()) __asm__("wait"); local_irq_enable(); but the processor architecture leaves it undefined if a processor calling WAIT with interrupts disabled will ever restart its pipeline and indeed some processors have made use of the freedom provided by the architecture definition. This has been resolved and the Config7.WII bit indicates that the use of WAIT is safe on 24K, 24KE and 34K cores. It also is safe on 74K starting revision 2.1.0 so enable the use of WAIT with interrupts disabled for 74K based on a c0_prid of at least that. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-26[MIPS] 20K: Handle WAIT related bugs according to errata informationRalf Baechle
We used to avoid the WAIT entirely on the 20K but really only need to do this on early revs of the 20K. Without this a 20K was a bit of a power hog. Well, in the lower power power hog category ;-) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-20[MIPS] Make some __setup functions staticAtsushi Nemoto
This fixes some sparse warnings. ("warning: symbol 'foo' was not declared. Should it be static?") Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-18[MIPS] Include <asm/bugs> to for declaration of check_bugs32.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06[MIPS] Whitespace cleanups.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30[MIPS] Don't print presence of WAIT instruction on bootup.Ralf Baechle
Not useful and quite a big of noise on bootup of large systems. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-09[MIPS] Fix RM9000 wait instruction detection.Ralf Baechle
Only revisions < 4.0 don't have a functional wait instruction. From Thomas Koeller (Thomas.Koeller@baslerweb.com). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27[MIPS] Reduce race between cpu_wait() and need_resched() checkingAtsushi Nemoto
If a thread became runnable between need_resched() and the WAIT instruction, switching to the thread will delay until a next interrupt. Some CPUs can execute the WAIT instruction with interrupt disabled, so we can get rid of this race on them (at least UP case). Original Patch by Atsushi with fixing up for MIPS Technology's cores by Ralf based on feedback from the RTL designers. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13[MIPS] Save 2k text size in cpu-probeThiemo Seufer
The appended patch drops the inline for decode_configs, this saves about 2k of text size. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13[MIPS] Uses MIPS_CONF_AR instead of magic constants.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30Remove obsolete #include <linux/config.h>Jörn Engel
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-29[MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-06[MIPS] SB1: Only pass1 FPUs are broken beyond recovery.Ralf Baechle
The wrong revision number in the check was forcing a fallback to FPU emulation for all SB1 cores in 2.6. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01[MIPS] Treat R14000 like R10000.Kumba
Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01[MIPS] Fix detection and handling of the 74K processor.Chris Dearman
Nothing exciting; Linux just didn't know it yet so this is most adding a value to a case statement. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21[MIPS] War on whitespace: cleanup initial spaces followed by tabs.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07[MIPS] Get rid of CONFIG_SB1_PASS_1_WORKAROUNDS #ifdef crapola.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10MIPS: Introduce machinery for testing for MIPSxxR1/2.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-12-01[MIPS] R10000 and R12000 need to set MIPS_CPU_4K_CACHE ...Ralf Baechle
... because they have R4000-style caches. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Add support for SB1A CPU.Andrew Isaacson
Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Sibyte fixesAndrew Isaacson
Fix typo in cpu_probe_sibyte. Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Detect 4KSD and treat it like 4KSc.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29R4600 has 32 FPRs.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Detect the MIPS R2 vectored interrupt, external interrupt controllerRalf Baechle
options and the precense of the MT ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29New kernel option nowait allows disabling the use of the wait instruction.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Detect the 34K.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29For MIPS32/MIPS64 cp0.config.mt == 1 implies a standard (R4k-style)Maciej W. Rozycki
TLB, so no need to set it separately for each implementation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Support the MIPS32 / MIPS64 DSP ASE.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-2964-bit fixes for Alchemy code ;)Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29No point in checking cpu_has_tlb before we've computed the CPU options.Ralf Baechle
So for now we just unconditionally set the option - Linux wouldn't work without a TLB anyway. Setting MIPS_CPU_4KTLB was missing for Alchemy and Sandcraft, add that back. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Cleanup decoding of MIPSxx config registers.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix BogoMIPS display on UP and some minor cosmetical things.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Detect the 4KEcR2 and for now detect handle it like the 4KEc.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fixed buglet with previous patch that broke non au1x builds.Pete Popov
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Remove CONFIG_PM dependency from au1x wait in cpu_probe.Pete Popov
Additional work necessary to completely remove that config option. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Base Au1200 2.6 support.Pete Popov
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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