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path: root/arch/mips/kernel/traps.c
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2009-09-17MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assemblerRalf Baechle
This way it doesn't have to use CONFIG_CPU_HAS_LLSC anymore. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.hDavid Daney
We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove it to mach-cavium-octeon/cpu-feature-overrides.h Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.David Daney
Some CPUs have implementation dependent rdhwr registers. Allow them to be enabled on a per CPU basis. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-30MIPS: Use BUG_ON() where possible.Ralf Baechle
Based on original patch by Stoyan Gaydarov <stoyboyker@gmail.com> which missed a few places. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-23MIPS: R2: Fix problem with code that incorrectly modifies ebase.Chris Dearman
Commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e had a change that incorrectly modified ebase. This backs out the lines that modified ebase. In addition, the ebase exception vector is now allocated with correct alignment and the ebase register updated according to the architecture specification. Based on original patch by David VomLehn <dvomlehn@cisco.com>. Signed-off-by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: Read watch registers with interrupts disabled.David Daney
If a context switch occurred between the watch exception and reading the watch registers, it would be possible for the new process to corrupt their state. Enabling interrupts only after the watch registers are read avoids this race. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: R2: Fix broken installation of cache error handler.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state.David Daney
If on Cavium, be aware of cop2 and hwrena during do_cpu(). Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-30MIPS: Switch FPU emulator trap to BREAK instruction.Ralf Baechle
Arguably using the address error handler has always been ugly. But with processors that handle unaligned loads and stores in hardware the current mechanism ceases to work so switch it to a BREAK instruction and allocate break code 514 to the FPU emulator. Yoichi Yuasa provided a build fix for CONFIG_BUG=n. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
2008-10-30MIPS: Consider value of c0_ebase when computing value of exception base.David Daney
It just so happens to be zero on all currently supported systems so this hasn't bitten yet ... [Ralf: Original patch from Cavium; handling of set_uncached_handler() and de-ifdef'ed trap_init() implementation by me.] Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-11MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.David Daney
Here we hook up the watch exception handler so that it sends SIGTRAP when the hardware watch registers are triggered. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-03[MIPS] SMTC: Fix holes in SMTC and FPU affinity support.Kevin D. Kissell
Signed-off-by: Kevin D. Kissell <kevink@paralogos.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-21[MIPS] Fix potential latency problem due to non-atomic cpu_wait.Atsushi Nemoto
If an interrupt happened between checking of NEED_RESCHED and WAIT instruction, adjust EPC to restart from checking of NEED_RESCHED. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-05[MIPS] Fix WARNING: at kernel/smp.c:290Thomas Bogendoerfer
trap_init issues flush_icache_range(), which uses ipi functions to get icache flushing done on all cpus. But this is done before interrupts are enabled and caused WARN_ON messages. This changeset introduces a new local_flush_icache_range() and uses it before interrupts (and additional CPUs) are enabled to avoid this problem. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-05[MIPS] Fix data bus error recoveryThomas Bogendoerfer
With -ffunction-section the entries in __dbe_table aren't no longer sorted, so the lookup of exception addresses in do_be() failed for some addresses. To avoid this we now sort __dbe_table. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-30[MIPS] kgdb: add arch support for the kernel's kgdb coreJason Wessel
The new kgdb architecture specific handler registers and unregisters dynamically for exceptions depending on when you configure a kgdb I/O driver. Aside from initializing the exceptions earlier in the boot process, kgdb should have no impact on a device when it is compiled in so long as an I/O module is not configured for use. There have been quite a number of contributors during the existence of this patch (see arch/mips/kernel/kgdb.c). Most recently Jason re-wrote the mips kgdb logic to use the die notification handlers. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-15[MIPS] Replace use of print_symbol with new %sP pointer format.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-15[MIPS] Remove board_watchpoint_handlerDavid Daney
It is not used anywhere in tree. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-06-05[MIPS] Fix check for valid stack pointer during backtraceThomas Bogendoerfer
The newly added check for valid stack pointer address breaks at least for 64bit kernels. Use __get_user() for accessing stack content to avoid crashes, when doing the backtrace. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28[MIPS] Fix handling of trap and breakpoint instructionsRalf Baechle
With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28[MIPS] Add support for MIPS CMP platform.Ralf Baechle
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28[MIPS] Add noulri kernel argument to disable "rdhwr $29" usermode support.Chris Dearman
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-12[MIPS] Fix loads of section missmatchesRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-12[MIPS] Added missing cases for rdhwr emulationChris Dearman
Some of these are architecturally required for R2 processors so lets try to be bit closer to the real thing. This also provides access to the CPU cycle timer, even on multiprocessors. In that aspect its currently bug compatible to what would happen on a R2-based SMP. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-12-14[MIPS] Ensure that ST0_FR is never set on a 32 bit kernelChris Dearman
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15[MIPS] Fix shadow register support.Ralf Baechle
Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-19Use helpers to obtain task pid in printks (arch code)Alexey Dobriyan
One of the easiest things to isolate is the pid printed in kernel log. There was a patch, that made this for arch-independent code, this one makes so for arch/xxx files. It took some time to cross-compile it, but hopefully these are all the printks in arch code. Signed-off-by: Alexey Dobriyan <adobriyan@openvz.org> Signed-off-by: Pavel Emelyanov <xemul@openvz.org> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-18[MIPS] time: Move R4000 clockevent device code to separate configurable fileRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-17[MIPS] SYNC emulation for MIPS I processorsMaciej W. Rozycki
Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16[MIPS] IP22: Fix warning.Ralf Baechle
CC arch/mips/sgi-ip22/ip22-berr.o arch/mips/sgi-ip22/ip22-berr.c: In function 'ip22_be_interrupt': arch/mips/sgi-ip22/ip22-berr.c:100: warning: passing argument 2 of 'die_if_kernel' discards qualifiers from pointer target type Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle
So far /proc/cpuinfo has been the only user but human readable processor name are more useful than that for proc. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle
This saves a few k on systems which only ever ship with a single CPU type. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Kill useless volatile keywordRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] Maintain si_code field properly for FP exceptionsThiemo Seufer
The appended patch adds code to update siginfo_t's si_code field. It fixes e.g. a floating point overflow regression in the SBCL testsuite. Signed-off-By: Thiemo Seufer <ths@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] SMTC: Fix duplicate status dumps on NMIThiemo Seufer
Also removes the while(1); loop by propagating the ATTRIB_NORET of die() to nmi_exception_handler. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] Fixup secure computing stuff.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-17Report that kernel is tainted if there was an OOPSPavel Emelianov
If the kernel OOPSed or BUGed then it probably should be considered as tainted. Thus, all subsequent OOPSes and SysRq dumps will report the tainted kernel. This saves a lot of time explaining oddities in the calltraces. Signed-off-by: Pavel Emelianov <xemul@openvz.org> Acked-by: Randy Dunlap <randy.dunlap@oracle.com> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> [ Added parisc patch from Matthew Wilson -Linus ] Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-13[MIPS] Make show_code static and add __user tagAtsushi Nemoto
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-13[MIPS] Add some __user tagsAtsushi Nemoto
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-12[MIPS] Sparse: Use NULL for pointerAtsushi Nemoto
This fixes a sparse warning: arch/mips/kernel/traps.c:376:44: warning: Using plain integer as NULL pointer Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] PMC MSP71xx mips commonMarc St-Jean
Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] Enable support for the userlocal hardware registerRalf Baechle
Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] FP affinity: Coding style cleanups Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] Remove unused watchpoint support and arch/mips/lib-{32,64}Atsushi Nemoto
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] Transform old-style macros to newer "__noreturn"Robert P. J. Day
Convert old/obsolete NORET_TYPE and ATTRIB_NORET macros to use the newer standard of "__noreturn" as defined in compiler-gcc.h. Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-06[MIPS] Fix timer/performance interrupt detectionChris Dearman
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-20[MIPS] Don't drag a platform specific header into generic arch code.Ralf Baechle
For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-11[MIPS] SMTC: The MT ASE requires to initialize c0_pagemask and c0_wired.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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