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AgeCommit message (Collapse)Author
2005-10-29Don't copy SB1 cache error handler to uncached memory.Ralf Baechle
This may have made sense on a paranoid day with pass 1 BCM1250 processors that were throwing cache error exception left and right for no good reason. On modern silicion that hardly makes sense and the code had gotten just an obscurity ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix stale comment in c-sb1.c.Andrew Isaacson
Signed-Off-By: Andrew Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Use R4000 TLB routines for SB1 also.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Sync c-tx39.c with c-r4k.c.Atsushi Nemoto
tx39_flush_cache_range() does nothing if !cpu_has_dc_aliases. It should flush d-cache and invalidate i-cache since the TX39(H2) has separate I/D cache. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Minor code cleanup.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29R4600 v2.0 needs a nop before tlbp.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Don't set up a sg dma address if we have no page address for some reason.Thiemo Seufer
Code cleanup. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29More .set push/pop.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Handle mtc0 - tlb write hazard for VR5432.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle
will also avoid smp_call_function from doing stupid things when called from a CPU that is not yet marked online. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle
a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Mark a few variables __read_mostly.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29MIPS R2 instruction hazard handling.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Detect the 34K.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Define kmap_atomic_pfn() for MIPS.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Date: Fri Jul 8 20:10:17 2005 +0000Ralf Baechle
Those literals are long. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Avoid tlbw* hazards for the R4600/R4700/R5000.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Inline ioremap() calls for constant addresses that map to KSEG1.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix the diagnostic dump for the XTLB refill handler.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix a diagnostic message.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Use macros for the RM7k cp0.config bits instead of magic numbers.Maciej W. Rozycki
Minor clean-ups. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Optimize R3k TLB Load/Store/Modified handlers, by schedulingMaciej W. Rozycki
delay slots properly and avoiding an unnecessary jump to a jump. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fill R3k load delay slots properly.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Only dump instructions actually emitted.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Handle _PAGE_DIRTY correctly for CONFIG_64BIT_PHYS_ADDR on 32bit CPUs.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Better interface to run uncached cache setup code.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Arrested for multiple offences of header file inclusion.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix race conditions for read_c0_entryhi. Remove broken ASID masks inThiemo Seufer
tlb-sb1.c. Make tlb-r4k.c and tlb-sb1.c more similiar and more efficient. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Remove useless casts. Fix formatting.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix 64bit SMP TLB handler and stack frame handling, optimize 32bit SMPThiemo Seufer
TLB handlers a bit, match definitions in pgtable-{32,64}.h better. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29R4300 delay slot.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Reformat; cosmetic cleanups.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Export shm_align_mask and flush_data_cache_page.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Gcc 4.0 fixes.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Sparseify MIPS.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Base Au1200 2.6 support.Pete Popov
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix initialization. Unbreak the wait-for-completion loops. Code cleanup.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Switch SiByte drivers back to __raw_*() functions.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Handle addresses beyond VMALLOC_END correctly.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Use intermediate variable.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Moves a test which determines if we actually need to perform aRalf Baechle
cacheflush to the right place. That's a bug which is harmless on UP but a severe bug on SMP. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Update MIPS to use the 4-level pagetable code thereby getting rid ofRalf Baechle
the compacrapability headers. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-2925Kf is also physically indexed.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-2920Kc and SB1 don't suffer from aliases.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Delete duplicate copy of fixrange_init.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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