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2009-12-01MIPS: Loongson: Switch from flatmem to sparsememWu Zhangjin
With flatmem hibernation for Loongson will fail, and there are also some other problems such as broken files when using NFS or CIFS / Samba. The config help of sparsemem says: "This option provides some potential performance benefits, along with decreased code complexity." So to avoid the potential problems of FLATMEM, we disable FLATMEM directly and use SPARSEMEM instead. Related email thread: http://groups.google.com/group/loongson-dev/browse_thread/thread/b6b65890ec2b0f24/feb43e5aa7f55d9b?show_docid=feb43e5aa7f55d9b Reported-by: Tatu Kilappa <tatu.kilappa@gmail.com> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/737/ Cc: linux-mips@linux-mips.org Cc: zhangfx@lemote.com Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-01MIPS: Loongson: Disallow 4kB pagesWu Zhangjin
Currently, with PAGE_SIZE_4KB, the kernel for loongson will hang on: Kernel panic - not syncing: Attempted to kill init! The possible reason is the cache aliases problem: Loongson 2F has 64kb, 4 way L1 Cache, the way size is 16kb, which is bigger then 4kb. so, If using 4kb page size, there is cache aliases problem. To avoid this kind of problem, extra cache flushing. The 2nd possible solution is 16kb page size which avoids cache aliases without the need for extra cache flushes. So we disable 4kB pages until the aliasing issue is solved. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/736/ Cc: linux-mips@linux-mips.org Cc: zhangfx@lemote.com Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-01MIPS: Add missing definition for MADV_HWPOISON.Ralf Baechle
Thanks to Joseph S. Myers for reporting this. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: "Joseph S. Myers" <joseph@codesourcery.com> Patchwork: http://patchwork.linux-mips.org/patch/723/
2009-12-01MIPS: Fix build error if __xchg() is not getting inlined.Ralf Baechle
If __xchg() is not getting inlined the outline version of the function will have a reference to __xchg_called_with_bad_pointer() which does not exist remaining. Fixed by using BUILD_BUG_ON() to check for allowable operand sizes. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/705/
2009-12-01MIPS: IP22/IP28 Disable early printk to fix boot problems on some systems.Martin Michlmayr
Some Debian users have reported that the kernel hangs early during boot on some IP22 systems. Thomas Bogendoerfer found that this is due to a "bad interaction between CONFIG_EARLY_PRINTK and overwritten prom memory during early boot". Since there's no fix yet, disable CONFIG_EARLY_PRINTK for now. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Cc: linux-mips@linux-mips.org Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/702/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-13MIPS: SMTC: Fix lockup in smtc_distribute_timerKevin D. Kissell
1. At the end of smtc_distribute_timer, nextstamp is valid and has already passed so we goto repeat. 2. Nothing updates nextstamp (only updated if the timeout is in the future And we just decided it is in the past) 3. At the end nextstamp still has the same value so it is still valid and in the past. 4. This repeats until read_c0_count has a value which causes nextstamp to be in the future. Reported and initial patch and testing by Mikael Starvik <mikael.starvik@axis.com>. Signed-off-by: Kevin D. Kissell <kevink@paralogos.com> Cc: Mikael Starvik <mikael.starvik@axis.com> Cc: linux-mips@linux-mips.org Cc: Jesper Nilsson <Jesper.Nilsson@axis.com> Patchwork: http://patchwork.linux-mips.org/patch/621/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-13MIPS: TXx9: Update rbtx49xx_defconfigAtsushi Nemoto
Enable following features: * MTD (RBTX4939, NAND_TXX9NDFMC) * HW_RANDOM (HW_RANDOM_TX4939) * SOUND (SND_SOC_TXX9ACLC) * DMADEVICE (TXX9_DMAC) Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-13MIPS: Make local arrays with CL_SIZE static __initdataAtsushi Nemoto
Since commit 22242681cff52bfb7cba5d2a37b91802be7a4e4c ("MIPS: Extend COMMAND_LINE_SIZE"), CL_SIZE is 4096 and local array variables with this size will cause an build failure with default CONFIG_FRAME_WARN settings. Although current users of such array variables are all early bootstrap code and not likely to cause real stack overflow (thread_info corruption), it is preferable to to declare these arrays static with __initdata. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-13MIPS: Add DMA declare coherent memory supportYoichi Yuasa
The ohci-sm501 driver requires dma_declare_coherent_memory(). It is used by the driver's local memory allocation with dma_alloc_coherent(). Tested on TANBAC TB0287(VR4131 + SM501). [Ralf: Fixed reject in dma-default.c and removed the entire #if 0'ed block in dma-mapping.h instead of just the #if 0.] Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-13MIPS: Fix emulation of 64-bit FPU on FPU-less 64-bit CPUs.David Daney
Running a 64-bit kernel on a 64-bit CPU without an FPU would cause the emulator to run in 32-bit mode. The c0_Status.FR bit is wired to zero on systems without an FPU, so using that bit to decide how the emulator behaves doesn't allow for proper emulation on 64-bit FPU-less processors. Instead, we need to select the emulator mode based on the user-space ABI. Since the thread flag TIF_32BIT_REGS is used to set c0_Status.FR, we can just use it to decide if the emulator should be in 32-bit or 64-bit mode. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: O32: Fix ppollArnaud Patard
sys_ppoll syscall needs to use a compat handler on 64bit kernels with o32 user-space. Signed-off-by: Arnaud Patard <apatard@mandriva.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Oprofile: Rename cpu_type from godson2 to loongson2Wu Zhangjin
Unify the naming method between kernel and the user-space oprofile tool. Because loongson is used instead of godson in most of the places, we agreed to use loongson instead, which will simplify future maintenance. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Alchemy: Fix hang with high-frequency edge interruptsManuel Lauss
The handle_edge_irq() flowhandler disables edge int sources which occur too fast (i.e. another edge comes in before the irq handler function had a chance to finish). Currently, the mask_ack() callback does not ack the edges in hardware, leading to an endless loop in the flowhandler where it tries to shut up the irq source. When I rewrote the alchemy IRQ code I wrongly assumed the mask_ack() callback was only used by the level flowhandler, hence it omitted the (at the time pointless) edge acks. Turned out I was wrong; so here is a complete mask_ack implementation for Alchemy IC, which fixes the above mentioned problem. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: TXx9: Fix spi-baseclk valueAtsushi Nemoto
TXx9 SPI bit rate is calculated by: fBR = fSPI / 2 / (n + 1) (fSPI is SPI master clock freq, i.e. imbusclk freq.) So use imbus_clk / 2 as a spi-baseclk. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: bcm63xx: Set the correct BCM3302 CPU nameFlorian Fainelli
For consistency with other BCM63xx SoC set the CPU name to "Broadcom BCM6338" when actually running on that system. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_storeZhang Le
Loongson 2 does not have dcache aliases when is using 16k pages. and the And because Loongson 2 doesn't do SMP , cpu_icache_snoops_remote_store does not matter here. Signed-off-by: Zhang Le <r0bertz@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Avoid potential hazard on Context registerRalf Baechle
set_saved_sp reads Context register. Avoid reading stale value from earlier incomplete write. Issue found and fixed for head.S by Chris Dearman <chris@mips.com>. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Octeon: Use lockless interrupt controller operations when possible.David Daney
Some newer Octeon chips have registers that allow lockless operation of the interrupt controller. Take advantage of them. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinityDavid Daney
Since the locks are used from interrupt context we need the irqsave/irqrestore versions of the locking functions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Set S-cache linesize to 64-bytes for MTI's S-cacheRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: SMTC: Avoid queing multiple reschedule IPIsJaidev Patwardhan
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: GCMP: Avoid accessing registers when they are not presentJaidev Patwardhan
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: GIC: Random fixes and enhancements.Chris Dearman
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_startChris Dearman
Signed-off-by: Chris Dearman (chris@mips.com) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operandsNigel Stephens
This patch ensures that the sign bit is always updated for NaN operands. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: SPRAM: Clean up support code a littleChris Dearman
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: 1004K: Enable SPRAM support.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4Ralf Baechle
Based on original patch by Chris Dearman <chris@mips.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: MTI: Fix accesses to device registers on MIPS boardsChris Dearman
This fixes the remaining problems introduced by f197465384bf7ef1af184c2ed1a4e268911a91e3 (incorrect access length & byteswapping in bigendian mode) Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Fix machine check exception in kmap_coherent()Kevin Cernekee
On an SMP system with cache aliases, the following sequence of events may happen: 1) copy_user_highpage() runs on CPU0, invoking kmap_coherent() to create a temporary mapping in the fixmap region 2) copy_page() starts on CPU0 3) CPU1 sends CPU0 an IPI asking CPU0 to run local_r4k_flush_cache_page() 4) CPU0 takes the interrupt, interrupting copy_page() 5) local_r4k_flush_cache_page() on CPU0 calls kmap_coherent() again 6) The second invocation of kmap_coherent() on CPU0 tries to use the same fixmap virtual address that was being used by copy_user_highpage() 7) CPU0 throws a machine check exception for the TLB address conflict Fixed by creating an extra set of fixmap entries for use in interrupt handlers. This prevents fixmap VA conflicts between copy_user_highpage() running in user context, and local_r4k_flush_cache_page() invoked from an SMP IPI. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: MTX-1: Fix build if CONFIG_PCI is disabled.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: AR7: register watchdog device only if enabled in hw configurationFlorian Fainelli
This patch checks if the watchdog enable bit is set in the DCL register meaning that the hardware watchdog actually works and if so, register the ar7_wdt platform_device. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: BCM63xx: Prepare for watchdog supportFlorian Fainelli
This patch prepares the board code to register a bcm63xx_wdt platform_device that we are going to use in a subsequent patch. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: BCM63xx: Make bcm63xx_uart_register an initfuncFlorian Fainelli
This patch removes the calls to bcm63xx_uart_register in board_bcm963xx.c and make bcm63xx_uart_register an initfunc. Allows us to remove bcm63xx_dev_uart.h which was there to make checkpatch.pl happy. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: AU1000: Fix build failure for db1x00 configured for Au1100 SoCFlorian Fainelli
This patch fixes the following warning, which becomes an error due to -Werror to be turned on: CC arch/mips/alchemy/common/gpiolib-au1000.o cc1: warnings being treated as errors arch/mips/alchemy/common/gpiolib-au1000.c: In function 'au1100_gpio2_to_irq': /home/florian/dev/kernel/linux-queue/arch/mips/include/asm/mach-au1x00/gpio-au1000.h:107: warning: control reaches end of non-void function Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: BCM63xx: Fix soft-reset lockup on BCM6345Florian Fainelli
This patch fixes a lockup on BCM6345 where setting the PLL soft reset bit will also lock the other blocks including UART. Instead of setting only the PLL soft reset bit in the software reset register, set this bit but do not touch the others. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: TXx9: Fix error handling / Fix for noenexisting gpio_remove.Ralf Roesch
Error was introduced by commit 0385d1f3d394c6814be0b165c153fc3fc254469a. Signed-off-by: Ralf Roesch <ralf.roesch@rw-gmbh.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Add IRQF_TIMER flag for timer interruptsWu Zhangjin
As the commit 3ee4c147 shows, we need to "Add IRQF_TIMER flag for timer interrupts", Atsushi Nemoto have reported that some other timer interrupts should be considered, Here it is. Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: 64-bit: Fix o32 lookup_dcookie syscallWu Zhangjin
An o32 aplication passes a 64-bit value in a pair of registers; a 64-bit kernel expects a 64-bit argument in a single register. Signed-off-by: Chen Jie <chenj@lemote.com> Signed-off-by: Hu Hongbing <huhb@lemote.com> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: VPE: Remove stray unlock_kernel.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Josip Rodin <joy@entuzijast.net>
2009-11-02MIPS: Add IRQF_TIMER flag for timer interruptsWu Zhangjin
Along the lines of d6c585a4342a2ff627a29f9aea77c5ed4cd76023, add IRQF_TIMER flag for all timer interrupts This ensures that timer interrupts won't be disabled on suspend and not threaded for PREEMPT_RT. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Loongson: Remove redundant local_irq_disable()Wu Zhangjin
That code is executed with irq disabled already, so, remove the redundant local_irq_disable() here. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: IP27: Fix buildRalf Baechle
Broken by 182a85f8a119c789610a9d464f4129ded9f3c107. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Cleanup CONFIG_DEBUG_STACK_USAGE version of alloc_thread_info.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Octeon: Fix compile error in arch/mips/cavium-octeon/smp.cDavid Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Don't write ones to reserved entryhi bits.Ralf Baechle
We've silently been relying on the hardware chopping off excess, reserved ASID bits for no better reason that it saving an instruction. Because we already have: #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) in <asm/mmu_context.h>. We can use a cleanup to avoid writing non-zero bits into the reserved entryhi bits. This avoid triggering some debugging assertion in the Cavium simulator. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Extend COMMAND_LINE_SIZERalf Baechle
Some firmware may pass well over 256 bytes these days. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-30MIPS: Avoid spurious make includecheck messageRalf Baechle
arch/mips/include/asm/unaligned.h: linux/unaligned/generic.h is included more than once. Entirely legitimate but just noise. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-30MIPS: VPE: Get rid of BKL.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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