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path: root/arch/sparc/kernel/perf_counter.c
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2009-09-10sparc64: Initial niagara2 perf counter support.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-09-10sparc64: Perf counter 'nop' event is not constant.David S. Miller
On Niagara-2, for example, it's going to be different. So make it something specified in sparc_pmu. Signed-off-by: David S. Miller <davem@davemloft.net>
2009-09-10sparc64: Provide a way to specify a perf counter overflow IRQ enable bit.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-09-10sparc64: Provide hypervisor tracing bit support for perf counters.David S. Miller
A PMU need only specify which bit in the PCR enabled hypervisor tracing in order to enable this. This will be used in Niagara-2 perf counter support. Signed-off-by: David S. Miller <davem@davemloft.net>
2009-09-10sparc64: Initial hw perf counter support.David S. Miller
Only supports one simple counter and only UltraSPARC-IIIi chips. Signed-off-by: David S. Miller <davem@davemloft.net>
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