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path: root/arch/x86/mm/pageattr_64.c
AgeCommit message (Expand)Author
2008-01-30x86: c_p_a() make it more robust against use of PAT bitsAndi Kleen
2008-01-30x86: c_p_a() fix: reorder TLB / cache flushes to follow Intel recommendationAndi Kleen
2008-01-30x86: cpa: remove unnecessary masking of addressAndi Kleen
2008-01-30x86: cpa: use wbinvd() macro instead of inline assembly in 64bit c_p_a()Andi Kleen
2008-01-30x86: return the page table level in lookup_address()Ingo Molnar
2008-01-30x86: clean up arch/x86/mm/pageattr_64.cIngo Molnar
2007-10-22Intel IOMMU: clflush_cache_range now takes size paramKeshavamurthy, Anil S
2007-10-19x86: fix global_flush_tlb() bugIngo Molnar
2007-10-17x86: Create clflush() inline, remove hardcoded wbinvdH. Peter Anvin
2007-10-17x86: NX bit handling in change_page_attr()Huang, Ying
2007-10-11x86_64: move mmThomas Gleixner