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2006-03-20[SPARC64]: Fix too early reference to %g6David S. Miller
%g6 is not necessarily set to current_thread_info() at sparc64_realfault_common. So store the fault code and address after we invoke etrap and %g6 is properly set up. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Kill hard-coded %pstate setting in sparc_exit.David S. Miller
Just flip the bit off of whatever it's currently set to. PSTATE_IE is guarenteed to be enabled when we get here. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Increase swapper_tsb size to 32K.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Kill sole argument passed to setup_tba().David S. Miller
No longer used, and move extern declaration to a header file. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Kill PROM locked TLB entry preservation code.David S. Miller
It is totally unnecessary complexity. After we take over the trap table, we handle all PROM tlb misses fully. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Use sparc64_highest_unlocked_tlb_ent in __tsb_context_switch()David S. Miller
Instead of ugly hard-coded value. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix bogus flush instruction usage.David S. Miller
Some of the trap code was still assuming that alternate global %g6 was hard coded with current_thread_info(). Let's just consistently flush at KERNBASE when we need a pipeline synchronization. That's locked into the TLB and will always work. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix incorrect TSB lock bit handling.David S. Miller
The TSB_LOCK_BIT define is actually a special value shifted down by 32-bits for the assembler code macros. In C code, this isn't what we want. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Kill {save,restore}_alternate_globals()David S. Miller
No longer needed now that we no longer have hard-coded alternate global register usage. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Preload TSB entries from update_mmu_cache().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Dynamically grow TSB in response to RSS growth.David S. Miller
As the RSS grows, grow the TSB in order to reduce the likelyhood of hash collisions and thus poor hit rates in the TSB. This definitely needs some serious tuning. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Add infrastructure for dynamic TSB sizing.David S. Miller
This also cleans up tsb_context_switch(). The assembler routine is now __tsb_context_switch() and the former is an inline function that picks out the bits from the mm_struct and passes it into the assembler code as arguments. setup_tsb_parms() computes the locked TLB entry to map the TSB. Later when we support using the physical address quad load instructions of Cheetah+ and later, we'll simply use the physical address for the TSB register value and set the map virtual and PTE both to zero. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: TSB refinements.David S. Miller
Move {init_new,destroy}_context() out of line. Do not put huge pages into the TSB, only base page size translations. There are some clever things we could do here, but for now let's be correct instead of fancy. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Elminate all usage of hard-coded trap globals.David S. Miller
UltraSPARC has special sets of global registers which are switched to for certain trap types. There is one set for MMU related traps, one set of Interrupt Vector processing, and another set (called the Alternate globals) for all other trap types. For what seems like forever we've hard coded the values in some of these trap registers. Some examples include: 1) Interrupt Vector global %g6 holds current processors interrupt work struct where received interrupts are managed for IRQ handler dispatch. 2) MMU global %g7 holds the base of the page tables of the currently active address space. 3) Alternate global %g6 held the current_thread_info() value. Such hardcoding has resulted in some serious issues in many areas. There are some code sequences where having another register available would help clean up the implementation. Taking traps such as cross-calls from the OBP firmware requires some trick code sequences wherein we have to save away and restore all of the special sets of global registers when we enter/exit OBP. We were also using the IMMU TSB register on SMP to hold the per-cpu area base address, which doesn't work any longer now that we actually use the TSB facility of the cpu. The implementation is pretty straight forward. One tricky bit is getting the current processor ID as that is different on different cpu variants. We use a stub with a fancy calling convention which we patch at boot time. The calling convention is that the stub is branched to and the (PC - 4) to return to is in register %g1. The cpu number is left in %g6. This stub can be invoked by using the __GET_CPUID macro. We use an array of per-cpu trap state to store the current thread and physical address of the current address space's page tables. The TRAP_LOAD_THREAD_REG loads %g6 with the current thread from this table, it uses __GET_CPUID and also clobbers %g1. TRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load the current processor's IRQ software state into %g6. It also uses __GET_CPUID and clobbers %g1. Finally, TRAP_LOAD_PGD_PHYS loads the physical address base of the current address space's page tables into %g7, it clobbers %g1 and uses __GET_CPUID. Many refinements are possible, as well as some tuning, with this stuff in place. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Kill pgtable quicklists and use SLAB.David S. Miller
Taking a nod from the powerpc port. With the per-cpu caching of both the page allocator and SLAB, the pgtable quicklist scheme becomes relatively silly and primitive. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: No need to D-cache color page tables any longer.David S. Miller
Unlike the virtual page tables, the new TSB scheme does not require this ugly hack. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Move away from virtual page tables, part 1.David S. Miller
We now use the TSB hardware assist features of the UltraSPARC MMUs. SMP is currently knowingly broken, we need to find another place to store the per-cpu base pointers. We hid them away in the TSB base register, and that obviously will not work any more :-) Another known broken case is non-8KB base page size. Also noticed that flush_tlb_all() is not referenced anywhere, only the internal __flush_tlb_all() (local cpu only) is used by the sparc64 port, so we can get rid of flush_tlb_all(). The kernel gets it's own 8KB TSB (swapper_tsb) and each address space gets it's own private 8K TSB. Later we can add code to dynamically increase the size of per-process TSB as the RSS grows. An 8KB TSB is good enough for up to about a 4MB RSS, after which the TSB starts to incur many capacity and conflict misses. We even accumulate OBP translations into the kernel TSB. Another area for refinement is large page size support. We could use a secondary address space TSB to handle those. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC]: BUG_ON() Conversion in arch/sparc/kernel/ioport.cEric Sesterhenn
this changes if() BUG(); constructs to BUG_ON() which is cleaner and can better optimized away Signed-off-by: Eric Sesterhenn <snakebyte@gmx.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: fix sparc_floppy_irq's auxio_register resetingBernhard R Link
The patch "[SPARC64]: Get rid of fast IRQ feature" moved the the code from arch/sparc64/kernel/entry.S: lduba [%g7] ASI_PHYS_BYPASS_EC_E, %g5 or %g5, AUXIO_AUX1_FTCNT, %g5 stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E andn %g5, AUXIO_AUX1_FTCNT, %g5 stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E to arch/sparc64/kernel/irq.c: val = readb(auxio_register); val |= AUXIO_AUX1_FTCNT; writeb(val, auxio_register); val &= AUXIO_AUX1_FTCNT; writeb(val, auxio_register); This looks like it it missing a bitwise not, which is reintroduced by this patch. Due to lack of a floppy device, I could not test it, but it looks evident. Signed-off-by: Bernhard R Link <brlink@debian.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-18[MIPS] SB1: Check for -mno-sched-prolog if building corelis debug kernel.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18[MIPS] Sibyte: Fix race in sb1250_gettimeoffset().Ralf Baechle
From Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>: sb1250_gettimeoffset() simply reads the current cpu 0 timer remaining value, however once this counter reaches 0 and the interrupt is raised, it immediately resets and begins to count down again. If sb1250_gettimeoffset() is called on cpu 1 via do_gettimeofday() after the timer has reset but prior to cpu 0 processing the interrupt and taking write_seqlock() in timer_interrupt() it will return a full value (or close to it) causing time to jump backwards 1ms. Once cpu 0 handles the interrupt and timer_interrupt() gets far enough along it will jump forward 1ms. Fix this problem by implementing mips_hpt_*() on sb1250 using a spare timer unrelated to the existing periodic interrupt timers. It runs at 1Mhz with a full 23bit counter. This eliminated the custom do_gettimeoffset() for sb1250 and allowed use of the generic fixed_rate_gettimeoffset() using mips_hpt_*() and timerhi/timerlo. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18[MIPS] Sibyte: Fix interrupt timer off by one bug.Ralf Baechle
From Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>: The timers need to be loaded with 1 less than the desired interval not the interval itself. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18[MIPS] Protect more of timer_interrupt() by xtime_lock.Ralf Baechle
From Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>: * do_timer() expects the arch-specific handler to take the lock as it modifies jiffies[_64] and xtime. * writing timerhi/lo in timer_interrupt() will mess up fixed_rate_gettimeoffset() which reads timerhi/lo. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18[MIPS] Simple patch to power off DBAU1200Matej Kupljen
Signed-off-by: Matej Kupljen <matej.kupljen@ultra.si> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18[MIPS] Fix DBAu1550 software power off.Sergei Shtylylov
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18[MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto
If dcache_size != icache_size or dcache_size != scache_size, or set-associative cache, icache/scache does not flushed properly. Make blast_?cache_page_indexed() masks its index value correctly. Also, use physical address for physically indexed pcache/scache. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18[MIPS] Get rid of the IP22-specific code in arclib.Ralf Baechle
This breaks the kernel build if sgiwd93 was configured as a module. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-17[PATCH] x86: check for online cpus before bringing them upSrivatsa Vaddagiri
Bryce reported a bug wherein offlining CPU0 (on x86 box) and then subsequently onlining it resulted in a lockup. On x86, CPU0 is never offlined. The subsequent attempt to online CPU0 doesn't take that into account. It actually tries to bootup the already booted CPU. Following patch fixes the problem (as acknowledged by Bryce). Please consider for inclusion in 2.6.16. Check if cpu is already online. Signed-off-by: Srivatsa Vaddagiri <vatsa@in.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-16Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc-mergeLinus Torvalds
* git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc-merge: powerpc: update defconfigs [PATCH] powerpc: properly configure DDR/P5IOC children devs [PATCH] powerpc: remove duplicate EXPORT_SYMBOLS [PATCH] powerpc: RTC memory corruption [PATCH] powerpc: enable NAP only on cpus who support it to avoid memory corruption [PATCH] powerpc: Clarify wording for CRASH_DUMP Kconfig option [PATCH] powerpc/64: enable CONFIG_BLK_DEV_SL82C105 [PATCH] powerpc: correct cacheflush loop in zImage powerpc: Fix problem with time going backwards powerpc: Disallow lparcfg being a module
2006-03-16powerpc: update defconfigsPaul Mackerras
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-16[PATCH] powerpc: properly configure DDR/P5IOC children devsJohn Rose
The dynamic add path for PCI Host Bridges can fail to configure children adapters under P5IOC controllers. It fails to properly fixup bus/device resources, and it fails to properly enable EEH. Both of these steps need to occur before any children devices are enabled in pci_bus_add_devices(). Signed-off-by: John Rose <johnrose@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-16[PATCH] powerpc: remove duplicate EXPORT_SYMBOLSOlaf Hering
remove warnings when building a 64bit kernel. smp_call_function triggers also with 32bit kernel. WARNING: vmlinux: duplicate symbol 'smp_call_function' previous definition was in vmlinux arch/powerpc/kernel/ppc_ksyms.c:164:EXPORT_SYMBOL(smp_call_function); arch/powerpc/kernel/smp.c:300:EXPORT_SYMBOL(smp_call_function); WARNING: vmlinux: duplicate symbol 'ioremap' previous definition was in vmlinux arch/powerpc/kernel/ppc_ksyms.c:113:EXPORT_SYMBOL(ioremap); arch/powerpc/mm/pgtable_64.c:321:EXPORT_SYMBOL(ioremap); WARNING: vmlinux: duplicate symbol '__ioremap' previous definition was in vmlinux arch/powerpc/kernel/ppc_ksyms.c:117:EXPORT_SYMBOL(__ioremap); arch/powerpc/mm/pgtable_64.c:322:EXPORT_SYMBOL(__ioremap); WARNING: vmlinux: duplicate symbol 'iounmap' previous definition was in vmlinux arch/powerpc/kernel/ppc_ksyms.c:118:EXPORT_SYMBOL(iounmap); arch/powerpc/mm/pgtable_64.c:323:EXPORT_SYMBOL(iounmap); Signed-off-by: Olaf Hering <olh@suse.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-16[PATCH] powerpc: RTC memory corruptionMichael Neuling
We should be memset'ing the data we are pointing to, not the pointer itself. This is in an error path so we probably don't hit it much. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-16[PATCH] powerpc: enable NAP only on cpus who support it to avoid memory ↵Benjamin Herrenschmidt
corruption This patch fixes incorrect setting of powersave_nap to 1 on all PowerMacs, potentially causing memory corruption on some models. This bug was introuced by me during the 32/64 bits merge. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-16[PATCH] powerpc: Clarify wording for CRASH_DUMP Kconfig optionMichael Ellerman
The wording of the CRASH_DUMP Kconfig option is not very clear. It gives you a kernel that can be used _as_ the kdump kernel, not a kernel that can boot into a kdump kernel. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-16[PATCH] powerpc/64: enable CONFIG_BLK_DEV_SL82C105Olaf Hering
Enable the onboard IDE driver for p610, p615 and p630. They have the CD connected to this card. All other RS/6000 systems with this controller have no connectors and dont need this option. Signed-off-by: Olaf Hering <olh@suse.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-16[PATCH] powerpc: correct cacheflush loop in zImageOlaf Hering
Correct the loop for cacheflush. No idea where I copied the code from, but the original does not work correct. Maybe the flush is not needed. Signed-off-by: Olaf Hering <olh@suse.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-16powerpc: Fix problem with time going backwardsPaul Mackerras
The recent changes to keep gettimeofday in sync with xtime had the side effect that it was occasionally possible for the time reported by gettimeofday to go back by a microsecond. There were two reasons: (1) when we recalculated the offsets used by gettimeofday every 2^31 timebase ticks, we lost an accumulated fractional microsecond, and (2) because the update is done some time after the notional start of jiffy, if ntp is slowing the clock, it is possible to see time go backwards when the timebase factor gets reduced. This fixes it by (a) slowing the gettimeofday clock by about 1us in 2^31 timebase ticks (a factor of less than 1 in 3.7 million), and (b) adjusting the timebase offsets in the rare case that the gettimeofday result could possibly go backwards (i.e. when ntp is slowing the clock and the timer interrupt is late). In this case the adjustment will reduce to zero eventually because of (a). Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-15[ARM] 3362/1: [cleanup] - duplicate decleration of mem_fclk_21285Ben Dooks
Patch from Ben Dooks arch/arm/kernel/setup.c declares mem_fclk_21285 when this is already declared in include/asm-arm/system.h Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-15[ARM] 3365/1: [cleanup] header for compat.c exported functionsBen Dooks
Patch from Ben Dooks arch/arm/kernel/compat.c exports two functions, convert_to_tag_list and squash_mem_tags which are not defined in any header files, and not used outside arch/arm/kernel. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-15[ARM] 3363/1: [cleanup] process.c - fix warningsBen Dooks
Patch from Ben Dooks Fix the following warnings from sparse: arch/arm/kernel/process.c:86:6: warning: symbol 'default_idle' was not declared. Should it be static? arch/arm/kernel/process.c:378:5: warning: symbol 'dump_fpu' was not declared. Should it be static? Include <linux/elfcore.h> for dump_fpu() decleration, and make default_idle() static as it is not used outside the file. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-15[ARM] 3358/1: [S3C2410] add missing SPI DMA resourcesAlbrecht Dreß
Patch from Albrecht Dreß Add DMA resources to s3c2410 spi platform devices - dma_(alloc|free)_coherent should now work as expected. Signed-off-by: Albrecht Dreß <albrecht.dress@lios-tech.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-15[ARM] 3357/1: enable frontlight on colliePavel Machek
Patch from Pavel Machek Enable frontlight during collie bootup, so that display is actually readable in anything other than bright sunlight. Signed-off-by: Pavel Machek <pavel@suse.cz> Signed-off-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-15[ARM] Fix "thead" typoRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-14[PATCH] Plug kdump shutdown race windowManeesh Soni
lapic_shutdown() re-enables interrupts which is un-desirable for panic case, so use local_irq_save() and local_irq_restore() to keep the irqs disabled for kexec on panic case, and close a possible race window while kdump shutdown as shown in this stack trace -- BUG: spinlock lockup on CPU#1, bash/4396, c52781a0 [<c01c1870>] _raw_spin_lock+0xb7/0xd2 [<c029e148>] _spin_lock+0x6/0x8 [<c011b33f>] scheduler_tick+0xe7/0x328 [<c0128a7c>] update_process_times+0x51/0x5d [<c0114592>] smp_apic_timer_interrupt+0x4f/0x58 [<c01141ff>] lapic_shutdown+0x76/0x7e [<c0104d7c>] apic_timer_interrupt+0x1c/0x30 [<c01141ff>] lapic_shutdown+0x76/0x7e [<c0116659>] machine_crash_shutdown+0x83/0xaa [<c013cc36>] crash_kexec+0xc1/0xe3 [<c029e148>] _spin_lock+0x6/0x8 [<c013cc22>] crash_kexec+0xad/0xe3 [<c0215280>] __handle_sysrq+0x84/0xfd [<c018d937>] write_sysrq_trigger+0x2c/0x35 [<c015e47b>] vfs_write+0xa2/0x13b [<c015ea73>] sys_write+0x3b/0x64 [<c0103c69>] syscall_call+0x7/0xb Signed-off-by: Maneesh Soni <maneesh@in.ibm.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-14Revert "[PATCH] x86-64: Fix up handling of non canonical user RIPs"Linus Torvalds
This reverts commit c33d4568aca9028a22857f94f5e0850012b6444b. Andrew Clayton and Hugh Dickins report that it's broken for them and causes strange page table and slab corruption, and spontaneous reboots. Let's get it right next time. Cc: Andrew Clayton <andrew@rootshell.co.uk> Cc: Hugh Dickins <hugh@veritas.com> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-14powerpc: Disallow lparcfg being a modulePaul Mackerras
The lparcfg code needs several things which are pretty arcane internal details and which we don't want to export, which means that lparcfg doesn't work when built as a module. This makes it a bool instead of a tristate in the Kconfig so that users can't try to build it as a module. Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-12[PATCH] x86-64: Fix up handling of non canonical user RIPsAndi Kleen
EM64T CPUs have somewhat weird error reporting for non canonical RIPs in SYSRET. We can't handle any exceptions there because the exception handler would end up running on the user stack which is unsafe. To avoid problems any code that might end up with a user touched pt_regs should return using int_ret_from_syscall. int_ret_from_syscall ends up using IRET, which allows safe exceptions. Cc: Ernie Petrides <petrides@redhat.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-12Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] iwmmxt thread state alignment [ARM] 3350/1: Enable 1-wire on ARM [ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problem [ARM] 3355/1: NSLU2: remove propmt depends [ARM] 3354/1: NAS100d: fix power led handling [ARM] Fix muldi3.S
2006-03-12[ARM] iwmmxt thread state alignmentRussell King
This patch removes the reliance of iwmmxt on hand coded alignments. Since thread_info is always 8K aligned, specifying that fpstate is 8-byte aligned achieves the same effect without needing to resort to hand coded alignments. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>