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2005-04-30[PATCH] kbuild/ppc: tell when uimage was not builtSam Ravnborg
Tom Rini said: Note that there is still a trivial'ish change to make. When mkimage doesn't exist on the host we should say "uImage not made" or something similar. So I did like Tom asked. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-30[PATCH] kbuild/i386: re-introduce dependency on vmlinux for install target, ↵Sam Ravnborg
and add kernel_install Removing the dependency on vmlinux for the install target raised a few complaints, so instead a new target i added: kernel_install. kernel_install will install the kernel just like the ordinary install target. The only difference is that install has a dependency on vmlinux, kernel_install does not. Therefore kernel_install is the best choice when accessing the kernel over a NFS mount or as another user. kernel_install is similar to modules_install in the fact that neither does a full kernel compile before performing the install. In this way they are good for root use. Also added back the dependency on vmlinux for the install target so peoples scripts are no longer broken. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-30Merge of master.kernel.org:/home/rmk/linux-2.6-rmk.gitLinus Torvalds
2005-04-30[PATCH] ARM: IntegratorCP: Fix CLCD MUX selection valuesRussell King
The documentation on these values seems to be rather wrong. These values have been determined by mere trial and error. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-30Merge of master.kernel.org:/home/rmk/linux-2.6-rmk.gitLinus Torvalds
2005-04-30[PATCH] ppc64: fix 32-bit signal frame back linkPaul Mackerras
When the kernel creates a signal frame on the user stack, it puts the old stack pointer value at the beginning so that the signal frame is linked into the chain of stack frames like any other frame. Unfortunately, for 32-bit processes we are writing the old stack pointer as a 64-bit value rather than a 32-bit value, and the process sees that as a null pointer, since it only looks at the first 32 bits, which are zero since ppc is bigendian and the stack pointer is below 4GB. This bug is in SLES9 and RHEL4 too, hence the ccs. This patch fixes the bug by making the signal code write the old stack pointer as a u32 instead of an unsigned long. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-30[PATCH] ARM: PXA I2C: add platform deviceRussell King
Add the PXA I2C platform device. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-30[PATCH] ARM: RTC: allow driver methods to return errorRussell King
Allow RTC drivers to return error codes from their read_time or read_alarm methods. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-29Merge of master.kernel.org:/home/rmk/linux-2.6-rmk.gitLinus Torvalds
2005-04-29[PATCH] ARM: 2660/2: fix ixdp2800 boot and pci initLennert Buytenhek
Patch from Lennert Buytenhek The IXDP2800 is an evalution platform for the IXP2800 processor that has two IXP2800s connected to the same PCI bus. This is problematic as both CPUs will try to configure the PCI bus as they boot linux. Contrary to on the other IXP2000 platforms, the boot loader on the IXDP2800 doesn't configure the PCI bus properly, so we do want the linux instance on one of the CPUs to do that. Making one of the CPUs ignore the PCI bus (and thus act like a pure PCI slave device) is not an option because there is a 82559 NIC on the PCI bus for each of the CPUs. The chosen solution is to have the master CPU configure the PCI bus while the slave is kept in a quiescent state, and then to have the slave CPU scan the PCI bus (without assigning resources) while the master is kept in a quiescent state. After this ritual, the master deletes the slave NIC from its PCI device list, the slave deletes the master NIC from its device list, and (almost) all is well. There's still one little problem: each of the CPUs has a 1G SDRAM BAR, but the IXP2000 only has 512M of outbound PCI memory window. We solve this by hand-assigning the master and slave SDRAM BARs to a location outside each of the IXP's outbound PCI windows, and by having the rest of the BARs autoconfigured in the outbound PCI windows, in the range [e0000000..ffffffff], so that there is a 1:1 pci:phys mapping between them. Even with this patch, a number of issues still remain -- just imagine what happens if one of the CPUs is rebooted, by watchdog or by hand, but the other one isn't. But those issues are not easily fixable given the strange PCI layout of this board and the behavior of the boot loader shipped with the platform. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29[PATCH] ARM: 2656/1: Access permission bits are wrong for kernel XIP ↵George G. Davis
sections on ARMv6 Patch from George G. Davis This patch is required for kernel XIP support on ARMv6 machines. It ensures that the access permission bits for kernel XIP section descriptors are APX=1 and AP[1:0]=01, which is Kernel read-only/User no access permissions. Prior to this change, kernel XIP section descriptor access permissions were set to Kernel no access/User no access on ARMv6 machines and the kernel would therefore hang upon entry to userspace when set_fs(USER_DS) was executed. Signed-off-by: Steve Longerbeam Signed-off-by: George G. Davis Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29[PATCH] ARM: 2651/3: kernel helpers for NPTL supportNicolas Pitre
Patch from Nicolas Pitre This patch entirely reworks the kernel assistance for NPTL on ARM. In particular this provides an efficient way to retrieve the TLS value and perform atomic operations without any instruction emulation nor special system call. This even allows for pre ARMv6 binaries to be forward compatible with SMP systems without any penalty. The problematic and performance critical operations are performed through segment of kernel provided user code reachable from user space at a fixed address in kernel memory. Those fixed entry points are within the vector page so we basically get it for free as no extra memory page is required and nothing else may be mapped at that location anyway. This is different from (but doesn't preclude) a full blown VDSO implementation, however a VDSO would prevent some assembly tricks with constants that allows for efficient branching to those code segments. And since those code segments only use a few cycles before returning to user code, the overhead of a VDSO far call would add a significant overhead to such minimalistic operations. The ARM_NR_set_tls syscall also changed number. This is done for two reasons: 1) this patch changes the way the TLS value was previously meant to be retrieved, therefore we ensure whatever library using the old way gets fixed (they only exist in private tree at the moment since the NPTL work is still progressing). 2) the previous number was allocated in a range causing an undefined instruction trap on kernels not supporting that syscall and it was determined that allocating it in a range returning -ENOSYS would be much nicer for libraries trying to determine if the feature is present or not. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29[PATCH] ARM: 2655/1: ARM1136 SWP instruction abort handler fixGeorge G. Davis
Patch from George G. Davis As noted in http://www.arm.com/linux/patch-2.6.9-arm1.gz, the "Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR." So the v6_early_abort handler does not report the correct rd/wr direction for the SWP instruction which may result in SEGVS or hangs. In order to work around this problem, this patch merely updates the fix contained in the ARM Ltd. patch to use the macroised abort handler fixups. Signed-off-by: George G. Davis Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29[PATCH] ARM: 2659/1: do not assign PCI I/O address zero on IXP2000Lennert Buytenhek
Patch from Lennert Buytenhek Assigning the address zero to a PCI device BAR causes some part of the PCI subsystem to believe that resource allocation for that BAR failed due to resource conflicts, which will make attempts to enable the device fail. Work around this by assigning I/O addresses starting from 00010000. While we're at it, make the PCI I/O resource end at 0001ffff, since we only have 64k of outbound I/O window on the IXP2000, and we don't do bank switching. Signed-off-by: Lennert Buytenhek Signed-off-by: Deepak Saxena Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29[PATCH] ARM: 2658/1: start ixp2000 pci memory resource at 0xe0000000Lennert Buytenhek
Patch from Lennert Buytenhek On the IXDP2800, the bootloader does an awful job of configuring the PCI bus, so we make linux reconfigure everything. Having a 1:1 pci:phys address mapping generally simplifies everything, so try to allocate PCI addresses from the [e0000000..ffffffff] range, which is the physical address range of the outbound PCI window on the IXP2000. This does not affect any of the other IXP2000 platforms since they all use their bootloader's PCI resource assignment. Signed-off-by: Lennert Buytenhek Signed-off-by: Deepak Saxena Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29[PATCH] ARM: 2657/1: export ixp2000_pci_config_addrLennert Buytenhek
Patch from Lennert Buytenhek Export ixp2000_pci_config_addr, to be used by the IXDP2800 platform setup code to coordinate booting the master and slave NPU. Signed-off-by: Lennert Buytenhek Signed-off-by: Deepak Saxena Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29x86: make traps on 'iret' be debuggable in user spaceLinus Torvalds
This makes a trap on the 'iret' that returns us to user space cause a nice clean SIGSEGV, instead of just a hard (and silent) exit. That way a debugger can actually try to see what happened, and we also properly notify everybody who might be interested about us being gone. This loses the error code, but tells the debugger what happened with ILL_BADSTK in the siginfo.
2005-04-28[PATCH] x86_64: fix PT_NOTE addition to IA32 vDSORoland McGrath
The addition of the PT_NOTE didn't take in the x86_64 version of the i386 vDSO, because I forgot the linker script bit in that copy. Signed-off-by: Roland McGrath <roland@redhat.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-27[PATCH] ppc64: Fix return value of some vDSO callsBenjamin Herrenschmidt
The ppc vDSO would not properly clear the return value for some calls, which will be a problem when interfacing those calls with glibc. This should be fixed before 2.6.12 is released (as it is the first kernel with the ppc vDSO) so that we don't have to play with symbol versioning and ugly workarounds. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-27Automatic merge of ↵Linus Torvalds
rsync://rsync.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6.git
2005-04-26[PATCH] ppc64: trivial user annotationsAl Viro
Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-26Automatic merge of kernel.org:/home/rmk/linux-2.6-rmk.gitLinus Torvalds
2005-04-26[PATCH] amd64 rt_sigframe user annotationAl Viro
->pretcode in struct rt_sigframe is a userland pointer (and already treated as such by code using that field). Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-26[PATCH] ppc-opc NULL noise removalAl Viro
Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-26[PATCH] ARM: make entry*.S includes more logicalRussell King
Move common includes to entry-header, and file specific includes to the relevant file. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26[PATCH] ARM: Remove single-use user save/restore macrosRussell King
Assembly macros are pointless if they're only used once. Move them inline. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26[PATCH] ARM: remove PT_TRACESYSRussell King
PT_TRACESYS is unused, remove it. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26[PATCH] ARM: Remove SVC_MODE definitionRussell King
SVC_MODE reflects the MODE_SVC definition in asm/ptrace.h. Use the asm/ptrace.h definition instead, and remove SVC_MODE. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26[PATCH] ARM: Use __NR_SYSCALL_BASE and __ARM_NR_BASE in asm codeRussell King
Don't define our own local constants, but use those already defined in asm/unistd.h instead. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26[PATCH] ARM: pt_regs offsetsRussell King
Generate pt_regs S_xx offsets from the structure itself instead of #defining them. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26[PATCH] ARM: Remove argument for disable_irq/enable_irqRussell King
Since we do not require a register for these operations, we can remove this unnecessary argument. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26[PATCH] ARM: remove some entry initialisation asm codeRussell King
Convert the trivial vector entry initialisation code to C code. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-25Automated merge of kernel.org:/home/rmk/linux-2.6-rmk.gitLinus Torvalds
2005-04-25[PATCH] ARM: 2650/1: PXA27x sleep - workaround Errata 39 & 50 (Patch 2667)Jeff Lackey
Patch from Jeff Lackey This patch updates arch/arm/mach-pxa/sleep.S to support the PXA270 CPU. It works around Errata 39 & 50 from the Intel(R) PXA27x Processor Family Specification Update. Signed-off-by: Jeff Lackey Signed-off-by: Russell King
2005-04-25From: jbarnes@sgi.comJesse Barnes
[IA64] fix ia64 Kconfig to allow CONFIG_PM on sn2 This probably should have been fixed when I fixed up the generic build for discontig+numa machines, but oh well. CONFIG_PM is allowable for generic builds but not for sn2 builds, which doesn't make much sense, and in fact breaks the build if recent ACPI bits are added to the tree. It looks like the only arch that needs to prevent CONFIG_PM stuff is the ski simulator (though those options could probably use some cleanup as well), so remove the big conditional and replace it with a simple test for IA64_HP_SIM instead. Signed-off-by: Jesse Barnes <jbarnes@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64] iosapic.c: typo ... s/spin_unlock_irq/spin_unlock/Kenji Kaneshige
vector sharing patch had a typo ... mismatched spin_lock() with a spin_unlock_irq(). Fix from Kenji Kaneshige. Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64] print "siblings" before {physical,core,thread} idTony Luck
Rohit and Suresh changed their mind about the order to print things in /proc/cpuinfo, but didn't include the change in the version of the patch they sent to me. Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64] vector sharing (Large I/O system support)Kenji Kaneshige
Current ia64 linux cannot handle greater than 184 interrupt sources because of the lack of vectors. The following patch enables ia64 linux to handle greater than 184 interrupt sources by allowing the same vector number to be shared by multiple IOSAPIC's RTEs. The design of this patch is besed on "Intel(R) Itanium(R) Processor Family Interrupt Architecture Guide". Even if you don't have a large I/O system, you can see the behavior of vector sharing by changing IOSAPIC_LAST_DEVICE_VECTOR to fewer value. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64] multi-core/multi-thread identificationSuresh Siddha
Version 3 - rediffed to apply on top of Ashok's hotplug cpu patch. /proc/cpuinfo output in step with x86. This is an updated MC/MT identification patch based on the previous discussions on list. Add the Multi-core and Multi-threading detection for IPF. - Add new core and threading related fields in /proc/cpuinfo. Physical id Core id Thread id Siblings - setup the cpu_core_map and cpu_sibling_map appropriately - Handles Hot plug CPU Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Gordon Jin <gordon.jin@intel.com> Signed-off-by: Rohit Seth <rohit.seth@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64] __copy_user breaks on unaligned srcKeith Owens
memcpy_mck.S::__copy_user breaks in the prefetch code under these conditions :- * src is unaligned and * dst is near the end of a page and * the page after dst is unmapped. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64] Need to handle lfetch in "no_context" case.Tony Luck
Thanks to Mark for tracking down this one. Users of __copy_from_user_inatomic() will be sad if we don't handle lfetch faults for the "no_context" case. Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64-SGI] Altix SN add support for slots in geoid_t locatorMark Goodwin
This patch against ia64-test-2.6.12 is needed for forthcoming Altix chipsets. It renames geoid_any_t to geoid_common_t and splits the 8bit 'slab' field into two 4bit fields for 'slab' and 'slot'. Similar changes in the Altix SAL will retain backward compatibility for old kernels. Signed-off-by: Mark Goodwin <markgw@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64] fix syscall-optimization goofDavid Mosberger-Tang
Sadly, I goofed in this syscall-tuning patch: ChangeSet 1.1966.1.40 2005/01/22 13:31:05 davidm@hpl.hp.com [IA64] Improve ia64_leave_syscall() for McKinley-type cores. Optimize ia64_leave_syscall() a bit better for McKinley-type cores. The patch looks big, but that's mostly due to renaming r16/r17 to r2/r3. Good for a 13 cycle improvement. The problem is that the size of the physical stacked registers was loaded into the wrong register (r3 instead of r17). Since r17 by coincidence always had the value 1, this had the effect of turning rse_clear_invalid into a no-op. That poses the risk of leaking kernel state back to user-land and is hence not acceptable. The fix below is simple, but unfortunately it costs us about 28 cycles in syscall overhead. ;-( Unfortunately, there isn't much we can do about that since those registers have to be cleared one way or another. --david Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64-SGI] Shub2 BTE support - BTE recovery codeRuss Anderson
patch 2: Shub2 BTE recovery code will be implemented in SAL. Define the SAL interface. Modify bte_error to call SAL for shub2. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64-SGI] Add new MMR definitions/Modify BTE initialiation&copy.Russ Anderson
patch 1: Add new MMR definitions. Modify BTE initialiation. Modify BTE copy. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64-SGI] disable TIOCA GART TLB prefetchingMark Maule
Patch to disable SGI TIOCA GART TLB prefetching due to hw bug. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64] MAX_PGT_FREES_PER_PASS must be 'L' to avoid warningTony Luck
'min' is very picky about types of arguments, make it happy Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64] sba_iommu bug fixesAlex Williamson
This fixes a couple of bugs in the zx1/sx1000 sba_iommu. These are all pretty low likelihood of hitting. The first problem is a simple off by one, deep in the sba_alloc_range() error path. Surrounding that was a lock ordering problem that could have potentially deadlocked with the order the locks are grabbed in sba_unmap_single(). I moved the resource locking into sba_search_bitmap() to prevent this. Finally, there's a potential race between unmapping pdir entries and marking incoming DMA pages clean. If you see any oddities, please let me know, but I've tested it pretty thoroughly here. Tony, please apply. Thanks, BTW, many of the options in this driver not on by default are becoming more and more broken. I'll be working on some patches to clean them out, but I wanted to get this bug fix out first. Signed-off-by: Alex Williamson <alex.williamson@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64] Percpu quicklist for combined allocator for pgd/pmd/pte.Robin Holt
This patch introduces using the quicklists for pgd, pmd, and pte levels by combining the alloc and free functions into a common set of routines. This greatly simplifies the reading of this header file. This patch is simple but necessary for large numa configurations. It simply ensures that only pages from the local node are added to a cpus quicklist. This prevents the trapping of pages on a remote nodes quicklist by starting a process, touching a large number of pages to fill pmd and pte entries, migrating to another node, and then unmapping or exiting. With those conditions, the pages get trapped and if the machine has more than 100 nodes of the same size, the calculation of the pgtable high water mark will be larger than any single node so page table cache flushing will never occur. I ran lmbench lat_proc fork and lat_proc exec on a zx1 with and without this patch and did not notice any change. On an sn2 machine, there was a slight improvement which is possibly due to pages from other nodes trapped on the test node before starting the run. I did not investigate further. This patch shrinks the quicklist based upon free memory on the node instead of the high/low water marks. I have written it to enable preemption periodically and recalculate the amount to shrink every time we have freed enough pages that the quicklist size should have grown. I rescan the nodes zones each pass because other processess may be draining node memory at the same time as we are adding. Signed-off-by: Robin Holt <holt@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25[IA64-SGI]Bruce Losure
Missed the "bk new" for this file in the last commit. Signed-off-by: Bruce Losure <blosure@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>