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2008-07-11x86/pci: Changing subsystem initialization order for NUMARobert Richter
Cc: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11x86/pci: Removing pci-y in MakefileRobert Richter
Cc: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11Merge branch 'x86/generalize-visws' into x86/coreIngo Molnar
2008-07-11x86: Recover timer_ack lost in the merge of the NMI watchdogMaciej W. Rozycki
In the course of the recent unification of the NMI watchdog an assignment to timer_ack to switch off unnecesary POLL commands to the 8259A in the case of a watchdog failure has been accidentally removed. The statement used to be limited to the 32-bit variation as since the rewrite of the timer code it has been relevant for the 82489DX only. This change brings it back. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11x86: I/O APIC: Never configure IRQ2Maciej W. Rozycki
There is no such entity as ISA IRQ2. The ACPI spec does not make it explicitly clear, but does not preclude it either -- all it says is ISA legacy interrupts are identity mapped by default (subject to overrides), but it does not state whether IRQ2 exists or not. As a result if there is no IRQ0 override, then IRQ2 is normally initialised as an ISA interrupt, which implies an edge-triggered line, which is unmasked by default as this is what we do for edge-triggered I/O APIC interrupts so as not to miss an edge. To the best of my knowledge it is useless, as IRQ2 has not been in use since the PC/AT as back then it was taken by the 8259A cascade interrupt to the slave, with the line position in the slot rerouted to newly-created IRQ9. No device could thus make use of this line with the pair of 8259A chips. Now in theory INTIN2 of the I/O APIC may be usable, but the interrupt of the device wired to it would not be available in the PIC mode at all, so I seriously doubt if anybody decided to reuse it for a regular device. However there are two common uses of INTIN2. One is for IRQ0, with an ACPI interrupt override (or its equivalent in the MP table). But in this case IRQ2 is gone entirely with INTIN0 left vacant. The other one is for an 8959A ExtINTA cascade. In this case IRQ0 goes to INTIN0 and if ACPI is used INTIN2 is assumed to be IRQ2 (there is no override and ACPI has no way to report ExtINTA interrupts). This is where a problem happens. The problem is INTIN2 is configured as a native APIC interrupt, with a vector assigned and the mask cleared. And the line may indeed get active and inject interrupts if the master 8959A has its timer interrupt enabled (it might happen for other interrupts too, but they are normally masked in the process of rerouting them to the I/O APIC). There are two cases where it will happen: * When the I/O APIC NMI watchdog is enabled. This is actually a misnomer as the watchdog pulses are delivered through the 8259A to the LINT0 inputs of all the local APICs in the system. The implication is the output of the master 8259A goes high and low repeatedly, signalling interrupts to INTIN2 which is enabled too! [The origin of the name is I think for a brief period during the development we had a capability in our code to configure the watchdog to use an I/O APIC input; that would be INTIN2 in this scenario.] * When the native route of IRQ0 via INTIN0 fails for whatever reason -- as it happens with the system considered here. In this scenario the timer pulse is delivered through the 8259A to LINT0 input of the local APIC of the bootstrap processor, quite similarly to how is done for the watchdog described above. The result is, again, INTIN2 receives these pulses too. Rafael's system used to escape this scenario, because an incorrect IRQ0 override would occupy INTIN2 and prevent it from being unmasked. My conclusion is IRQ2 should be excluded from configuration in all the cases and the current exception for ACPI systems should be lifted. The reason being the exception not only being useless, but harmful as well. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: "Rafael J. Wysocki" <rjw@sisk.pl> Cc: Matthew Garrett <mjg59@srcf.ucam.org> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11x86: L-APIC: Always fully configure IRQ0Maciej W. Rozycki
Unlike the 32-bit one, the 64-bit variation of the LVT0 setup code for the "8259A Virtual Wire" through the local APIC timer configuration does not fully configure the relevant irq_chip structure. Instead it relies on the preceding I/O APIC code to have set it up, which does not happen if the I/O APIC variants have not been tried. The patch includes corresponding changes to the 32-bit variation too which make them both the same, barring a small syntactic difference involving sequence of functions in the source. That should work as an aid with the upcoming merge. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: "Rafael J. Wysocki" <rjw@sisk.pl> Cc: Matthew Garrett <mjg59@srcf.ucam.org> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11x86: L-APIC: Set IRQ0 as edge-triggeredMaciej W. Rozycki
IRQ0 is edge-triggered, but the "8259A Virtual Wire" through the local APIC configuration in the 32-bit version uses the "fasteoi" handler suitable for level-triggered APIC interrupt. Rewrite code so that the "edge" handler is used. The 64-bit version uses different code and is unaffected. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: "Rafael J. Wysocki" <rjw@sisk.pl> Cc: Matthew Garrett <mjg59@srcf.ucam.org> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11x86: use matching CFI_ENDPROCGlauber Costa
The RING0_INT_FRAME macro defines a CFI_STARTPROC. So we should really be using CFI_ENDPROC after it. Signed-off-by: Glauber Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11x86_64: vdso32 cleanup using feature flagsJeremy Fitzhardinge
Use the X86_FEATURE_SYSENTER32 to remove hard-coded CPU vendor check. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11x86_64: add pseudo-features for 32-bit compat syscallJeremy Fitzhardinge
Add pseudo-feature bits to describe whether the CPU supports sysenter and/or syscall from ia32-compat userspace. This removes a hardcoded test in vdso32-setup. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11x86: fix tsc unification buglet with ftrace and stackprotectorIngo Molnar
Yinghai Lu reported crashes on 64-bit x86: BUG: unable to handle kernel NULL pointer dereference at 0000000000000000 IP: [<ffffffff80253b17>] hrtick_start_fair+0x89/0x173 [...] And with a long session of debugging and a lot of difficulty, tracked it down to this commit: ---------------> 8fbbc4b45ce3e4c0eeb15004c79c72b6896a79c2 is first bad commit commit 8fbbc4b45ce3e4c0eeb15004c79c72b6896a79c2 Author: Alok Kataria <akataria@vmware.com> Date: Tue Jul 1 11:43:34 2008 -0700 x86: merge tsc_init and clocksource code <-------------- The problem is that the TSC unification missed these Makefile rules in arch/x86/kernel/Makefile: # Do not profile debug and lowlevel utilities CFLAGS_REMOVE_tsc_64.o = -pg CFLAGS_REMOVE_tsc_32.o = -pg ... CFLAGS_tsc_64.o := $(nostackp) ... which rules make sure that various instrumentation and debugging facilities are disabled for code that might end up in a VDSO - such as the TSC code. Reported-and-bisected-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Conflicts: Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11x86: introduce max_low_pfn_mapped for 64-bitYinghai Lu
when more than 4g memory is installed, don't map the big hole below 4g. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11x86: reserve SLITYinghai Lu
save the SLIT, in case we are using fixmap to read it, and that fixmap could be cleared by others. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-11x86: e820: user-defined memory maps: remove the range instead of update it ↵Yinghai Lu
to reserved also let mem= to print out modified e820 map too Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Bernhard Walle <bwalle@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86: fix compile error in current tip.gitJeremy Fitzhardinge
Gas 2.15 complains about 32-bit registers being used in lea. AS arch/x86/lib/copy_user_64.o /local/scratch-2/jeremy/hg/xen/paravirt/linux/arch/x86/lib/copy_user_64.S: Assembler messages: /local/scratch-2/jeremy/hg/xen/paravirt/linux/arch/x86/lib/copy_user_64.S:188: Error: `(%edx,%ecx,8)' is not a valid 64 bit base/index expression /local/scratch-2/jeremy/hg/xen/paravirt/linux/arch/x86/lib/copy_user_64.S:257: Error: `(%edx,%ecx,8)' is not a valid 64 bit base/index expression AS arch/x86/lib/copy_user_nocache_64.o /local/scratch-2/jeremy/hg/xen/paravirt/linux/arch/x86/lib/copy_user_nocache_64.S: Assembler messages: /local/scratch-2/jeremy/hg/xen/paravirt/linux/arch/x86/lib/copy_user_nocache_64.S:107: Error: `(%edx,%ecx,8)' is not a valid 64 bit base/index expression Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Cc: Vitaly Mayatskikh <v.mayatskih@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: fix pci_direct_conf1 dependencyIngo Molnar
fix: arch/x86/pci/built-in.o: In function `pci_subsys_init': visws.c:(.init.text+0xfc5): undefined reference to `pci_direct_conf1' Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: build fixIngo Molnar
fix: arch/x86/kernel/built-in.o: In function `visws_early_detect': : undefined reference to `mach_get_smp_config_quirk' arch/x86/kernel/built-in.o: In function `visws_early_detect': : undefined reference to `mach_find_smp_config_quirk' Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86: remove duplicate call to use_tsc_delayGlauber Costa
Integration generated a duplicate call to use_tsc_delay. Particularly, the one that is done before we check for general tsc usability seems wrong. Signed-off-by: Glauber Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: build fixIngo Molnar
fix: arch/x86/kernel/visws_quirks.c: In function ‘visws_early_detect’: arch/x86/kernel/visws_quirks.c:293: error: ‘no_broadcast’ undeclared (first use in this function) arch/x86/kernel/visws_quirks.c:293: error: (Each undeclared identifier is reported only once arch/x86/kernel/visws_quirks.c:293: error: for each function it appears in.) make[1]: *** [arch/x86/kernel/visws_quirks.o] Error 1 make: *** [arch/x86/kernel/visws_quirks.o] Error 2 Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: do not allow VisWS for VoyagerIngo Molnar
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86/pci: fix warnings in subsys_initcall functionsRobert Richter
Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86/pci merge: fixing numaq initializationRobert Richter
Patch d49c4288 (tip/x86/mpparse) introduced some changes in calling subsys_init calls if CONFIG_X86_NUMAQ option is set. This patch updates subsystem initalization according to this changes. Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, eliminate Kconfig specialsIngo Molnar
remove leftover traces of various VISWS related Kconfig specials. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, remove leftover filesIngo Molnar
remove leftover arch/x86/mach-visws/* files. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, clean upIngo Molnar
merge traps_visws.c and apic_visws.c into visws_quirks.c. (no code changed) Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, clean upIngo Molnar
rename setup_visws.c to visws_quirks.c. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, IO-APIC setup fixIngo Molnar
skip IO-APIC setup on a VISWS if it's enabled. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, clean upIngo Molnar
remove VISWS Kconfig complications, now that it's supported by the generic architecture. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, flip over VISWS to generic archIngo Molnar
this is the big move: flip over VISWS to generic arch support. From this commit on CONFIG_X86_VISWS is just another (default-disabled) option that turns on certain quirks - no other complications. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, copy visws filesIngo Molnar
copy arch/x86/mach-visws/setup_visws.c, apic_visws.c and traps_visws.c files to arch/x86/kernel/, in preparation of the switchover to a non-subarch setup for VISWS. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, add early quirks to default architecturesIngo Molnar
add early quirk support to the generic architecture code. this allows VISWS to be supported by the generic code and allows us to remove the VISWS subarch. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, create include/asm-x86/visws/Ingo Molnar
move the include/asm-x86/mach-visws/ VISWS specific hardware details include files into include/asm-x86/visws, to be used from generic code. No code changed. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, install proper PCI quirkIngo Molnar
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, use generic mpparse codeIngo Molnar
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, add early init quirksIngo Molnar
add early init quirks for VisWS. This gradually turns the VISWS subarch into a generic PC architecture. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, VisWS: turn into generic arch, make VisWS boot on a regular PCIngo Molnar
first step: make the VISWS subarch boot on a regular PC. We take various shortcuts for that. We copy the generic arch setup file over into the VISWS setup file. This is the only step that is not expected to boot on a real VISWS. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86: add early quirk supportIngo Molnar
Add early quirks support. In preparation of enabling the generic architecture to boot on a VISWS. This will allow us to remove the VISWS subarch and all its complications. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10Merge branch 'x86/unify-pci' into x86/coreIngo Molnar
2008-07-10x86: fix visws and vsmp buildIngo Molnar
these two sub-architectures want PCI to be default-on, not default-off. Reported-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86: I/O APIC: Add a 64-bit variation of replace_pin_at_irq()Maciej W. Rozycki
When an interrupt is rerouted to a different I/O APIC pin the relevant entry of the irq_2_pin list should get updated accordingly so that operations are performed on the correct redirection entry. This is already done by the 32-bit variation of the code and here is a complementing 64-bit implementation. Should make someone's decision less tough when merging the two. ;) Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10Revert "x86: fix IO APIC breakage on HP nx6325"Ingo Molnar
This reverts commit 90221a61a71b7ad659d8741cf1e404506b174982. This too was just temporary diagnostics - not needed now that we've got the final fix via: | commit e2079c43861f71b2deb78ee20e247ad954fdd67e | Author: Rafael J. Wysocki <rjw@sisk.pl> | Date: Tue Jul 8 16:12:26 2008 +0200 | | x86: fix C1E && nx6325 stability problem Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10Revert "x86: fix IO APIC breakage on HP nx6325, v2"Ingo Molnar
This reverts commit a74a1cc3df0be89658bc735c8aed80c8392e2c15. This was just temporary diagnostics commit - not needed now that we've got the final fix. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, AMD IOMMU: clean up Kconfig entryFUJITA Tomonori
AMD_IOMMU should depend on IOMMU_HELPER since they are the IOMMU helper functions. SWIOTLB requires IOMMU_HELPER so declaring that AMD_IOMMU depends on SWIOTLB properly fixes the problems. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86: make e820_end return end_of_ram again for 64bitYinghai Lu
even on 64bit systems with less than 4G RAM, we can now use fixmap to handle acpi SIT near end of ram. change e820_end to e820_end_of_ram again? or e820_ram_pfn? Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86, acpi: merge __acpi_map_tableYinghai Lu
and let 64-bit to fall back to use fixmap too. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10x86: overmapped fix when 4K pages on tail, 64-bitYinghai Lu
fix phys_pmd_init to make sure not to return bigger value than end. also print out range split:1G/2M/4K in init_memory_mapping(). Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-09x86: fix copy_user on x86Vitaly Mayatskikh
Switch copy_user_generic_string(), copy_user_generic_unrolled() and __copy_user_nocache() from custom tail handlers to generic copy_user_tail_handle(). Signed-off-by: Vitaly Mayatskikh <v.mayatskih@gmail.com> Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-09x86: introduce copy_user_handle_tail() routineVitaly Mayatskikh
Introduce generic C routine for handling necessary tail operations after protection fault in copy_*_user on x86. Signed-off-by: Vitaly Mayatskikh <v.mayatskih@gmail.com> Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-09Merge branch 'x86/unify-lib' into x86/coreIngo Molnar
2008-07-09x86: e820 memmap - add checking for NULL early paramCyrill Gorcunov
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Cc: Cyrill Gorcunov <gorcunov@gmail.com> Cc: akpm@linux-foundation.org Cc: andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@elte.hu>
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