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2006-06-21[POWERPC] spufs: remove stop_code from struct spuMasato Noguchi
This patch remove 'stop_code' -- discarded member of struct spu. It is written at initialize and interrupt, but never read in current implementation. Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] spufs: fix spu irq affinity settingGeoff Levand
This changes the hypervisor abstraction of setting cpu affinity to a higher level to avoid platform dependent interrupt controller routines. I replaced spu_priv1_ops:spu_int_route_set() with a new routine spu_priv1_ops:spu_cpu_affinity_set(). As a by-product, this change eliminated what looked like an existing bug in the set affinity code where spu_int_route_set() mistakenly called int_stat_get(). Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] spufs: further abstract priv1 register accessGeoff Levand
To support muti-platform binaries the spu hypervisor accessor routines must have runtime binding. I removed the existing statically linked routines in spu.h and spu_priv1_mmio.c and created new accessor routines in spu_priv1.h that operate indirectly through an ops struct spu_priv1_ops. spu_priv1_mmio.c contains the instance of the accessor routines for running on raw hardware. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] spufs: split the Cell BE support into generic and platform ↵Geoff Levand
dependant parts Creates new config variables PPC_CELL_NATIVE and PPC_IBM_CELL_BLADE. The existing CONFIG_PPC_CELL is now used to denote the generic Cell processor support. PPC_CELL = make descends into platforms/cell PPC_CELL_NATIVE = add bare metal support PPC_IBM_CELL_BLADE = add blade device drivers, etc. Also renames spu_priv1.c to spu_priv1_mmio.c. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] spufs: dont try to access SPE channel 1 countarnd@arndb.de
The save/restore sequence for SPE contexts currently attempts to save and restore the channel count for SPE channel 1 (the SPU_WriteEventMask channel. But the CBE architecture (section 9.11.2) clearly states that this channel does not have an associated count. Hardware simply ignores the attempt to write this count, but the simulator generates a warning message. WARNING: 279721590: SPE7: Attempt to write channel count for CH 1 with no associated count is ignored. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] spufs: use kzalloc in create_spuJeremy Kerr
Clean up create_spu() a little by using kzalloc instead of kmalloc + assignments. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] spufs: fix initial state of wbox filearnd@arndb.de
The wbox channel count of an spu is now initialized to four for the saved context. This makes it possible to write to the mailbox right away without waiting for the SPE to become scheduled first. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] spufs: add a phys-id attribute to each SPU contextarnd@arndb.de
For performance analysis, it is often interesting to know which physical SPE a thread is currently running on, and, more importantly, if it is running at all. This patch adds a simple attribute to each SPU directory with that information. The attribute is read-only and called 'phys-id'. It contains an ascii string with the number of the physical SPU (e.g. "0x5"), or alternatively the string "0xffffffff" (32 bit -1) when it is not running at all at the time that the file is read. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] spufs: set up correct SLB entries for 64k pagesarnd@arndb.de
spufs currently knows only 4k pages and 16M hugetlb pages. Make it use the regular methods for deciding on the SLB bits. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] spufs: fix deadlock in spu_create error pathMichael Ellerman
spufs_rmdir tries to acquire the spufs root i_mutex, which is already held by spufs_create_thread. This was tracked as Bug #H9512. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] spufs: restore mapping of mssync registerarnd@arndb.de
A recent change to the way that the mfc file gets mapped made it impossible to map the SPE Multi-Source Synchronization register into user space, but that may be needed by some applications. This restores the missing functionality. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] cell: always build spu base into the kernelarnd@arndb.de
The spu_base module is rather deeply intermixed with the core kernel, so it makes sense to have that built-in. This will let us extend the base in the future without having to export more core symbols just for it. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] cell: register SPUs as sysdevsJeremy Kerr
SPUs are registered as system devices, exposing attributes through sysfs. Since the sysdev includes a kref, we can remove the one in struct spu (it isn't used at the moment anyway). Currently only the interrupt source and numa node attributes are added. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] cell: update defconfigarnd@arndb.de
Enable some of the most requested features in defconfig and refresh with the latest powerpc.git Kconfig files. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] cell: fix interrupt priority handlingarnd@arndb.de
Checking the priority field to test for irq validity is completely bogus and breaks with future external interrupt controllers. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] cell: add RAS supportBenjamin Herrenschmidt
This is a first version of support for the Cell BE "Reliability, Availability and Serviceability" features. It doesn't yet handle some of the RAS interrupts (the ones described in iic_is/iic_irr), I'm still working on a proper way to expose these. They are essentially a cascaded controller by themselves (sic !) though I may just handle them locally to the iic driver. I need also to sync with David Erb on the way he hooked in the performance monitor interrupt. So that's all for 2.6.17 and I'll do more work on that with my rework of the powerpc interrupt layer that I'm hacking on at the moment. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] Add mpc8641hpcn PCI/PCI-Express platform files.Jon Loeliger
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] Add the MPC8641 HPCN platform files.Jon Loeliger
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] Add starting of secondary 86xx CPUs.Jon Loeliger
Clear the high BATS during load_up_mmu if FTR_HAS_HIGH_BATS. Allow just a bit more time for secondary CPUs to phone home. Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] Add 8641 CPU table entry.Jon Loeliger
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com> Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] Add mpc8641_hpcn_defconfig config file.Jon Loeliger
Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] Add the mpc8641 hpcn Kconfig and Makefiles.Jon Loeliger
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] Prevent duplicate lmb reservations for Device Tree blob.Jon Loeliger
Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] Guard L3CR references with CPU_FTR_L3CR.Jon Loeliger
Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-21[POWERPC] RTAS delay, fix module build breaksJohn Rose
Export both news RTAS delay functions, and change the scanlog module to use the new delay functions. Signed-off-by: John Rose <johnrose@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-20Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (42 commits) [ARM] Fix tosa build error [ARM] 3610/1: Make reboot work on Versatile [ARM] 3609/1: S3C24XX: defconfig update for s3c2410_defconfig [ARM] 3591/1: Anubis: IDE device definitions [ARM] Include asm/hardware.h not asm/arch/hardware.h [ARM] 3594/1: Poodle: Add touchscreen support + other updates [ARM] 3564/1: sharpsl_pm: Abstract some machine specific parameters [ARM] 3561/1: Poodle: Correct the MMC/SD power control [ARM] 3593/1: Add reboot and shutdown handlers for Zaurus handhelds [ARM] 3599/1: AT91RM9200 remove global variables [ARM] 3607/1: AT91RM9200 misc fixes [ARM] 3605/1: AT91RM9200 Power Management [ARM] 3604/1: AT91RM9200 New boards [ARM] 3603/1: AT91RM9200 remove old files [ARM] 3592/1: AT91RM9200 Serial driver update [ARM] 3590/1: AT91RM9200 Platform devices support [ARM] 3589/1: AT91RM9200 DK/EK board update [ARM] 3588/1: AT91RM9200 CSB337/637 board update [ARM] 3587/1: AT91RM9200 hardware headers [ARM] 3586/1: AT91RM9200 header update ...
2006-06-20Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds
* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SPARC64]: Update defconfig. [SPARC64]: Don't double-export synchronize_irq. [SPARC64]: Move over to GENERIC_HARDIRQS. [SPARC64]: Virtualize IRQ numbers. [SPARC64]: Kill ino_bucket->pil [SPARC]: Kill __irq_itoa(). [SPARC64]: bp->pil can never be zero [SPARC64]: Send all device interrupts via one PIL. [SPARC]: Fix iommu_flush_iotlb end address [SPARC]: Mark smp init functions as cpuinit [SPARC]: Add missing rw can_lock macros [SPARC]: Setup cpu_possible_map [SPARC]: Add topology_init()
2006-06-20[ARM] Fix tosa build errorRussell King
tosa.c references mdelay(), but was missing linux/delay.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-20Merge git://git.infradead.org/~dwmw2/rbtree-2.6Linus Torvalds
* git://git.infradead.org/~dwmw2/rbtree-2.6: [RBTREE] Switch rb_colour() et al to en_US spelling of 'color' for consistency Update UML kernel/physmem.c to use rb_parent() accessor macro [RBTREE] Update hrtimers to use rb_parent() accessor macro. [RBTREE] Add explicit alignment to sizeof(long) for struct rb_node. [RBTREE] Merge colour and parent fields of struct rb_node. [RBTREE] Remove dead code in rb_erase() [RBTREE] Update JFFS2 to use rb_parent() accessor macro. [RBTREE] Update eventpoll.c to use rb_parent() accessor macro. [RBTREE] Update key.c to use rb_parent() accessor macro. [RBTREE] Update ext3 to use rb_parent() accessor macro. [RBTREE] Change rbtree off-tree marking in I/O schedulers. [RBTREE] Add accessor macros for colour and parent fields of rb_node
2006-06-20Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits) [ARM] 3559/1: S3C2442: core and serial port [ARM] 3557/1: S3C24XX: centralise and cleanup uart registration [ARM] 3558/1: SMDK24XX: LED platform devices [ARM] 3534/1: add spi support to lubbock platform [ARM] 3554/1: ARM: Fix dyntick locking [ARM] 3553/1: S3C24XX: earlier print of cpu idcode info [ARM] 3552/1: S3C24XX: Move VA of GPIO for low-level debug [ARM] 3551/1: S3C24XX: PM code failes to compile with CONFIG_DCACHE_WRITETHROUGH [ARM] 3550/1: OSIRIS: fix serial port map for 1:1 [ARM] 3548/1: Fix the ARMv6 CPU id in compressed/head.S [ARM] 3335/1: Old-abi Thumb sys_syscall broken [ARM] 3467/1: [3/3] Support for Philips PNX4008 platform: defconfig [ARM] 3466/1: [2/3] Support for Philips PNX4008 platform: chip support [ARM] 3465/1: [1/3] Support for Philips PNX4008 platform: headers [ARM] 3407/1: lpd7x: documetation update [ARM] 3406/1: lpd7x: compilation fix for smc91x [ARM] 3405/1: lpd7a40x: CPLD ssp driver [ARM] 3404/1: lpd7a40x: AMBA CLCD support [ARM] 3403/1: lpd7a40x: updated default configurations [ARM] 3402/1: lpd7a40x: serial driver bug fix ...
2006-06-20[ARM] 3610/1: Make reboot work on VersatileDeepak Saxena
Patch from Deepak Saxena This patch makes soft reboot work on the Versatile board. Thanks to Catalin Marinas @ ARM for pointing out the proper way to do this. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-20Merge S3Cxxxx branchRussell King
2006-06-20[ARM] Include asm/hardware.h not asm/arch/hardware.hRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-20Merge Zaurus branchRussell King
2006-06-20Merge AT91 branchRussell King
2006-06-20[ARM] 3599/1: AT91RM9200 remove global variablesAndrew Victor
Patch from Andrew Victor This patch removes some now unnecessary global variables - at91_master_clock, at91_serial_map, at91_console_port. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-20[ARM] 3609/1: S3C24XX: defconfig update for s3c2410_defconfigBen Dooks
Patch from Ben Dooks Update s3c2410_defconfig to latest kernel with the latest patches Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-20[ARM] 3607/1: AT91RM9200 misc fixesAndrew Victor
Patch from Andrew Victor This final patch includes some general fixes. 1. Link in pm.o if CONFIG_PM is enabled. [Should have been included in patch 3605/1]. 2. Use __raw_readl()/__raw_writel() when accessing System Peripheral registers. 3. Removed some unnecessary includes Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-20[ARM] 3605/1: AT91RM9200 Power ManagementAndrew Victor
Patch from Andrew Victor This patch adds the core Power Management support for the AT91RM9200 processor. It will support suspend-to-RAM and standby modes. The suspend-to-RAM functionality is not 100% complete. The code that needs to be execute from the internal SRAM to restore the system is outstanding. For now we just fall through to Standby mode. The AT91-specific at91_suspend_entering_slow_clock() function will eventually be replaced by clk_must_disable() once that functionality is added to mainline clock API. Patch from David Brownell. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-20[ARM] 3604/1: AT91RM9200 New boardsAndrew Victor
Patch from Andrew Victor This patch adds support for an additional 4 AT91RM9200-based boards: 1. Conitec ARM&EVA [MACH_CARMEVA] (http://www.conitec.net/english/linuxboard.htm) 2. KwikByte KB920x [MACH_KB9200] (http://kwikbyte.com/KB9202_description_new.htm) 3. Embest ATEB9200 [MACH_ATEB9200] (http://www.embedinfo.com/english/product/ATEB9200.asp) 4. Sperry-Sun KAFA board [MACH_KAFA] (unknown) Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-20[SPARC64]: Update defconfig.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20[SPARC64]: Don't double-export synchronize_irq.David S. Miller
It is done by the generic IRQ layer now. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20[SPARC64]: Move over to GENERIC_HARDIRQS.David S. Miller
This is the long overdue conversion of sparc64 over to the generic IRQ layer. The kernel image is slightly larger, but the BSS is ~60K smaller due to the reduced size of struct ino_bucket. A lot of IRQ implementation details, including ino_bucket, were moved out of asm-sparc64/irq.h and are now private to arch/sparc64/kernel/irq.c, and most of the code in irq.c totally disappeared. One thing that's different at the moment is IRQ distribution, we do it at enable_irq() time. If the cpu mask is ALL then we round-robin using a global rotating cpu counter, else we pick the first cpu in the mask to support single cpu targetting. This is similar to what powerpc's XICS IRQ support code does. This works fine on my UP SB1000, and the SMP build goes fine and runs on that machine, but lots of testing on different setups is needed. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20[SPARC64]: Virtualize IRQ numbers.David S. Miller
Inspired by PowerPC XICS interrupt support code. All IRQs are virtualized in order to keep NR_IRQS from needing to be too large. Interrupts on sparc64 are arbitrary 11-bit values, but we don't need to define NR_IRQS to 2048 if we virtualize the IRQs. As PCI and SBUS controller drivers build device IRQs, we divy out virtual IRQ numbers incrementally starting at 1. Zero is a special virtual IRQ used for the timer interrupt. So device drivers all see virtual IRQs, and all the normal interfaces such as request_irq(), enable_irq(), etc. translate that into a real IRQ number in order to configure the IRQ. At this point knowledge of the struct ino_bucket is almost entirely contained within arch/sparc64/kernel/irq.c There are a few small bits in the PCI controller drivers that need to be swept away before we can remove ino_bucket's definition out of asm-sparc64/irq.h and privately into kernel/irq.c Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20[SPARC64]: Kill ino_bucket->pilDavid S. Miller
And reuse that struct member for virt_irq, which will be used in future changesets for the implementation of mapping between real and virtual IRQ numbers. This nicely kills off a ton of SBUS and PCI controller PIL assignment code which is no longer necessary. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20[SPARC]: Kill __irq_itoa().David S. Miller
This ugly hack was long overdue to die. It was a way to print out Sparc interrupts in a more freindly format, since IRQ numbers were arbitrary opaque 32-bit integers which vectored into PIL levels. These 32-bit integers were not necessarily in the 0-->NR_IRQS range, but the PILs they vectored to were. The idea now is that we will increase NR_IRQS a little bit and use a virtual<-->real IRQ number mapping scheme similar to PowerPC. That makes this IRQ printing hack irrelevant, and furthermore only a handful of drivers actually used __irq_itoa() making it even less useful. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20[SPARC64]: bp->pil can never be zeroDavid S. Miller
Only pil0_dummy_bucket had a pil of zero and we just killed that off, so we can delete all special case code that used bp->pil==0 as a way to identify a dummy bucket. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20[SPARC64]: Send all device interrupts via one PIL.David S. Miller
This is the first in a series of cleanups that will hopefully allow a seamless attempt at using the generic IRQ handling infrastructure in the Linux kernel. Define PIL_DEVICE_IRQ and vector all device interrupts through there. Get rid of the ugly pil0_dummy_{bucket,desc}, instead vector the timer interrupt directly to a specific handler since the timer interrupt is the only event that will be signaled on PIL 14. The irq_worklist is now in the per-cpu trap_block[]. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20[SPARC]: Fix iommu_flush_iotlb end addressBob Breuer
Fix the calculation of the end address when flushing iotlb entries to ram. This bug has been a cause of esp dma errors, and it affects HyperSPARC systems much worse than SuperSPARC systems. Signed-off-by: Bob Breuer <breuerr@mc.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-20[SPARC]: Mark smp init functions as cpuinitBob Breuer
Fix the smp related section mismatch warnings by marking the smp init functions as cpuinit. Signed-off-by: Bob Breuer <breuerr@mc.net> Signed-off-by: David S. Miller <davem@davemloft.net>