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2009-07-29drm/i915: Set preferred mode for integrated TV according to TV formatling.ma@intel.com
In order to get best possible quality image we chose 640x480 for NTSC, PAL and 480p, 1280x720 for 720p, 1920x1080 for 1080i/p TV format respectively. Signed-off-by: Ma Ling <ling.ma@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-29drm/i915: fix 845G FIFO size & burst lengthJesse Barnes
I had one report of flicker due to FIFO underruns on 845G. Scott was kind enough to test a few patches and report success with this one. Looks like 845G measures FIFO size slightly differently than other chips, and we were also clobbering the FIFO burst length. Fixing both of those issues gives him a healthy machine again. Note that we still only adjust plane A's watermark in the 830/845 case. If someone is willing to test we could support a bigger variety of dual-head 830/845 configurations with a bit more code. Fixes fdo bug #19304 (again). Reported-by: Scott Hansen <scottandchrystie@comcast.net> Tested-by: Scott Hansen <scottandchrystie@comcast.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-29drm/i915: fix VGA detect on IGDNGZhenyu Wang
Check FORCE_DETECT bit to be clear for the finish of hotplug detect process. Also check possible mono monitor which should also be marked as connected. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-29drm/i915: Add eDP support on IGDNG mobile chipZhenyu Wang
This adds embedded DisplayPort support on next mobile chip which aims to replace origin LVDS port. VBT's driver feature block has been used to determine the type of current internal panel for eDP or LVDS. Currently no panel fitting support for eDP and backlight control would be added in future. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-29drm/i915: enable DisplayPort support on IGDNGZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-29drm/i915: Fix channel ending action for DP aux transactionZhenyu Wang
We should use current channel 'status' bits to clear DP aux channel's done and error bits, instead of using the channel setting bits, that will set send/busy bit again to initiate new transaction. This also includes also some minor cleanup. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-29drm/i915: fix issue in display pipe setup on IGDNGZhenyu Wang
During pipe DPMS off, instead of busy waiting pipe off, insert delays during wait and don't loop after enough tries which matches spec requirement. Also try to match DPMS on path by disable FDI TX PLL in DPMS off. Disable PF by writing PF_WIN_SZ which really trigger the update. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-29drm/i915: disable VGA plane reliablyZhenyu Wang
This does VGA disable like DDX driver. SR01 bit 5 should be set before VGA plane disable through control register, otherwise we might get random crash and lockups. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-29drm/I915: Fix offset to DVO timings in LVDS dataZhao Yakui
Now the DVO timing in LVDS data entry is obtained by using the following step: a. get the entry size for every LVDS panel data b. Get the LVDS fp entry for the preferred panel type c. get the DVO timing by using entry->dvo_timing In our driver the entry->dvo_timing is related with the size of lvds_fp_timing. For example: the size is 46. But it seems that the size of lvds_fp_timing varies on the differnt platform. In such case we will get the incorrect DVO timing entry because of the incorrect DVO offset in LVDS panel data entry. This also removes a hack on new IGDNG to get proper DVO timing. Calculate the DVO timing offset in LVDS data entry to get the DVO timing a. get the DVO timing offset in the LVDS fp data entry by using the pointer definition in LVDS data ptr b. get the LVDS data entry c. get the DVO timing by adding the DVO timing offset to data entry https://bugs.freedesktop.org/show_bug.cgi?id=22787 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Tested-by: Zhenyu Wang <zhenyuw@linux.intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-29Merge branch 'drm-radeon-kms' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-radeon-kms' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (35 commits) drm/radeon: set fb aperture sizes for framebuffer handoff. drm/ttm: fix highuser vs dma32 confusion. drm/radeon: Fix size used for benchmarking BO copies. drm/radeon: Add radeon.test parameter for running BO GPU copy tests. drm/radeon/kms: allow interruptible waits for objects. drm/ttm: powerpc: Fix Highmem cache flushing. x86: Export kmap_atomic_prot() needed for TTM. drm/ttm: Fix ttm in-kernel copying of pages with non-standard caching attributes. drm/ttm: Fix an oops and sync object leak. drm/radeon/kms: vram sizing on certain r100 chips needs workaround. drm/radeon: Pay more attention to object placement requested by userspace. drm/radeon: Fall back to evicting BOs with memcpy if necessary. drm/radeon: Don't unreserve twice on failure to validate. drm/radeon/kms: fix bandwidth computation on avivo hardware drm/radeon/kms: add initial colortiling support. drm/radeon/kms: fix hotspot handling on pre-avivo chips drm/radeon/kms: enable frac fb divs on rs600/rs690/rs740 drm/radeon/kms: add PLL flag to prefer frequencies <= the target freq drm/radeon/kms: block RN50 from using 3D engine. drm/radeon/kms: fix VRAM sizing like DDX does it. ...
2009-07-29drm/radeon: set fb aperture sizes for framebuffer handoff.Dave Airlie
This will allow efi/vesa to handoff to radeon. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/ttm: fix highuser vs dma32 confusion.Dave Airlie
DMA32 and highmem are sort of exclusive. Noticed by AndrewR on #radeon. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/radeon: Fix size used for benchmarking BO copies.Michel Dänzer
The incorrect size caused benchmark results to be inflated by a factor of 4. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/radeon: Add radeon.test parameter for running BO GPU copy tests.Michel Dänzer
If enabled, during initialization BO GTT->VRAM and VRAM->GTT GPU copies are tested across the whole GTT aperture. This has helped uncover the benchmark copy size bug and verify the maximum aperture size supported by the AGP bridge in my PowerBook. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/radeon/kms: allow interruptible waits for objects.Dave Airlie
Blocking here isn't something the X server mouse appreciates, avoid the block and let userspace retry the waits. libdrm_radeon userspace library is also expecting EBUSY not ERESTART Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/ttm: powerpc: Fix Highmem cache flushing.Thomas Hellstrom
Temporarily maps highmem pages while flushing to get a valid virtual address to flush. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/ttm: Fix ttm in-kernel copying of pages with non-standard caching ↵Thomas Hellstrom
attributes. For x86 this affected highmem pages only, since they were always kmapped cache-coherent, and this is fixed using kmap_atomic_prot(). For other architectures that may not modify the linear kernel map we resort to vmap() for now, since kmap_atomic_prot() generally uses the linear kernel map for lowmem pages. This of course comes with a performance impact and should be optimized when possible. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/ttm: Fix an oops and sync object leak.Thomas Hellstrom
The code was potentially dereferencig a NULL sync object pointer. At the same time a sync object reference was potentially leaked. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/radeon/kms: vram sizing on certain r100 chips needs workaround.Dave Airlie
If an rn50/r100/m6/m7 GPU has < 64MB RAM, i.e. 8/16/32, the aperture used to calculate the MC_FB_LOCATION needs to be worked out from the CONFIG_APER_SIZE register, and not the actual vram size. TTM VRAM size was also being initialised wrong, use actual vram size to initialise it. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/radeon: Pay more attention to object placement requested by userspace.Michel Dänzer
Previously we were basically always setting the GTT and VRAM flags regardless of what userspace requested. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/radeon: Fall back to evicting BOs with memcpy if necessary.Michel Dänzer
Otherwise if there's no GTT space we would fail the eviction, leading to cascaded failure. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/radeon: Don't unreserve twice on failure to validate.Michel Dänzer
This is done later in radeon_object_list_unvalidate(). Doing it twice triggers a BUG in TTM, rendering X on KMS unusable until reboot. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/radeon/kms: fix bandwidth computation on avivo hardwareJerome Glisse
Fix bandwidth computation and crtc priority in memory controller so that crtc memory request are fullfill in time to avoid display artifact. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-29drm/radeon/kms: add initial colortiling support.Dave Airlie
This adds new set/get tiling interfaces where the pitch and macro/micro tiling enables can be set. Along with a flag to decide if this object should have a surface when mapped. The only thing we need to allocate with a mapped surface should be the frontbuffer. Note rotate scanout shouldn't require one, and back/depth shouldn't either, though mesa needs some fixes. It fixes the TTM interfaces along Thomas's suggestions, and I've tested the surface stealing code with two X servers and not seen any lockdep issues. I've stopped tiling the fbcon frontbuffer, as I don't see there being any advantage other than testing, I've left the testing commands in there, just flip the fb_tiled to true in radeon_fb.c Open: Can we integrate endian swapping in with this? Future features: texture tiling - need to relocate texture registers TXOFFSET* with tiling info. This also merges Michel's cleanup surfaces regs at init time patch even though it makes sense on its own, this patch really relies on it. Some PowerMac firmwares set up a tiling surface at the beginning of VRAM which messes us up otherwise. that patch is: Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-22drm/i915: hdmi detection according by reading edidling.ma@intel.com
According to investigations from windows team ,hw team, and our test results on all 4x platofrms available (gm45, g45b, q45, g45a, g45c, g41a, and g41), we find currently Hot plug live status and Hot plug interrupt detection are not reliable, sometime the results from the two approaches are contradicts. So we chose edid detection for hdmi output. Signed-off-by: Ma Ling <ling.ma@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-16drm/i915: correct self-refresh calculation in "everything off" caseJesse Barnes
If no planes are enabled, the self-refresh calculation may end up doing a divide by zero. This patch should prevent that by making sure at least one of the CRTCs had a valid hdisplay value. Reported-by: Eric Anholt <eric@anholt.net> Tested-by: Eric Anholt <eric@anholt.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-16drm/i915: handle FIFO oversubsription correctlyJesse Barnes
If you're pushing a plane hard (i.e. you need most or all of the FIFO entries just to cover your frame refresh latency), the watermark level may end up being negative. So fix up the signed vs. unsigned math in the calculation function to handle this correctly, giving all available FIFO entries to such a configuration. Reported-by: Eric Anholt <eric@anholt.net> Tested-by: Eric Anholt <eric@anholt.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-15drm/radeon/kms: fix hotspot handling on pre-avivo chipsAlex Deucher
Need to adjust CUR_OFFSET for yorigin Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: enable frac fb divs on rs600/rs690/rs740Alex Deucher
Allows us to hit dot clocks much closer, especially on chips with non-27 Mhz reference clocks like most IGP chips. This fixes most flickering and blanking problems with non-exact dot clocks on these chips. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: add PLL flag to prefer frequencies <= the target freqAlex Deucher
This is needed when using fractional feedback dividers on some IGP chips. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: block RN50 from using 3D engine.Dave Airlie
RN50/ES1000 is a cut-down rv100 chip used in the server market. The 3D engine on these is either not there or unverified so refuse any attempt to configure registers on it. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: fix VRAM sizing like DDX does it.Dave Airlie
Doing this like the DDX seems like the most sure fire way to avoid having to reinvent it slowly and painfully. At the moment we keep getting things wrong with aper vs vram, so we know the DDX does it right. booted on PCI r100, PCIE rv370, IGP rs400. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/ttm/radeon: add dma32 support.Dave Airlie
This add support for using dma32 memory on gpus that really need it. Currently IGPs are left without DMA32 but we might need to change that unless we can fix rs690. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon: Endianness fixes for radeondrmfb.Michel Dänzer
For now handle it via r/g/b offsets and disallow 16 bpp modes on big endian machines. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: don't swap PCIEGART PTEs in VRAM.Dave Airlie
On powerpc, since we aren't using any hw swappers, this will get flipped around by default in hw. tested on a G5 + rv515. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: drop zero length CS indirect buffers.Dave Airlie
If userspace sends a zero length IB, it really shouldn't have bothered so EINVAL it. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: fix vram vs aper size check.Dave Airlie
Fix this to be correct like the DDX code, looks like a typo on transfer to the kernel. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: get lvds info for DIG LVTMA and UNIPHY encodersAlex Deucher
Noticed by Rafał Miłecki on dri-devel. On r6xx/r7xx hardware, laptop panels can be driven by KLDSCP_LVTMA or UNIPHY. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: fix quirk for MSI laptopAlex Deucher
The line mux for the connector in the bios tables is used for enumerating drm connectors. Since this laptop has a quirk where the same line much is listed for both VGA and LVDS, the connectors get combined. Setting the line mux on LVDS to an unused value prevents both encoders from being combined into the same connector. This should fix bko bug 13720. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15ttm: Fix caching mode selection.Thomas Hellstrom
A bug caused a new caching state to be selected on each buffer object validation regardless of the current caching state. Moreover, a caching state could be selected that wasn't supported by the memory type. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon: fix support for vline relocations.Dave Airlie
Userspace sends us a special relocation type to sync video/exa to vlines to avoid tearing, this deals with the relocation in the kernel, it picks the correct crtc and avoids issues where crtcs are disabled. This version also parses the wait until to make sure it isn't trying to do anything evil. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: respect TOM on rs100->rs480 IGP variants.Dave Airlie
Normally we are free to place VRAM where we want in the GPUs memory address space, however on IGP chips the VRAM is actual RAM, and no special translation or aperture is used inside the GPU MC. So when you move the VRAM aperture away from the TOM register, you actually move it into main memory and can trash things quite badly. This commit makes the code respect the TOM location for MC_FB_LOCATION. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: set crtc and cursor offsets correctly on legacy chips.Dave Airlie
The crtc and cursor offsets on the legacy chips are offset from DISPLAY_BASE_ADDR. The code worked if display base addr was at 0, but otherwise falls to pieces. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: remove IB flushing trick.Dave Airlie
If there is a problem then this is hiding it, we shouldn't ever need to flush the IB. Either the buffers are: WB - caching just works. WC - no need to do explicit flush, the MB + readback will do it Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: mmio base/size should be resource_size_t.Dave Airlie
Unsigned long is incorrect for 64-bit resources on 32-bit hw. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm/radeon/kms: fix some GART table entry bugs.Dave Airlie
1. rv370 can accept 40-bit addresses - also at 24-bit shift not 4 bits 2. rs480 table can be in 40-bit space. - 4 bit shift for top 8 bits 3. rs480 table entries can be in 40-bit space. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-07-15drm: Move a dereference below a NULL testJulia Lawall
If the NULL test is necessary, then the dereference should be moved below the NULL test. The semantic patch that makes this change is as follows: (http://www.emn.fr/x-info/coccinelle/) // <smpl> @@ type T; expression E; identifier i,fld; statement S; @@ - T i = E->fld; + T i; ... when != E when != i if (E == NULL) S + i = E->fld; // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Dave Airlie <airlied@linux.ie>
2009-07-15drm/ttm: fix misplaced parenthesesRoel Kluin
Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dave Airlie <airlied@linux.ie>
2009-07-15drm/via: Fix vblank IRQ on VIA hardware.Simon Farnsworth
via_enable_vblank wasn't setting the VBlank enable bit - instead, it was masking out the rest of the register. At the same time, fix via_disable_vblank to clear the VBlank enable bit. Signed-off-by: Dave Airlie <airlied@linux.ie>
2009-07-15drm: drm_gem, check kzalloc retvalJiri Slaby
Check kzalloc retval against NULL in drm_gem_object_alloc and bail out appropriately. While at it merge the fail paths and jump to them by gotos at the end of the function. Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Signed-off-by: Dave Airlie <airlied@linux.ie>