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path: root/drivers/net/tg3.h
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2007-11-12[TG3]: Add A1 revsMatt Carlson
This patch adds the A1 revision of 5784, 5764, and 5761, and applies all previous bugfixes. In places where the list of devices gets too long, the patch uses a new TG3_FLG3_5761_5784_AX_FIXES flag instead. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-11-12[TG3]: Prescaler fixMatt Carlson
Internal hardware timers become inaccurate after link events. Clock frequency switches performed by the CPMU fail to adjust timer prescalers. The fix is to detect core clock frequency changes during link events and adjust the timer prescalers accordingly. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-11-12[TG3]: Disable GPHY autopowerdownMatt Carlson
New CPMU devices contend with the GPHY for power management. The GPHY autopowerdown feature is enabled by default in the PHY and thus needs to be disabled after every PHY reset. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-11-12[TG3]: Fix nvram selftest failuresMatt Carlson
Newer devices contain bootcode in the chip's private ROM area. This bootcode is called selfboot. Selfboot can be patched in the device's NVRAM and the patches can have several formats. In one particular format, the checksum calculation needs to be slightly modified. This patch adjusts the NVRAM test code for that case, and add support for the missing formats. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-11-12[TG3]: 5784 / 5764 DMA engine lockup fixMatt Carlson
5784 and 5764 devices lock up when the link speed is 10Mbps, the CPMU link speed mode is enabled, and the MAC clock is running at 1.5Mhz. The fix is to run the MAC clock at faster speeds. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-11-12[TG3]: 5784 / 5764 GPHY power down fixMatt Carlson
5784 and 5764 devices fail to link / pass traffic after one load / unload cycle. This happens because of a hardware bug in the new CPMU. During normal operation, the MAC depends on the PHY clock being available. When the PHY is powered down, the clock the MAC depends on is disabled. The fix is to switch the MAC clock to an alternate source before powering down the PHY, and to restore the MAC clock to the PHY source upon device resume. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-22[TG3]: PCI command adjustmentMatt Carlson
This patch changes the way the driver works with the PCI command register. It adjusts the access size from dwords to words. This patch is done both as a PCI configuration space cleanup and as preparatory work for PCI error recovery. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-22[TG3]: Add management FW version to ethtool reportMatt Carlson
This patch appends the management firmware version to the bootcode firmware string reported through ethtool. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10[TG3]: WOL defaultsMatt Carlson
This patch enables WOL by default if out-of-box WOL is enabled in the NVRAM. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10[TG3]: Add 5761 supportMatt Carlson
This patch adds rest of the miscellaneous code required to support the 5761. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10[TG3]: Add 5761 APE supportMatt Carlson
This patch adds support for the new APE block, present in 5761 chips. APE stands for Application Processing Engine. The primary function of the APE is to process manageability traffic, such as ASF. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10[TG3]: Add new 5761 NVRAM decode routinesMatt Carlson
This patch adds a new 5761-specific NVRAM strapping decode routine. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10[TG3]: Add 5784 and 5764 support.Matt Carlson
This patch adds the support for 5784 and 5764 devices. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10[TG3]: ASIC decoding and basic CPMU support.Matt Carlson
Newer products change the way the ASIC revision is obtained. This patch implements how the driver will extract the revision number. This patch also adds preliminary CPMU support. CPMU stands for Central Power Management Unit. The CPMU's role is to put the chip into lower power states when the operating conditions allow it. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10[TG3]: Walk PCI capability lists.Matt Carlson
Newer tg3 devices shuffle around the registers in PCI configuration space. This patch changes the way the driver accesses the PCI capabilities registers. Hardcoded register locations are replaced with offsets from pci_find_capability() return values. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10[NET]: Make NAPI polling independent of struct net_device objects.Stephen Hemminger
Several devices have multiple independant RX queues per net device, and some have a single interrupt doorbell for several queues. In either case, it's easier to support layouts like that if the structure representing the poll is independant from the net device itself. The signature of the ->poll() call back goes from: int foo_poll(struct net_device *dev, int *budget) to int foo_poll(struct napi_struct *napi, int budget) The caller is returned the number of RX packets processed (or the number of "NAPI credits" consumed if you want to get abstract). The callee no longer messes around bumping dev->quota, *budget, etc. because that is all handled in the caller upon return. The napi_struct is to be embedded in the device driver private data structures. Furthermore, it is the driver's responsibility to disable all NAPI instances in it's ->stop() device close handler. Since the napi_struct is privatized into the driver's private data structures, only the driver knows how to get at all of the napi_struct instances it may have per-device. With lots of help and suggestions from Rusty Russell, Roland Dreier, Michael Chan, Jeff Garzik, and Jamal Hadi Salim. Bug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra, Joseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan. [ Ported to current tree and all drivers converted. Integrated Stephen's follow-on kerneldoc additions, and restored poll_list handling to the old style to fix mutual exclusion issues. -DaveM ] Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-18[TG3]: Fix msi issue with kexec/kdump.Michael Chan
Tina Yang <tina.yang@oracle.com> discovered an MSI related problem when doing kdump. The problem is that the kexec kernel is booted without going through system reset, and as a result, MSI may already be enabled when tg3_init_one() is called. tg3_init_one() calls pci_save_state() which will save the stale MSI state. Later on in tg3_open(), we call pci_enable_msi() to reconfigure MSI on the chip before we reset the chip. After chip reset, we call pci_restore_state() which will put the stale MSI address/data back onto the chip. This is no longer a problem in the latest kernel because pci_restore_state() has been changed to restore MSI state from internal data structures which will guarantee restoring the proper MSI state. But I think we should still fix it. Our save and restore sequence can still cause very subtle problems down the road. The fix is to have our own functions save and restore precisely what we need. We also change it to save and restore state inside tg3_chip_reset() in a more straight forward way. Thanks to Tina for helping to test and debug the problem. [ Bump driver version and release date. -DaveM ] Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-11[TG3]: Add missing NVRAM strapping.Matt Carlson
This patch adds a missing NVRAM strapping for 5755 devices. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-11[TG3]: Enable auto MDI.Matt Carlson
This patch adds automatic MDI crossover support when autonegotiation is turned off. Automatic MDI crossover allows link to be established without the use of a crossover cable. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-09tg3: use flush_work_keventd()Andrew Morton
Convert tg3 over to flush_work_keventd(). Remove nasty now-unneeded deadlock avoidance logic. (akpm: bypassed maintainers, sorry. There are other patches which depend on this) Cc: "Maciej W. Rozycki" <macro@linux-mips.org> Cc: David Howells <dhowells@redhat.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Michael Chan <mchan@broadcom.com> Cc: Jeff Garzik <jeff@garzik.org> Cc: Oleg Nesterov <oleg@tv-sign.ru> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07[TG3]: Add ASPM workaround.Matt Carlson
This patch adds workaround to fix performance problems caused by slow PCIE L1->L0 transitions on ICH8 platforms. Changed all magic numbers to constants as suggested by Jeff Garzik. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-05[TG3]: Add TG3_FLAG_SUPPORT_MSI flag.Michael Chan
And fix up the code to always allow MSI on 5714 A2. Call tg3_find_peer() earlier because we need that information before we can determine whether we can set TG3_FLAG_SUPPORT_MSI or not. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-05[TG3]: Eliminate the TG3_FLAG_5701_REG_WRITE_BUG flag.Matt Carlson
This patch removes the use of the TG3_FLAG_5701_REG_WRITE_BUG flag. It's logic is only used to set a function pointer and thus the logic can be collapsed and the flag removed. [ Comment tidy by Christoph Hellwig. -DaveM ] Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com>
2007-05-05[TG3]: Eliminate the TG3_FLAG_GOT_SERDES_FLOWCTL flag.Michael Chan
This flag does not do anything useful. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-05[TG3]: WoL fixes.Gary Zambrano
Change TG3_FLAG_SERDES_WOL_CAP to TG3_FLAG_WOL_CAP to make it easier to manage WoL. This flag is now used consistently during ethtool WoL setup and power setting changes. Signed-off-by: Gary Zambrano <zambrano@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-03-25[TG3]: Exit irq handler during chip reset.Michael Chan
On most tg3 chips, the memory enable bit in the PCI command register gets cleared during chip reset and must be restored before accessing PCI registers using memory cycles. The chip does not generate interrupt during chip reset, but the irq handler can still be called because of irq sharing or irqpoll. Reading a register in the irq handler can cause a master abort in this scenario and may result in a crash on some architectures. Use the TG3_FLAG_CHIP_RESETTING flag to tell the irq handler to exit without touching any registers. The checking of the flag is in the "slow" path of the irq handler and will not affect normal performance. The msi handler is not shared and therefore does not require checking the flag. Thanks to Bernhard Walle <bwalle@suse.de> for reporting the problem. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-03-25[TG3]: Eliminate the unused TG3_FLAG_SPLIT_MODE flag.Michael Chan
This flag to support multiple PCIX split completions was never used because of hardware bugs. This will make room for a new flag. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-26[TG3]: TSO workaround fixes.Michael Chan
1. Add race condition check after netif_stop_queue(). tg3_tx() runs without netif_tx_lock and can race with tg3_start_xmit_dma_bug() -> tg3_tso_bug(). 2. Firmware TSO in 5703/5704/5705 also have the same TSO limitation, i.e. they cannot handle TSO headers bigger than 80 bytes. Rename TG3_FL2_HW_TSO_1_BUG to TG3_FL2_TSO_BUG and set this flag on these chips as well. 3. Update version to 3.74. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-13[TG3]: Use constant for PHY register 0x1e.Michael Chan
Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-01-09[TG3]: Add PHY workaround for 5755M.Michael Chan
Some PHY trim values need to be fine-tuned on 5755M to be IEEE-compliant. Update version to 3.72. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-12-17[TG3]: Power down/up 5906 PHY correctly.Michael Chan
The 5906 PHY requires a special register bit to power down and up the PHY. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-12-07[TG3]: Add TG3_FLG2_IS_NIC flag.Michael Chan
Add Tg3_FLG2_IS_NIC flag to unambiguously determine whether the device is NIC or onboard. Previously, the EEPROM_WRITE_PROT flag was overloaded to also mean onboard. With the separation, we can support some devices that are onboard but do not use eeprom write protect. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28[TG3]: Add 5709 self-test support.Michael Chan
Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28[TG3]: Add 5709 PHY support.Michael Chan
Add support for the 5709 10/100 PHY. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28[TG3]: Add basic 5906 support.Michael Chan
Add support for the new 5709 device. This is a new 10/100 Mbps chip. The mailbox access and firmware interface are quite different from all other tg3 chips. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28[TG3]: Add 5722 and 5756 support.Michael Chan
Add IDs to support 5722 and 5756. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28[TG3]: Improve ASF heartbeat.Michael Chan
Change to a different ASF heartbeat message code to improve reliability. There were some reports of unintended resets on real time kernels where the timer may be slow and cause the heartbeat to be late. Netpoll will also have the same problem because the timer irq will be unavailable. Using the new heartbeat code, the ASF firmware will also check the ring condition before resetting the chip when the heartbeat is expiring. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28[TG3]: Improve 5704S autoneg.Michael Chan
Improve 5704S autoneg logic by using a serdes_counter field to keep track of the transient states. This eliminates a 200 msec busy loop in the code. Autoneg will take its course without the driver busy waiting for it to finish. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-08-07[TG3]: Fix tx race conditionMichael Chan
Fix a subtle race condition between tg3_start_xmit() and tg3_tx() discovered by Herbert Xu <herbert@gondor.apana.org.au>: CPU0 CPU1 tg3_start_xmit() if (tx_ring_full) { tx_lock tg3_tx() if (!netif_queue_stopped) netif_stop_queue() if (!tx_ring_full) update_tx_ring netif_wake_queue() tx_unlock } Even though tx_ring is updated before the if statement in tg3_tx() in program order, it can be re-ordered by the CPU as shown above. This scenario can cause the tx queue to be stopped forever if tg3_tx() has just freed up the entire tx_ring. The possibility of this happening should be very rare though. The following changes are made: 1. Add memory barrier to fix the above race condition. 2. Eliminate the private tx_lock altogether and rely solely on netif_tx_lock. This eliminates one spinlock in tg3_start_xmit() when the ring is full. 3. Because of 2, use netif_tx_lock in tg3_tx() before calling netif_wake_queue(). 4. Change TX_BUFFS_AVAIL to an inline function with a memory barrier. Herbert and David suggested using the memory barrier instead of volatile. 5. Check for the full wake queue condition before getting netif_tx_lock in tg3_tx(). This reduces the number of unnecessary spinlocks when the tx ring is full in a steady-state condition. 6. Update version to 3.65. Signed-off-by: Michael Chan <mchan@broadcom.com> Acked-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-30[TG3]: Add TSO workaround using GSOMichael Chan
Use GSO to workaround a rare TSO bug on some chips. This hardware bug may be triggered when the TSO header size is greater than 80 bytes. When this condition is detected in a TSO packet, the driver will use GSO to segment the packet to workaround the hardware bug. Thanks to Juergen Kreileder <jk@blackdown.de> for reporting the problem and collecting traces to help debug the problem. And thanks to Herbert Xu <herbert@gondor.apana.org.au> for providing the GSO mechanism that happens to be the perfect workaround for this problem. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-30[TG3]: Turn on hw fix for ASF problemsMichael Chan
Clear a bit to enable a hardware fix for some ASF related problem. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-30[TG3]: Add rx BD workaroundMichael Chan
Add workaround to limit the burst size of rx BDs being DMA'ed to the chip. This works around hardware errata on a number of 5750, 5752, and 5755 chips. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-17[TG3]: Convert to non-LLTXMichael Chan
Herbert Xu pointed out that it is unsafe to call netif_tx_disable() from LLTX drivers because it uses dev->xmit_lock to synchronize whereas LLTX drivers use private locks. Convert tg3 to non-LLTX to fix this issue. tg3 is a lockless driver where hard_start_xmit and tx completion handling can run concurrently under normal conditions. A tx_lock is only needed to prevent netif_stop_queue and netif_wake_queue race condtions when the queue is full. So whether we use LLTX or non-LLTX, it makes practically no difference. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-17[TG3]: Add recovery logic when MMIOs are re-orderedMichael Chan
Add recovery logic when we suspect that the system is re-ordering MMIOs. Re-ordered MMIOs to the send mailbox can cause bogus tx completions and hit BUG_ON() in the tx completion path. tg3 already has logic to handle re-ordered MMIOs by flushing the MMIOs that must be strictly ordered (such as the send mailbox). Determining when to enable the flush is currently a manual process of adding known chipsets to a list. The new code replaces the BUG_ON() in the tx completion path with the call to tg3_tx_recover(). It will set the TG3_FLAG_MBOX_WRITE_REORDER flag and reset the chip later in the workqueue to recover and start flushing MMIOs to the mailbox. A message to report the problem will be printed. We will then decide whether or not to add the host bridge to the list of chipsets that do re-ordering. We may add some additional code later to print the host bridge's ID so that the user can report it more easily. The assumption that re-ordering can only happen on x86 systems is also removed. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-09[TG3]: Handle Sun onboard tg3 chips more correctly.David S. Miller
Get rid of all the SUN_570X logic and instead: 1) Make sure MEMARB_ENABLE is set when we probe the SRAM for config information. If that is off we will get timeouts. 2) Always try to sync with the firmware, if there is no firmware running do not treat it as an error and instead just report it the first time we notice this condition. 3) If there is no valid SRAM signature, assume the device is onboard by setting TG3_FLAG_EEPROM_WRITE_PROT. Update driver version and release date. With help from Michael Chan and Fabio Massimo Di Nitto. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-04-29[TG3]: Add phy workaroundMichael Chan
Add some PHY workaround code to reduce jitter on some PHYs. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-04-09[TG3]: Speed up SRAM access (2nd version)Michael Chan
Speed up SRAM read and write functions if possible by using MMIO instead of config. cycles. With this change, the post reset signature done at the end of D3 power change must now be moved before the D3 power change. IBM reported a problem on powerpc blades during ethtool self test that was caused by the memory test taking excessively long. Config. cycles are very slow on powerpc and the memory test can take more than 10 seconds to complete using config. cycles. David Miller informed me that an earlier version of the patch caused problems on sparc64 systems with built-in tg3 chips. This version fixes the problem by excluding all SUN built-in tg3 chips from doing MMIO SRAM access. TG3_FLAG_EEPROM_WRITE_PROT is also set unconditionally when TG3_FLG2_SUN_570X is set. This should be sane as all SUN chips are built-in and do not require Vaux switching. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-04-09[TG3]: Kill some less useful flagsMichael Chan
Kill the TG3_FLAG_NO_{TX|RX}_PSEUDO_CSUM flags because they are not very useful. This will free up some bits for new flags. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-23[TG3]: Add 5755 nvram supportMichael Chan
Add 5755 nvram support. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-23[TG3]: Add 5755 supportMichael Chan
Add support for new chip 5755 which is very similar to 5787. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>