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path: root/drivers/pci
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2008-06-12PCI: fixup write combine comment in pci_mmap_resourceJesse Barnes
Now that we can actually do write combining properly, there's no need to have the FIXME. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-06-12Merge branch 'pci-for-jesse' of ↵Jesse Barnes
git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-tip into for-linus
2008-06-12x86: PAT export resource_wc in pci sysfsvenkatesh.pallipadi@intel.com
For the ranges with IORESOURCE_PREFETCH, export a new resource_wc interface in pci /sysfs along with resource (which is uncached). Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-30PCI: fix rpadlpar pci hotplug driver sysfs usageBenjamin Herrenschmidt
When Greg "fixed" the sysfs usage of that driver a while back, he seem to have introduced a bug where the quotes are added around the name of our specific sysfs files, thus breaking the user space tool. This fixes it. Tested DLPAR operations on a POWER6 machine successfully. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-27pciehp: add message about pciehp_slot_with_bus optionKenji Kaneshige
Some (broken?) platform assign the same slot name to multiple hotplug slots. On such system, slot initialization would fail because of name collision. The pciehp driver already have a "slot_with_bus" module option which adds the bus number into the slot name. This patch adds the message about this module option that will be displayed when slot name collision is detected. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-27pci hotplug core: add check of duplicate slot nameKenji Kaneshige
Fix the following errors reported by Jan C. Nordholz in http://bugzilla.kernel.org/show_bug.cgi?id=10751. kobject_add_internal failed for 2 with -EEXIST, don't try to register things with the same name in the same directory. Pid: 1, comm: swapper Tainted: G W 2.6.26-rc3 #1 [<c0266980>] kobject_add_internal+0x140/0x190 [<c0266afd>] kobject_init_and_add+0x2d/0x40 [<c027bc91>] pci_hp_register+0x81/0x2f0 [<c027fd07>] pciehp_probe+0x1a7/0x470 [<c01b3b84>] sysfs_add_one+0x44/0xa0 [<c01b3c1f>] sysfs_addrm_start+0x3f/0xb0 [<c01b497a>] sysfs_create_link+0x8a/0xf0 [<c0279570>] pcie_port_probe_service+0x50/0x80 [<c02e0545>] driver_sysfs_add+0x55/0x70 [<c02e0662>] driver_probe_device+0x82/0x180 [<c02e07cc>] __driver_attach+0x6c/0x70 [<c02dfe0a>] bus_for_each_dev+0x3a/0x60 [<c05db2d0>] pcied_init+0x0/0x80 [<c02e04e6>] driver_attach+0x16/0x20 [<c02e0760>] __driver_attach+0x0/0x70 [<c02e0341>] bus_add_driver+0x1a1/0x220 [<c05db2d0>] pcied_init+0x0/0x80 [<c02e09cd>] driver_register+0x4d/0x120 [<c05db050>] ibm_acpiphp_init+0x0/0x190 [<c0125aab>] printk+0x1b/0x20 [<c05db2d0>] pcied_init+0x0/0x80 [<c05db2de>] pcied_init+0xe/0x80 [<c05c751a>] kernel_init+0x10a/0x300 [<c0120138>] schedule_tail+0x18/0x50 [<c0103b9a>] ret_from_fork+0x6/0x1c [<c05c7410>] kernel_init+0x0/0x300 [<c05c7410>] kernel_init+0x0/0x300 [<c010485b>] kernel_thread_helper+0x7/0x1c ======================= pci_hotplug: Unable to register kobject '2'<3>pciehp: pci_hp_register failed with error -22 Slot with the same name can be registered multiple times if shpchp or pciehp driver is loaded after acpiphp is loaded because ACPI based hotplug driver and Native OS hotplug driver trying to handle the same physical slot. In this case, current pci_hotplug core will call kobject_init_and_add() muliple time with the same name. This is the cause of this problem. To fix this problem, this patch adds the check into pci_hp_register() to see if the slot with the same name. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-27pciehp: move msleep after power offKenji Kaneshige
According to the PCI Express specification, we must wait for at least 1 second after turning power off before taking any action that relies on power having been removed from the slot/adapter. For this, current pciehp wait for 1 second after issuing the power off command in hpc_power_off_slot() function. But waiting for 1 second in hpc_power_off_slot() can make pciehp probing slow-down because pciehp probe code calls hpc_power_off_slot() if the slot is not occupied just in case. We don't need to wait for 1 second at the pciehp probe time because there is no action on that empty slot. So move 1 second wait from hpc_power_off_slot() to the caller of hpc_power_off_slot(). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-27pciehp: poll cmd completion if hotplug interrupt is disabledKenji Kaneshige
Fix improper long wait for command completion in pciehp probing. As described in PCI Express specification, software notification is not generated if the command that occurs as a result of a write to the Slot Control register that disables software notification of command completed events. Since pciehp driver doesn't take it into account, such command is issued in pciehp probing, and it causes improper long wait for command completion. This patch changes the pciehp driver to take such command into account. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-27pciehp: fix slow probingKenji Kaneshige
Fix the "pciehp probing slow" problem reported from Jan C. Nordholz in http://bugzilla.kernel.org/show_bug.cgi?id=10751. The command completed bit in Slot Status register applies only to commands issued to control the attention indicator, power indicator, power controller, or electromechanical interlock. However, writes to other parts of the Slot Control register would end up writing to the control fields. Hence, any write to Slot Control register is considered as a command. However, if the controller doesn't support any of attention indicator, power indicator, power controller and electromechanical interlock, command completed bit would not set in writing to Slot Control register. In this case, we should not wait for command completed bit set, otherwise all commands would be considered not completed in timeout seconds (1 sec.). The cause of the problem is pciehp driver didn't take this situation into account. This patch changes pciehp to take it into account. This patch also add the check for "No Command Completed Support" bit in Slot Capability register. If it is set, we should not wait for command completed bit set as well. This problem seems to be revealed by the commit c27fb883dffe11aa4cb35ecea1fa1832ba45d4da that fixed the bug that pciehp did not wait for command completed properly (pciehp just ignored the command completion event). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-27pciehp: fix NULL dereference in interrupt handlerKenji Kaneshige
Fix the following NULL dereference problem reported from Pierre Ossman and Ingo Molnar. pciehp: HPC vendor_id 8086 device_id 27d0 ss_vid 0 ss_did 0 pciehp: pciehp_find_slot: slot (device=0x0) not found BUG: unable to handle kernel NULL pointer dereference at 0000000000000070 IP: [<ffffffff80494a8b>] pciehp_handle_presence_change+0x7e/0x113 PGD 0 Oops: 0000 [1] CPU 0 Modules linked in: Pid: 1, comm: swapper Tainted: G W 2.6.26-rc3-sched-devel.git-00001-g2b99b26-dirty #170 RIP: 0010:[<ffffffff80494a8b>] [<ffffffff80494a8b>] pciehp_handle_presence_change+0x7e/0x113 RSP: 0000:ffff81003f83fbb0 EFLAGS: 00010046 RAX: 0000000000000039 RBX: 0000000000000000 RCX: 0000000000000000 RDX: 0000000000000000 RSI: 0000000000000001 RDI: 0000000000000046 RBP: ffff81003f83fbd0 R08: 0000000000000001 R09: ffffffff80245103 R10: 0000000000000020 R11: 0000000000000000 R12: ffff81003ea53a30 R13: 0000000000000000 R14: 0000000000000011 R15: ffffffff80495926 FS: 0000000000000000(0000) GS:ffffffff80be7400(0000) knlGS:0000000000000000 CS: 0010 DS: 0018 ES: 0018 CR0: 000000008005003b CR2: 0000000000000070 CR3: 0000000000201000 CR4: 00000000000006a0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process swapper (pid: 1, threadinfo ffff81003f83e000, task ffff81003f840000) Stack: 0000000000000008 ffff81003f83fbf6 ffff81003ea53a30 0000000000000008 ffff81003f83fc10 ffffffff80495ab4 0000000000000011 0000000000000002 0000000000000202 0000000000000202 00000000fffffff4 ffff81003ea53a30 Call Trace: [<ffffffff80495ab4>] pcie_isr+0x18e/0x1bc [<ffffffff80260831>] request_irq+0x106/0x12f [<ffffffff80495fb6>] pcie_init+0x15e/0x6cc [<ffffffff804933a3>] pciehp_probe+0x64/0x541 [<ffffffff8048f4e7>] pcie_port_probe_service+0x4c/0x76 [<ffffffff8054af70>] driver_probe_device+0xd4/0x1f0 [<ffffffff8054b108>] __driver_attach+0x7c/0x7e [<ffffffff8054b08c>] ? __driver_attach+0x0/0x7e [<ffffffff8054a4b6>] bus_for_each_dev+0x53/0x7d [<ffffffff8054ad3c>] driver_attach+0x1c/0x1e [<ffffffff8054a9c2>] bus_add_driver+0xdd/0x25b [<ffffffff80c09d3d>] ? pcied_init+0x0/0x8b [<ffffffff8054b288>] driver_register+0x5f/0x13e [<ffffffff80c09d3d>] ? pcied_init+0x0/0x8b [<ffffffff8048f441>] pcie_port_service_register+0x47/0x49 [<ffffffff80c09d52>] pcied_init+0x15/0x8b [<ffffffff80bf3938>] kernel_init+0x75/0x243 [<ffffffff808639d2>] ? _spin_unlock_irq+0x2b/0x3a [<ffffffff80228d1f>] ? finish_task_switch+0x57/0x9a [<ffffffff8020c258>] child_rip+0xa/0x12 [<ffffffff8020bcec>] ? restore_args+0x0/0x30 [<ffffffff80bf38c3>] ? kernel_init+0x0/0x243 [<ffffffff8020c24e>] ? child_rip+0x0/0x12 Code: 83 80 00 00 00 48 39 f0 75 e1 0f b6 c9 48 c7 c2 00 0e 8d 80 48 c7 c6 8a 60 a6 80 48 c7 c7 10 db a8 80 31 c0 e8 3f 8d d9 ff 31 db <48> 8b 43 70 48 8d 75 ef 48 89 df ff 50 30 80 7d ef 00 74 37 48 RIP [<ffffffff80494a8b>] pciehp_handle_presence_change+0x7e/0x113 RSP <ffff81003f83fbb0> CR2: 0000000000000070 Kernel panic - not syncing: Fatal exception The situation under which it occurs is hw and timing related: it appears to happen on a system that has PCI hotplug hardware but with no active hotplug cards, and another interrupt in the same (shared) IRQ line arrives too early, before the hotplug-slot entry has been set up - as triggered by CONFIG_DEBUG_SHIRQ=y: This patch contains the following two fixes. (1) Clear all events bits in Slot Status register to prevent the pciehp driver from detecting the spurious events that would have been occur before pciehp loading. (2) Add check whether slot initialization had been already done. This is short term fix. We need more structural fixes to install interrupt handler after slot initialization is done. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-27shpchp: add message about shpchp_slot_with_bus optionKenji Kaneshige
Some (broken?) platform assign the same slot name to multiple hotplug slots. On such system, slot initialization would fail because of name collision. The shpchp driver already have a "slot_with_bus" module option which adds the bus number into the slot name. This patch adds the message about this module option that will be displayed when slot name collision is detected. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-24PCI: use dev_to_node in pci_call_probeYinghai Lu
to make sure get one online node. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-21PCI: don't enable ASPM on devices with mixed PCIe/PCI functionsShaohua Li
The Slot 03:00.* of JMicron controller has two functions, but one is PCIE endpoint the other isn't PCIE device, very strange. PCIE spec defines all functions should have the same config for ASPM, so disable ASPM for the whole slot in this case. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-15Clean up 'print_fn_descriptor_symbol()' typesLinus Torvalds
Everybody wants to pass it a function pointer, and in fact, that is what you _must_ pass it for it to make sense (since it knows that ia64 and ppc64 use descriptors for function pointers and fetches the actual address from there). So don't make the argument be a 'unsigned long' and force everybody to add a cast. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-05-13ACPI/PCI: another multiple _OSC memory leak fixKenji Kaneshige
The acpi_query_osc() function can be called for the ACPI object that doesn't have _OSC method. In this case, acpi_get_osc_data() would allocate a useless memory region. To avoid this, we need to check the existence of _OSC before calling acpi_get_osc_data() in acpi_query_osc(). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-13PCI: enable nv_msi_ht_cap_quirk for ALi bridgesBjörn Krombholz
This applies the NVidia MSI enabled flag for HT capable devices quirk to ALi bridges as well. As described in more detail in http://bugzilla.kernel.org/show_bug.cgi?id=10667 this is required for my board which is using an nForce 3 250Gb chipset with an ALi M1695 northbridge. It fixes a regression introduced in 2.6.24 that made the internal NIC of the board unusable (MSI initialisation of the NIC but disabled MSI on the northbridge devices. Signed-off-by: Björn Krombholz <fox.box@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-13PCI: Make the intel-iommu_wait_op macro work when jiffies are not runningmark gross
The following patch changes the intel-iommu.c code to use the TSC instead of jiffies for detecting bad DMAR functionality. Some systems with bad bios's have been seen to hang in early boot spinning in the IOMMU_WAIT_IO macro. This patch will replace the infinite loop with a call to panic. Signed-off-by: Mark Gross <mgross@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-13ACPI/PCI: handle multiple _OSCKenji Kaneshige
The pci_osc_control_set() function can be called for the ACPI object that doesn't have _OSC method. In this case, acpi_get_osc_data() would allocate a useless memory region. To avoid this, we need to check the existence of _OSC before calling acpi_get_osc_data(). Here is a patch to fix this problem in pci_osc_control_set. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-13ACPI/PCI: handle multiple _OSCShaohua Li
There is an IA64 system here which have two pci root bridges with _OSC. One _OSC disables SHPC control bit but the other not. Below patch makes _OSC data per-device instead of one global, otherwise linux takes both root bridges don't support SHPC. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-05-13PCI ACPI: fix uninitialized variable in __pci_osc_support_setKenji Kaneshige
Fix uninitialized variable in __pci_osc_support_set(). If the ACPI namespace doesn't have any device object corresponding to the specified hid, 'retval' in __pci_osc_support_set() is not changed by the acpi_query_osc() callback. Since 'retval' is not initizlized in the current implementation, the contents of 'retval' is undefined in this case. This causes a mis-handling of ctrlset_buf[OSC_SUPPORT_TYPE] and will cause an unexpected result in the subsequent pci_osc_control_set() call as a result. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-29x86/pci: remove flag in pci_cfg_space_size_extYinghai Lu
so let pci_cfg_space_size call it directly without flag. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-29Merge branch 'for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (21 commits) pciehp: fix error message about getting hotplug control pci/irq: let pci_device_shutdown to call pci_msi_shutdown v2 pci/irq: restore mask_bits in msi shutdown -v3 doc: replace yet another dev with pdev for consistency in DMA-mapping.txt PCI: don't expose struct pci_vpd to userspace doc: fix an incorrect suggestion to pass NULL for PCI like buses Consistently use pdev as the variable of type struct pci_dev *. pciehp: Fix command write shpchp: fix slot name make pciehp_acpi_get_hp_hw_control_from_firmware() pciehp: Clean up pcie_init() pciehp: Mask hotplug interrupt at controller release pciehp: Remove useless hotplug interrupt enabling pciehp: Fix wrong slot capability check pciehp: Fix wrong slot control register access pciehp: Add missing memory barrier pciehp: Fix interrupt event handlig pciehp: fix slot name Update MAINTAINERS with location of PCI tree PCI: Add Intel SCH PCI IDs ...
2008-04-29pciehp: fix error message about getting hotplug controlKenji Kaneshige
People are confused by the following error message that actually is not for indicating a error. Cannot get control of hotplug hardware for pci %s This patch changes this message to debug message. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan>
2008-04-29pci/irq: let pci_device_shutdown to call pci_msi_shutdown v2Yinghai Lu
[PATCH 2/2] pci/irq: let pci_device_shutdown to call pci_msi_shutdown v2 this change | commit 23a274c8a5adafc74a66f16988776fc7dd6f6e51 | Author: Prakash, Sathya <sathya.prakash@lsi.com> | Date: Fri Mar 7 15:53:21 2008 +0530 | | [SCSI] mpt fusion: Enable MSI by default for SAS controllers | | This patch modifies the driver to enable MSI by default for all SAS chips. | | Signed-off-by: Sathya Prakash <sathya.prakash@lsi.com> | Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com> | Causes the kexec of a RHEL 5.1 kernel to fail. root casue: the rhel 5.1 kernel still uses INTx emulation. and mptscsih_shutdown doesn't call pci_disable_msi to reenable INTx on kexec path So call pci_msi_shutdown in the shutdown path to do the same thing to msix Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan>
2008-04-29pci/irq: restore mask_bits in msi shutdown -v3Yinghai Lu
[PATCH 1/2] pci/irq: restore mask_bits in msi shutdown -v3 Yinghai found that kexec'ing a RHEL 5.1 kernel with 2.6.25-rc3+ kernels prevents his NIC from working. He bisected to | commit 89d694b9dbe769ca1004e01db0ca43964806a611 | Author: Thomas Gleixner <tglx@linutronix.de> | Date: Mon Feb 18 18:25:17 2008 +0100 | | genirq: do not leave interupts enabled on free_irq | | The default_disable() function was changed in commit: | | 76d2160147f43f982dfe881404cfde9fd0a9da21 | genirq: do not mask interrupts by default | For MSI, default_shutdown will call mask_bit for msi device. All mask bits will left disabled after free_irq. Then in the kexec case, the next kernel can only use msi_enable bit, so all device's MSI can not be used. So lets to restore the mask bit to its pci reset defined value (enabled) when we disable the kernels use of msi to be a little friendlier to kexec'd kernels. Extend msi_set_mask_bit to msi_set_mask_bits to take mask, so we can fully restore that to 0x00 instead of 0xfe. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan>
2008-04-29Merge branch 'for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86-bigbox-pci * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86-bigbox-pci: x86: add pci=check_enable_amd_mmconf and dmi check x86: work around io allocation overlap of HT links acpi: get boot_cpu_id as early for k8_scan_nodes x86_64: don't need set default res if only have one root bus x86: double check the multi root bus with fam10h mmconf x86: multi pci root bus with different io resource range, on 64-bit x86: use bus conf in NB conf fun1 to get bus range on, on 64-bit x86: get mp_bus_to_node early x86 pci: remove checking type for mmconfig probe x86: remove unneeded check in mmconf reject driver core: try parent numa_node at first before using default x86: seperate mmconf for fam10h out from setup_64.c x86: if acpi=off, force setting the mmconf for fam10h x86_64: check MSR to get MMCONFIG for AMD Family 10h x86_64: check and enable MMCONFIG for AMD Family 10h x86_64: set cfg_size for AMD Family 10h in case MMCONFIG x86: mmconf enable mcfg early x86: clear pci_mmcfg_virt when mmcfg get rejected x86: validate against acpi motherboard resources Fixed up fairly trivial conflicts in arch/x86/pci/{init.c,pci.h} due to OLPC support manually.
2008-04-29drivers: use non-racy method for proc entries creation (2)Denis V. Lunev
Use proc_create()/proc_create_data() to make sure that ->proc_fops and ->data be setup before gluing PDE to main tree. Signed-off-by: Denis V. Lunev <den@openvz.org> Cc: Greg Kroah-Hartman <gregkh@suse.de> Cc: Alexey Dobriyan <adobriyan@gmail.com> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Cc: Peter Osterlund <petero2@telia.com> Cc: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Cc: Dmitry Torokhov <dtor@mail.ru> Cc: Neil Brown <neilb@suse.de> Cc: Mauro Carvalho Chehab <mchehab@infradead.org> Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Alessandro Zummo <a.zummo@towertech.it> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-04-29proc: remove proc_busAlexey Dobriyan
Remove proc_bus export and variable itself. Using pathnames works fine and is slightly more understandable and greppable. Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-04-28drivers: fix integer as NULL pointer warningsHarvey Harrison
Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-04-26x86: multi pci root bus with different io resource range, on 64-bitYinghai Lu
scan AMD opteron io/mmio routing to make sure every pci root bus get correct resource range. Thus later pci scan could assign correct resource to device with unassigned resource. this can fix a system without _CRS for multi pci root bus. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-04-26driver core: try parent numa_node at first before using defaultYinghai Lu
in the device_add, we try to use use parent numa_node. need to make sure pci root bus's bridge device numa_node is set. then we could use device->numa_node direclty for all device. and don't need to call pcibus_to_node(). Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-04-26x86_64: set cfg_size for AMD Family 10h in case MMCONFIGYinghai Lu
reuse pci_cfg_space_size but skip check pci express and pci-x CAP ID. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Cc: Andrew Morton <akpm@linux-foundation.org> Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-04-25pciehp: Fix command writeKenji Kaneshige
Current implementation of pciehp_write_cmd() always enables command completed interrupt. But pciehp_write_cmd() is also used for clearing command completed interrupt enable bit. In this case, we must not set the command completed interrupt enable bit. To fix this bug, this patch add the check to see if caller wants to change command complete interrupt enable bit. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-25shpchp: fix slot nameKenji Kaneshige
Current shpchp uses the combination of bus number and slot number as a slot name. But it is not a good idea because bus number is not a physical identifier but a logical identifier. This is against the shpc specification. So remove the bus number from the physical identifier. However, there are some platforms with the problem that it provides the same slot number. For those platforms, this patch also introduces new module option 'shpchp_slot_with_bus'. If it is specified, shpchp uses the combination of bus number and slot number as a slot name. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-25make pciehp_acpi_get_hp_hw_control_from_firmware()Adrian Bunk
this_patch_makes_the_needlessly_global_pciehp_acpi_get_hp_hw_control_from_firmware_static ;) Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-25pciehp: Clean up pcie_init()Kenji Kaneshige
Clean up pciehp_ini(). This patch is trying to - Remove redundant capablity checks that were already done in PCIe port bus driver. - Separate the code only for debugging and make debug information easier to read. - Make the entire code easier to read and understand what it is doing. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-25pciehp: Mask hotplug interrupt at controller releaseKenji Kaneshige
We must disable hotplug interrupt at controller relase time, otherwise spurious interrupts might happen if any slot events occured (e.g. MRL change) after unloading pciehp driver. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-25pciehp: Remove useless hotplug interrupt enablingKenji Kaneshige
Hotplug interrupt is enabled at initialization and nobody clears it. So we need to setup it in each command. This patch removes redundant codes about this. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-25pciehp: Fix wrong slot capability checkKenji Kaneshige
Current pciehp saves only 8bits of Slot Capability registers in ctrl->ctrlcap. But it refers more than 8bit for checking EMI capability. It is clearly a bug and EMI would never work. To fix this problem, this patch saves full Slot Capability contens in ctrl->slot_cap. It also reduce the redundant reads of Slot Capability register. And this pach also cleans up the macros to check the slot capabilitys (e.g. MRL_SENS(), and so on). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-25pciehp: Fix wrong slot control register accessKenji Kaneshige
Current pciehp implementaion clears hotplug events without waiting for command completion. Because of this, events might not be cleared properly. To prevent this problem, we must use pciehp_write_cmd() to write to Slot Control register. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-25pciehp: Add missing memory barrierKenji Kaneshige
Fix the possible race condition between pcie_isr() and pciehp_write_cmd() because of the lack of memory barrier. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-25pciehp: Fix interrupt event handligKenji Kaneshige
Current pciehp implementation disables and re-enables hotplug interrupts in its interrupt handler. This operation might be intend to guarantee that interrupts for the events newly occured during previous events are being handled will be successfully generated. But current implementaion has the following prolems. - Current interrupt service routin clears status changes without waiting command completion. Because of this, events might not be cleared properly. - Current interrupt service routine clears status changes caused by disabling or enabling hotplug interrupts itself. This will lose new events that occurs during previous interrupts are being handled. - Current implementation doesn't have any serialization mechanism between the code to wait for command completion and the interrupt handler that clears the command completion events caused by itself. There is clearly race conditions between them, and it may cause the problem that waiting for command completion doesn't work for example. To fix those problems, this patch stops disabling/re-enabling hotplug interrupts in interrupt service routine. Instead of this, this patch re-inspects Slot Status register after clearing what is presumed to be the last bending interrupt in order to guarantee that all interrupt events are serviced. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-25pciehp: fix slot nameKenji Kaneshige
Current pciehp uses the combination of bus number and slot number as a slot name. But it is not a good idea because bus number is not a physical identifier but a logical identifier. This is against the PCIE specification. So remove the bus number from the physical identifier. However, there are some platforms with the problem that it provides the same slot number. For those platforms, this patch also introduces new module option 'pciehp_slot_with_bus'. If it is specified, pciehp uses the combination of bus number and slot number as a slot name. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-24intel-iommu.c: dma ops fixIngo Molnar
Stephen Rothwell noticed that: Commit 2be621498d461b63ca6124f86e3b9582e1a8e722 ("x86: dma-ops on highmem fix") in Linus' tree introduced a new warning (noticed in the x86_64 allmodconfig build of linux-next): drivers/pci/intel-iommu.c:2240: warning: initialization from incompatible pointer type Which points at an instance of map_single that needs updating. Fix it to the new prototype. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-04-23PCI Express ASPM support should default to 'No'Jesper Juhl
Running 'make oldconfig' I just noticed that PCIEASPM defaults to 'y' in Kconfig even though the feature is both experimental and the help text recommends that if you are unsure you say 'n'. It seems to me that this really should default to 'n', not 'y' at the moment. The following patch makes that change. Please consider applying. Signed-off-by: Jesper Juhl <jesper.juhl@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-04-22Fix cardbus resource allocationLinus Torvalds
Commit 884525655d07fdee9245716b998ecdc45cdd8007 ("PCI: clean up resource alignment management") didn't set the alignment information for the cardbus window resources, causing their subsequent allocations to fail miserably with a message like yenta_cardbus 0000:15:00.0: device not available because of BAR 7 [100:1ff] collisions yenta_cardbus: probe of 0000:15:00.0 failed with error -16 or similar. This fixes it and clarifies the code a bit too (we used to have to use the insane PCI bridge alignment logic that put the alignment in the "start" field, this makes it use the slightly easier-to-understand size-based alignment, and allows us to set the resource start to zero until it gets allocated). Reported-and-tested-by: Jeff Chua <jeff.chua.linux@gmail.com> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-04-21Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6Linus Torvalds
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6: (42 commits) PCI: Change PCI subsystem MAINTAINER PCI: pci-iommu-iotlb-flushing-speedup PCI: pci_setup_bridge() mustn't be __devinit PCI: pci_bus_size_cardbus() mustn't be __devinit PCI: pci_scan_device() mustn't be __devinit PCI: pci_alloc_child_bus() mustn't be __devinit PCI: replace remaining __FUNCTION__ occurrences PCI: Hotplug: fakephp: Return success, not ENODEV, when bus rescan is triggered PCI: Hotplug: Fix leaks in IBM Hot Plug Controller Driver - ibmphp_init_devno() PCI: clean up resource alignment management PCI: aerdrv_acpi.c: remove unneeded NULL check PCI: Update VIA CX700 quirk PCI: Expose PCI VPD through sysfs PCI: iommu: iotlb flushing PCI: simplify quirk debug output PCI: iova RB tree setup tweak PCI: parisc: use generic pci_enable_resources() PCI: ppc: use generic pci_enable_resources() PCI: powerpc: use generic pci_enable_resources() PCI: ia64: use generic pci_enable_resources() ...
2008-04-20PCI: pci-iommu-iotlb-flushing-speedupmark gross
The following patch is an update to use an array instead of a list of IOVA's in the implementation of defered iotlb flushes. It takes inspiration from sba_iommu.c I like this implementation better as it encapsulates the batch process within intel-iommu.c, and no longer touches iova.h (which is shared) Performance data: Netperf 32byte UDP streaming 2.6.25-rc3-mm1: IOMMU-strict : 58Mps @ 62% cpu NO-IOMMU : 71Mbs @ 41% cpu List-based IOMMU-default-batched-IOTLB flush: 66Mbps @ 57% cpu with this patch: IOMMU-strict : 73Mps @ 75% cpu NO-IOMMU : 74Mbs @ 42% cpu Array-based IOMMU-default-batched-IOTLB flush: 72Mbps @ 62% cpu Signed-off-by: <mgross@linux.intel.com> Cc: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2008-04-20PCI: pci_setup_bridge() mustn't be __devinitAdrian Bunk
WARNING: drivers/pci/built-in.o(.text+0x28ee9): Section mismatch in reference from the function pci_bus_assign_resources() to the function .devinit.text:pci_setup_bridge() Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2008-04-20PCI: pci_bus_size_cardbus() mustn't be __devinitAdrian Bunk
WARNING: drivers/pci/built-in.o(.text+0x28e1f): Section mismatch in reference from the function pci_bus_size_bridges() to the function .devinit.text:pci_bus_size_cardbus() Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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