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path: root/drivers/spi/spi_bitbang.c
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2006-06-30Remove obsolete #include <linux/config.h>Jörn Engel
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-05-16[PATCH] SPI: spi_bitbang: clocking fixesDavid Brownell
This fixes two problems triggered by the MMC stack updating clocks: - SPI masters driver should accept a max clock speed of zero; that's one convention for marking idle devices. (Presumably that helps controllers that don't autogate clocks to "off" when not in use.) - There are more than 1000 nanoseconds per millisecond; setting the clock down to 125 KHz now works properly. Showing once again that Zero (http://en.wikipedia.org/wiki/Zero) is still an inexhaustible number of bugs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-05-16[PATCH] SPI: devices can require LSB-first encodingsDavid Brownell
Add spi_device hook for LSB-first word encoding, and update all the (in-tree) controller drivers to reject such devices. Eventually, some controller drivers will be updated to support lsb-first encodings on the wire; no current drivers need this. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-05-16[PATCH] SPI: Renamed bitbang_transfer_setup to spi_bitbang_setup_transfer ↵Kumar Gala
and export it Renamed bitbang_transfer_setup to follow convention of other exported symbols from spi-bitbang. Exported spi_bitbang_setup_transfer to allow users of spi-bitbang to use the function in their own setup_transfer. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Cc: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-05-16[PATCH] SPI: per-transfer overrides for wordsize and clockingImre Deak
Some protocols (like one for some bitmap displays) require different clock speed or word size settings for each transfer in an SPI message. This adds those parameters to struct spi_transfer. They are to be used when they are nonzero; otherwise the defaults from spi_device are to be used. The patch also adds a setup_transfer callback to spi_bitbang, uses it for messages that use those overrides, and implements it so that the pure bitbanging code can help resolve any questions about how it should work. Signed-off-by: Imre Deak <imre.deak@nokia.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-13[PATCH] spi: use linked lists rather than an arrayVitaly Wool
This makes the SPI core and its users access transfers in the SPI message structure as linked list not as an array, as discussed on LKML. From: David Brownell <dbrownell@users.sourceforge.net> Updates including doc, bugfixes to the list code, add spi_message_add_tail(). Plus, initialize things _before_ grabbing the locks in some cases (in case it grows more expensive). This also merges some bitbang updates of mine that didn't yet make it into the mm tree. Signed-off-by: Vitaly Wool <vwool@ru.mvista.com> Signed-off-by: Dmitry Pervushin <dpervushin@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-13[PATCH] spi: add spi_bitbang driverDavid Brownell
This adds a bitbanging spi master, hooking up to board/adapter-specific glue code which knows how to set and read the signals (gpios etc). This code kicks in after the glue code creates a platform_device with the right platform_data. That data includes I/O loops, which will usually come from expanding an inline function (provided in the header). One goal is that the I/O loops should be easily optimized down to a few GPIO register accesses, in common cases, for speed and minimized overhead. This understands all the currently defined protocol tweaking options in the SPI framework, and might eventually serve as as reference implementation. - different word sizes (1..32 bits) - differing clock rates - SPI modes differing by CPOL (affecting chip select and I/O loops) - SPI modes differing by CPHA (affecting I/O loops) - delays (usecs) after transfers - temporarily deselecting chips in mid-transfer A lot of hardware could work with this framework, though common types of controller can't reach peak performance without switching to a driver structure that supports pipelining of transfers (e.g. DMA queues) and maybe controllers (e.g. IRQ driven). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>