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/*
* STMP APBH Register Definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ARCH_ARM___APBH_H
#define __ARCH_ARM___APBH_H 1
#include <mach/stmp3xxx_regs.h>
#define REGS_APBH_BASE (REGS_BASE + 0x4000)
#define REGS_APBH_BASE_PHYS (0x80004000)
#define REGS_APBH_SIZE 0x00002000
HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00000000)
#define HW_APBH_CTRL0_ADDR (REGS_APBH_BASE + 0x00000000)
#define BM_APBH_CTRL0_SFTRST 0x80000000
#define BM_APBH_CTRL0_CLKGATE 0x40000000
#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000
#define BM_APBH_CTRL0_APB_BURST4_EN 0x10000000
#define BP_APBH_CTRL0_RESET_CHANNEL 16
#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
#define BF_APBH_CTRL0_RESET_CHANNEL(v) \
(((v) << 16) & BM_APBH_CTRL0_RESET_CHANNEL)
HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x00000010)
#define HW_APBH_CTRL1_ADDR (REGS_APBH_BASE + 0x00000010)
HW_REGISTER(HW_APBH_CTRL2, REGS_APBH_BASE, 0x00000020)
HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x00000030)
HW_REGISTER_0_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x00000040, 0x70)
#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0
#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF
#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v)
HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x00000050, 0x70)
HW_REGISTER_0_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x00000060, 0x70)
#define BP_APBH_CHn_CMD_XFER_COUNT 16
#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
#define BF_APBH_CHn_CMD_XFER_COUNT(v) \
(((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT)
#define BP_APBH_CHn_CMD_CMDWORDS 12
#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
#define BF_APBH_CHn_CMD_CMDWORDS(v) \
(((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS)
#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100
#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
#define BM_APBH_CHn_CMD_CHAIN 0x00000004
#define BP_APBH_CHn_CMD_COMMAND 0
#define BM_APBH_CHn_CMD_COMMAND 0x00000003
#define BF_APBH_CHn_CMD_COMMAND(v) \
(((v) << 0) & BM_APBH_CHn_CMD_COMMAND)
#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1
#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2
#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3
HW_REGISTER_0_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x00000070, 0x70)
HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x00000080, 0x70)
#define BP_APBH_CHn_SEMA_PHORE 16
#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
#define BF_APBH_CHn_SEMA_PHORE(v) \
(((v) << 16) & BM_APBH_CHn_SEMA_PHORE)
#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \
(((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA)
HW_REGISTER_0_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x00000090, 0x70)
HW_REGISTER_0_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0x000000a0, 0x70)
HW_REGISTER_0(HW_APBH_VERSION, REGS_APBH_BASE, 0x000003f0)
#endif /* __ARCH_ARM___APBH_H */
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