blob: dc7ab9c80611567baa497dffbe42d89e040e68e8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
|
/*
* MPC885 ADS Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/ {
model = "MPC885ADS";
compatible = "mpc8xx";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,885@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <2000>; // L1, 8K
i-cache-size = <2000>; // L1, 8K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
};
memory {
device_type = "memory";
reg = <00000000 800000>;
};
soc885@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
bus-frequency = <0>;
mdio@e80 {
device_type = "mdio";
compatible = "fs_enet";
reg = <e80 8>;
#address-cells = <1>;
#size-cells = <0>;
Phy0: ethernet-phy@0 {
reg = <0>;
device_type = "ethernet-phy";
};
Phy1: ethernet-phy@1 {
reg = <1>;
device_type = "ethernet-phy";
};
Phy2: ethernet-phy@2 {
reg = <2>;
device_type = "ethernet-phy";
};
};
fec@e00 {
device_type = "network";
compatible = "fs_enet";
model = "FEC";
device-id = <1>;
reg = <e00 188>;
mac-address = [ 00 00 0C 00 01 FD ];
interrupts = <3 1>;
interrupt-parent = <&Mpc8xx_pic>;
phy-handle = <&Phy1>;
};
fec@1e00 {
device_type = "network";
compatible = "fs_enet";
model = "FEC";
device-id = <2>;
reg = <1e00 188>;
mac-address = [ 00 00 0C 00 02 FD ];
interrupts = <7 1>;
interrupt-parent = <&Mpc8xx_pic>;
phy-handle = <&Phy2>;
};
Mpc8xx_pic: pic@ff000000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
built-in;
device_type = "mpc8xx-pic";
compatible = "CPM";
};
pcmcia@0080 {
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
compatible = "fsl,pq-pcmcia";
device_type = "pcmcia";
reg = <80 80>;
interrupt-parent = <&Mpc8xx_pic>;
interrupts = <d 1>;
};
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
reg = <860 f0>;
command-proc = <9c0>;
brg-frequency = <0>;
interrupts = <0 2>; // cpm error interrupt
interrupt-parent = <&Cpm_pic>;
Cpm_pic: pic@930 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
built-in;
device_type = "cpm-pic";
compatible = "CPM";
};
smc@a80 {
device_type = "serial";
compatible = "cpm_uart";
model = "SMC";
device-id = <1>;
reg = <a80 10 3e80 40>;
clock-setup = <00ffffff 0>;
rx-clock = <1>;
tx-clock = <1>;
current-speed = <0>;
interrupts = <4 3>;
interrupt-parent = <&Cpm_pic>;
};
smc@a90 {
device_type = "serial";
compatible = "cpm_uart";
model = "SMC";
device-id = <2>;
reg = <a90 20 3f80 40>;
clock-setup = <ff00ffff 90000>;
rx-clock = <2>;
tx-clock = <2>;
current-speed = <0>;
interrupts = <3 3>;
interrupt-parent = <&Cpm_pic>;
};
scc@a40 {
device_type = "network";
compatible = "fs_enet";
model = "SCC";
device-id = <3>;
reg = <a40 18 3e00 80>;
mac-address = [ 00 00 0C 00 03 FD ];
interrupts = <1c 3>;
interrupt-parent = <&Cpm_pic>;
phy-handle = <&Phy2>;
};
};
};
};
|
