blob: 964a1c0ea637f461e046109f041d55dd82664ddb (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
|
/*
* File: include/asm-blackfin/mach-bf548/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (C) 2004-2007 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
* slot1 and store of a P register in slot 2 is not
* supported */
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
* Channel DMA stops */
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
* registers. */
#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the
* Shadow of a Conditional Branch */
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
* interrupt not functional */
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
* SPORT external receive and transmit clocks. */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
* VDDint <=0.9V */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
* not restored */
#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
* Boundary of Reserved Memory */
#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
* LC Registers Are Interrupted */
#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */
#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */
#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to
* the USB FIFO Simultaneously */
#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write()
* function */
#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional
* */
#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */
#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM
* Skew */
#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */
#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration
* of Host DMA Port */
#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent
* Allowed Configuration on Host DMA Port */
#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
#endif /* _MACH_ANOMALY_H_ */
|
