diff options
| author | Roland Scheidegger <rscheidegger_lists@hispeed.ch> | 2005-09-09 22:35:49 +0000 |
|---|---|---|
| committer | Roland Scheidegger <rscheidegger_lists@hispeed.ch> | 2005-09-09 22:35:49 +0000 |
| commit | 53c8037786a64eede00a8944ccaa42768609b66b (patch) | |
| tree | fde338a96dbee18161237c9cd925909deff0ceff /shared-core/radeon_state.c | |
| parent | c8b5a9f8cc3f55faf135be70e7ff0f7f062ca408 (diff) | |
Add support for GL_ATI_fragment_shader, new packets R200_EMIT_PP_AFS_0/1,
R200_EMIT_PP_TXCTLALL_0-5 (replaces R200_EMIT_PP_TXFILTER_0-5, 2 more
regs) and R200_EMIT_ATF_TFACTOR (replaces R200_EMIT_TFACTOR_0 (8 consts
instead of 6)
Diffstat (limited to 'shared-core/radeon_state.c')
| -rw-r--r-- | shared-core/radeon_state.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index 52a9643f..8b3317b2 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -210,6 +210,15 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * case RADEON_EMIT_PP_CUBIC_FACES_1: case RADEON_EMIT_PP_CUBIC_FACES_2: case R200_EMIT_PP_TRI_PERF_CNTL: + case R200_EMIT_PP_AFS_0: + case R200_EMIT_PP_AFS_1: + case R200_EMIT_ATF_TFACTOR: + case R200_EMIT_PP_TXCTLALL_0: + case R200_EMIT_PP_TXCTLALL_1: + case R200_EMIT_PP_TXCTLALL_2: + case R200_EMIT_PP_TXCTLALL_3: + case R200_EMIT_PP_TXCTLALL_4: + case R200_EMIT_PP_TXCTLALL_5: /* These packets don't contain memory offsets */ break; @@ -583,7 +592,16 @@ static struct { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, { - R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, + R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, { + R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, { /* 85 */ + R200_PP_AFS_1, 32, "R200_PP_AFS_1"}, { + R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, { + R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, { + R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, { + R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, { + R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, { + R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, { + R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, }; /* ================================================================ |