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authorAlex Deucher <alexdeucher@gmail.com>2008-09-18 15:11:48 -0400
committerAlex Deucher <alexdeucher@gmail.com>2008-09-18 15:11:48 -0400
commite1e782af5ddafdd24a4cf741139bb0b8e682e543 (patch)
tree0deae8b6d7f44bc19a1212c98012302d9136a247 /shared-core
parent6d0de5a899ea883693737333b4b0511c28f32d92 (diff)
Radeon: restructure PLL data
- store pixel clocks, core clock, and memory clocks separately - grab all pll limits from bios tables
Diffstat (limited to 'shared-core')
-rw-r--r--shared-core/radeon_cp.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 6c5bf03b..1ad005b7 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -2506,8 +2506,6 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
else
dev_priv->flags |= RADEON_IS_PCI;
-
-
DRM_DEBUG("%s card detected\n",
((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
@@ -2527,7 +2525,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
if (dev_priv->chip_family == CHIP_R300 &&
(RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11)
dev_priv->pll_errata |= CHIP_ERRATA_R300_CG;
-
+
if (dev_priv->chip_family == CHIP_RV200 ||
dev_priv->chip_family == CHIP_RS200)
dev_priv->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;