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-rw-r--r--shared-core/nouveau_dma.c6
-rw-r--r--shared-core/nouveau_dma.h3
-rw-r--r--shared-core/nouveau_drv.h17
-rw-r--r--shared-core/nouveau_fifo.c108
-rw-r--r--shared-core/nouveau_irq.c11
-rw-r--r--shared-core/nouveau_reg.h47
-rw-r--r--shared-core/nouveau_state.c12
-rw-r--r--shared-core/nv04_fifo.c12
-rw-r--r--shared-core/nv04_graph.c5
-rw-r--r--shared-core/nv04_instmem.c9
-rw-r--r--shared-core/nv10_fifo.c12
-rw-r--r--shared-core/nv10_graph.c11
-rw-r--r--shared-core/nv40_fifo.c4
-rw-r--r--shared-core/nv50_fifo.c9
14 files changed, 189 insertions, 77 deletions
diff --git a/shared-core/nouveau_dma.c b/shared-core/nouveau_dma.c
index b406c22d..dff786d4 100644
--- a/shared-core/nouveau_dma.c
+++ b/shared-core/nouveau_dma.c
@@ -133,10 +133,10 @@ nouveau_dma_channel_takedown(struct drm_device *dev)
#define RING_SKIPS 8
-#define READ_GET() ((NV_READ(NV03_FIFO_REGS_DMAGET(dchan->chan->id)) - \
- dchan->chan->pushbuf_base) >> 2)
+#define READ_GET() ((NV_READ(dchan->chan->get) - \
+ dchan->chan->pushbuf_base) >> 2)
#define WRITE_PUT(val) do { \
- NV_WRITE(NV03_FIFO_REGS_DMAPUT(dchan->chan->id), \
+ NV_WRITE(dchan->chan->put, \
((val) << 2) + dchan->chan->pushbuf_base); \
} while(0)
diff --git a/shared-core/nouveau_dma.h b/shared-core/nouveau_dma.h
index f8df54eb..ce3c58cb 100644
--- a/shared-core/nouveau_dma.h
+++ b/shared-core/nouveau_dma.h
@@ -89,8 +89,7 @@ typedef enum {
if (dchan->cur != dchan->put) { \
DRM_MEMORYBARRIER(); \
dchan->put = dchan->cur; \
- NV_WRITE(NV03_FIFO_REGS_DMAPUT(dchan->chan->id), \
- (dchan->put<<2)); \
+ NV_WRITE(dchan->chan->put, dchan->put << 2); \
} \
} while(0)
diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h
index c276b69f..f2d018b9 100644
--- a/shared-core/nouveau_drv.h
+++ b/shared-core/nouveau_drv.h
@@ -114,6 +114,12 @@ struct nouveau_channel
struct mem_block *pushbuf_mem;
uint32_t pushbuf_base;
+ /* FIFO user control regs */
+ uint32_t user, user_size;
+ uint32_t put;
+ uint32_t get;
+ uint32_t ref_cnt;
+
/* Notifier memory */
struct mem_block *notifier_block;
struct mem_block *notifier_heap;
@@ -193,9 +199,13 @@ struct nouveau_fb_engine {
struct nouveau_fifo_engine {
void *priv;
+ int channels;
+
int (*init)(struct drm_device *);
void (*takedown)(struct drm_device *);
+ int (*channel_id)(struct drm_device *);
+
int (*create_context)(struct nouveau_channel *);
void (*destroy_context)(struct nouveau_channel *);
int (*load_context)(struct nouveau_channel *);
@@ -221,6 +231,7 @@ struct nouveau_engine {
struct nouveau_fifo_engine fifo;
};
+#define NOUVEAU_MAX_CHANNEL_NR 128
struct drm_nouveau_private {
enum {
NOUVEAU_CARD_INIT_DOWN,
@@ -241,7 +252,7 @@ struct drm_nouveau_private {
drm_local_map_t *ramin; /* NV40 onwards */
int fifo_alloc_count;
- struct nouveau_channel *fifos[NV_MAX_FIFO_NUMBER];
+ struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
struct nouveau_engine Engine;
struct nouveau_drm_channel channel;
@@ -364,7 +375,6 @@ extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
/* nouveau_fifo.c */
extern int nouveau_fifo_init(struct drm_device *);
-extern int nouveau_fifo_number(struct drm_device *);
extern int nouveau_fifo_ctx_size(struct drm_device *);
extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *);
extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *,
@@ -452,12 +462,14 @@ extern int nv40_fb_init(struct drm_device *);
extern void nv40_fb_takedown(struct drm_device *);
/* nv04_fifo.c */
+extern int nv04_fifo_channel_id(struct drm_device *);
extern int nv04_fifo_create_context(struct nouveau_channel *);
extern void nv04_fifo_destroy_context(struct nouveau_channel *);
extern int nv04_fifo_load_context(struct nouveau_channel *);
extern int nv04_fifo_save_context(struct nouveau_channel *);
/* nv10_fifo.c */
+extern int nv10_fifo_channel_id(struct drm_device *);
extern int nv10_fifo_create_context(struct nouveau_channel *);
extern void nv10_fifo_destroy_context(struct nouveau_channel *);
extern int nv10_fifo_load_context(struct nouveau_channel *);
@@ -473,6 +485,7 @@ extern int nv40_fifo_save_context(struct nouveau_channel *);
/* nv50_fifo.c */
extern int nv50_fifo_init(struct drm_device *);
extern void nv50_fifo_takedown(struct drm_device *);
+extern int nv50_fifo_channel_id(struct drm_device *);
extern int nv50_fifo_create_context(struct nouveau_channel *);
extern void nv50_fifo_destroy_context(struct nouveau_channel *);
extern int nv50_fifo_load_context(struct nouveau_channel *);
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index 4b84f9cc..cb912f29 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -28,22 +28,6 @@
#include "nouveau_drm.h"
-/* returns the number of hw fifos */
-int nouveau_fifo_number(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv=dev->dev_private;
- switch(dev_priv->card_type)
- {
- case NV_04:
- case NV_05:
- return 16;
- case NV_50:
- return 128;
- default:
- return 32;
- }
-}
-
/* returns the size of fifo context */
int nouveau_fifo_ctx_size(struct drm_device *dev)
{
@@ -288,12 +272,13 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
* (woo, full userspace command submission !)
* When there are no more contexts, you lost
*/
- for(channel=0; channel<nouveau_fifo_number(dev); channel++) {
+ for (channel = 0; channel < engine->fifo.channels; channel++) {
if (dev_priv->fifos[channel] == NULL)
break;
}
+
/* no more fifos. you lost. */
- if (channel==nouveau_fifo_number(dev))
+ if (channel == engine->fifo.channels)
return -EINVAL;
dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_channel),
@@ -309,6 +294,28 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
DRM_INFO("Allocating FIFO number %d\n", channel);
+ /* Locate channel's user control regs */
+ if (dev_priv->card_type < NV_40) {
+ chan->user = NV03_USER(channel);
+ chan->user_size = NV03_USER_SIZE;
+ chan->put = NV03_USER_DMA_PUT(channel);
+ chan->get = NV03_USER_DMA_GET(channel);
+ chan->ref_cnt = NV03_USER_REF_CNT(channel);
+ } else
+ if (dev_priv->card_type < NV_50) {
+ chan->user = NV40_USER(channel);
+ chan->user_size = NV40_USER_SIZE;
+ chan->put = NV40_USER_DMA_PUT(channel);
+ chan->get = NV40_USER_DMA_GET(channel);
+ chan->ref_cnt = NV40_USER_REF_CNT(channel);
+ } else {
+ chan->user = NV50_USER(channel);
+ chan->user_size = NV50_USER_SIZE;
+ chan->put = NV50_USER_DMA_PUT(channel);
+ chan->get = NV50_USER_DMA_GET(channel);
+ chan->ref_cnt = NV50_USER_REF_CNT(channel);
+ }
+
/* Allocate space for per-channel fixed notifier memory */
ret = nouveau_notifier_init_channel(chan);
if (ret) {
@@ -352,14 +359,11 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
return ret;
}
- /* setup channel's default get/put values */
- if (dev_priv->card_type < NV_50) {
- NV_WRITE(NV03_FIFO_REGS_DMAPUT(channel), chan->pushbuf_base);
- NV_WRITE(NV03_FIFO_REGS_DMAGET(channel), chan->pushbuf_base);
- } else {
- NV_WRITE(NV50_FIFO_REGS_DMAPUT(channel), chan->pushbuf_base);
- NV_WRITE(NV50_FIFO_REGS_DMAGET(channel), chan->pushbuf_base);
- }
+ /* setup channel's default get/put values
+ * XXX: quite possibly extremely pointless..
+ */
+ NV_WRITE(chan->get, chan->pushbuf_base);
+ NV_WRITE(chan->put, chan->pushbuf_base);
/* If this is the first channel, setup PFIFO ourselves. For any
* other case, the GPU will handle this when it switches contexts.
@@ -398,9 +402,31 @@ void nouveau_fifo_free(struct nouveau_channel *chan)
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->Engine;
+ uint64_t t_start;
DRM_INFO("%s: freeing fifo %d\n", __func__, chan->id);
+ /* Disable channel switching, if this channel isn't currenly
+ * active re-enable it if there's still pending commands.
+ * We really should do a manual context switch here, but I'm
+ * not sure I trust our ability to do this reliably yet..
+ */
+ NV_WRITE(NV03_PFIFO_CACHES, 0);
+ if (engine->fifo.channel_id(dev) != chan->id &&
+ NV_READ(chan->get) != NV_READ(chan->put)) {
+ NV_WRITE(NV03_PFIFO_CACHES, 1);
+ }
+
+ /* Give the channel a chance to idle, wait 2s (hopefully) */
+ t_start = engine->timer.read(dev);
+ while (NV_READ(chan->get) != NV_READ(chan->put)) {
+ if (engine->timer.read(dev) - t_start > 2000000000ULL) {
+ DRM_ERROR("Failed to idle channel %d before destroy."
+ "Prepare for strangeness..\n", chan->id);
+ break;
+ }
+ }
+
/* disable the fifo caches */
NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
@@ -408,14 +434,12 @@ void nouveau_fifo_free(struct nouveau_channel *chan)
NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
/* stop the fifo, otherwise it could be running and
- * it will crash when removing gpu objects */
- if (dev_priv->card_type < NV_50) {
- NV_WRITE(NV03_FIFO_REGS_DMAPUT(chan->id), chan->pushbuf_base);
- NV_WRITE(NV03_FIFO_REGS_DMAGET(chan->id), chan->pushbuf_base);
- } else {
- NV_WRITE(NV50_FIFO_REGS_DMAPUT(chan->id), chan->pushbuf_base);
- NV_WRITE(NV50_FIFO_REGS_DMAGET(chan->id), chan->pushbuf_base);
- }
+ * it will crash when removing gpu objects
+ *XXX: from real-world evidence, absolutely useless..
+ */
+ NV_WRITE(chan->get, chan->pushbuf_base);
+ NV_WRITE(chan->put, chan->pushbuf_base);
+
// FIXME XXX needs more code
engine->fifo.destroy_context(chan);
@@ -451,10 +475,11 @@ void nouveau_fifo_free(struct nouveau_channel *chan)
void nouveau_fifo_cleanup(struct drm_device *dev, struct drm_file *file_priv)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_engine *engine = &dev_priv->Engine;
int i;
DRM_DEBUG("clearing FIFO enables from file_priv\n");
- for(i = 0; i < nouveau_fifo_number(dev); i++) {
+ for(i = 0; i < engine->fifo.channels; i++) {
struct nouveau_channel *chan = dev_priv->fifos[i];
if (chan && chan->file_priv == file_priv)
@@ -467,8 +492,9 @@ nouveau_fifo_owner(struct drm_device *dev, struct drm_file *file_priv,
int channel)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_engine *engine = &dev_priv->Engine;
- if (channel >= nouveau_fifo_number(dev))
+ if (channel >= engine->fifo.channels)
return 0;
if (dev_priv->fifos[channel] == NULL)
return 0;
@@ -508,14 +534,8 @@ static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
/* make the fifo available to user space */
/* first, the fifo control regs */
- init->ctrl = dev_priv->mmio->offset;
- if (dev_priv->card_type < NV_50) {
- init->ctrl += NV03_FIFO_REGS(init->channel);
- init->ctrl_size = NV03_FIFO_REGS_SIZE;
- } else {
- init->ctrl += NV50_FIFO_REGS(init->channel);
- init->ctrl_size = NV50_FIFO_REGS_SIZE;
- }
+ init->ctrl = dev_priv->mmio->offset + chan->user;
+ init->ctrl_size = chan->user_size;
res = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS,
0, &chan->regs);
if (res != 0)
diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index 43f37ca0..500fda2f 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -68,6 +68,7 @@ static void
nouveau_fifo_irq_handler(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_engine *engine = &dev_priv->Engine;
uint32_t status;
while ((status = NV_READ(NV03_PFIFO_INTR_0))) {
@@ -75,8 +76,7 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
NV_WRITE(NV03_PFIFO_CACHES, 0);
- chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
- (nouveau_fifo_number(dev) - 1);
+ chid = engine->fifo.channel_id(dev);
get = NV_READ(NV03_PFIFO_CACHE1_GET);
if (status & NV_PFIFO_INTR_CACHE_ERROR) {
@@ -190,6 +190,7 @@ static int
nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_engine *engine = &dev_priv->Engine;
int channel;
if (dev_priv->card_type < NV_10) {
@@ -234,8 +235,7 @@ nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
}
}
- if (channel > nouveau_fifo_number(dev) ||
- dev_priv->fifos[channel] == NULL) {
+ if (channel > engine->fifo.channels || !dev_priv->fifos[channel]) {
DRM_ERROR("AIII, invalid/inactive channel id %d\n", channel);
return -EINVAL;
}
@@ -365,9 +365,10 @@ static inline void
nouveau_pgraph_intr_context_switch(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_engine *engine = &dev_priv->Engine;
uint32_t chid;
- chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
+ chid = engine->fifo.channel_id(dev);
DRM_DEBUG("PGRAPH context switch interrupt channel %x\n", chid);
switch(dev_priv->card_type) {
diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h
index 43573f2c..bc71e5f8 100644
--- a/shared-core/nouveau_reg.h
+++ b/shared-core/nouveau_reg.h
@@ -45,16 +45,40 @@
#define NV_CLASS_NULL 0x00000030
#define NV_CLASS_DMA_IN_MEMORY 0x0000003D
+#define NV03_USER(i) (0x00800000+(i*NV03_USER_SIZE))
+#define NV03_USER__SIZE 16
+#define NV10_USER__SIZE 32
+#define NV03_USER_SIZE 0x00010000
+#define NV03_USER_DMA_PUT(i) (0x00800040+(i*NV03_USER_SIZE))
+#define NV03_USER_DMA_PUT__SIZE 16
+#define NV10_USER_DMA_PUT__SIZE 32
+#define NV03_USER_DMA_GET(i) (0x00800044+(i*NV03_USER_SIZE))
+#define NV03_USER_DMA_GET__SIZE 16
+#define NV10_USER_DMA_GET__SIZE 32
+#define NV03_USER_REF_CNT(i) (0x00800048+(i*NV03_USER_SIZE))
+#define NV03_USER_REF_CNT__SIZE 16
+#define NV10_USER_REF_CNT__SIZE 32
+
+#define NV40_USER(i) (0x00c00000+(i*NV40_USER_SIZE))
+#define NV40_USER_SIZE 0x00001000
+#define NV40_USER_DMA_PUT(i) (0x00c00040+(i*NV40_USER_SIZE))
+#define NV40_USER_DMA_PUT__SIZE 32
+#define NV40_USER_DMA_GET(i) (0x00c00044+(i*NV40_USER_SIZE))
+#define NV40_USER_DMA_GET__SIZE 32
+#define NV40_USER_REF_CNT(i) (0x00c00048+(i*NV40_USER_SIZE))
+#define NV40_USER_REF_CNT__SIZE 32
+
+#define NV50_USER(i) (0x00c00000+(i*NV50_USER_SIZE))
+#define NV50_USER_SIZE 0x00002000
+#define NV50_USER_DMA_PUT(i) (0x00c00040+(i*NV50_USER_SIZE))
+#define NV50_USER_DMA_PUT__SIZE 128
+#define NV50_USER_DMA_GET(i) (0x00c00044+(i*NV50_USER_SIZE))
+#define NV50_USER_DMA_GET__SIZE 128
+/*XXX: I don't think this actually exists.. */
+#define NV50_USER_REF_CNT(i) (0x00c00048+(i*NV50_USER_SIZE))
+#define NV50_USER_REF_CNT__SIZE 128
+
#define NV03_FIFO_SIZE 0x8000UL
-#define NV_MAX_FIFO_NUMBER 128
-#define NV03_FIFO_REGS_SIZE 0x10000
-#define NV03_FIFO_REGS(i) (0x00800000+i*NV03_FIFO_REGS_SIZE)
-# define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40)
-# define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44)
-#define NV50_FIFO_REGS_SIZE 0x2000
-#define NV50_FIFO_REGS(i) (0x00c00000+i*NV50_FIFO_REGS_SIZE)
-# define NV50_FIFO_REGS_DMAPUT(i) (NV50_FIFO_REGS(i)+0x40)
-# define NV50_FIFO_REGS_DMAGET(i) (NV50_FIFO_REGS(i)+0x44)
#define NV03_PMC_BOOT_0 0x00000000
#define NV03_PMC_BOOT_1 0x00000004
@@ -406,6 +430,11 @@
#define NV04_PFIFO_CACHE0_PULL1 0x00003054
#define NV03_PFIFO_CACHE1_PUSH0 0x00003200
#define NV03_PFIFO_CACHE1_PUSH1 0x00003204
+#define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8)
+#define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16)
+#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f
+#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f
+#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f
#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220
#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224
# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index c19d7bf4..82a04b55 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -116,8 +116,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv04_graph_destroy_context;
engine->graph.load_context = nv04_graph_load_context;
engine->graph.save_context = nv04_graph_save_context;
+ engine->fifo.channels = 16;
engine->fifo.init = nouveau_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
+ engine->fifo.channel_id = nv04_fifo_channel_id;
engine->fifo.create_context = nv04_fifo_create_context;
engine->fifo.destroy_context = nv04_fifo_destroy_context;
engine->fifo.load_context = nv04_fifo_load_context;
@@ -143,8 +145,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv10_graph_destroy_context;
engine->graph.load_context = nv10_graph_load_context;
engine->graph.save_context = nv10_graph_save_context;
+ engine->fifo.channels = 32;
engine->fifo.init = nouveau_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
+ engine->fifo.channel_id = nv10_fifo_channel_id;
engine->fifo.create_context = nv10_fifo_create_context;
engine->fifo.destroy_context = nv10_fifo_destroy_context;
engine->fifo.load_context = nv10_fifo_load_context;
@@ -170,8 +174,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv20_graph_destroy_context;
engine->graph.load_context = nv20_graph_load_context;
engine->graph.save_context = nv20_graph_save_context;
+ engine->fifo.channels = 32;
engine->fifo.init = nouveau_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
+ engine->fifo.channel_id = nv10_fifo_channel_id;
engine->fifo.create_context = nv10_fifo_create_context;
engine->fifo.destroy_context = nv10_fifo_destroy_context;
engine->fifo.load_context = nv10_fifo_load_context;
@@ -197,8 +203,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv20_graph_destroy_context;
engine->graph.load_context = nv20_graph_load_context;
engine->graph.save_context = nv20_graph_save_context;
+ engine->fifo.channels = 32;
engine->fifo.init = nouveau_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
+ engine->fifo.channel_id = nv10_fifo_channel_id;
engine->fifo.create_context = nv10_fifo_create_context;
engine->fifo.destroy_context = nv10_fifo_destroy_context;
engine->fifo.load_context = nv10_fifo_load_context;
@@ -224,8 +232,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv40_graph_destroy_context;
engine->graph.load_context = nv40_graph_load_context;
engine->graph.save_context = nv40_graph_save_context;
+ engine->fifo.channels = 32;
engine->fifo.init = nv40_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
+ engine->fifo.channel_id = nv10_fifo_channel_id;
engine->fifo.create_context = nv40_fifo_create_context;
engine->fifo.destroy_context = nv40_fifo_destroy_context;
engine->fifo.load_context = nv40_fifo_load_context;
@@ -252,8 +262,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv50_graph_destroy_context;
engine->graph.load_context = nv50_graph_load_context;
engine->graph.save_context = nv50_graph_save_context;
+ engine->fifo.channels = 128;
engine->fifo.init = nv50_fifo_init;
engine->fifo.takedown = nv50_fifo_takedown;
+ engine->fifo.channel_id = nv50_fifo_channel_id;
engine->fifo.create_context = nv50_fifo_create_context;
engine->fifo.destroy_context = nv50_fifo_destroy_context;
engine->fifo.load_context = nv50_fifo_load_context;
diff --git a/shared-core/nv04_fifo.c b/shared-core/nv04_fifo.c
index d172302c..230c8e72 100644
--- a/shared-core/nv04_fifo.c
+++ b/shared-core/nv04_fifo.c
@@ -36,6 +36,15 @@
#define NV04_RAMFC__SIZE 32
int
+nv04_fifo_channel_id(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
+ NV03_PFIFO_CACHE1_PUSH1_CHID_MASK);
+}
+
+int
nv04_fifo_create_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
@@ -84,7 +93,8 @@ nv04_fifo_load_context(struct nouveau_channel *chan)
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t tmp;
- NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | chan->id);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
+ NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));
diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c
index 04dbf0ed..81a6d5c8 100644
--- a/shared-core/nv04_graph.c
+++ b/shared-core/nv04_graph.c
@@ -353,6 +353,7 @@ struct graph_state {
void nouveau_nv04_context_switch(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_engine *engine = &dev_priv->Engine;
struct nouveau_channel *next, *last;
int chid;
@@ -370,7 +371,7 @@ void nouveau_nv04_context_switch(struct drm_device *dev)
return;
}
- chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
+ chid = engine->fifo.channel_id(dev);
next = dev_priv->fifos[chid];
if (!next) {
@@ -378,7 +379,7 @@ void nouveau_nv04_context_switch(struct drm_device *dev)
return;
}
- chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+ chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (engine->fifo.channels - 1);
last = dev_priv->fifos[chid];
if (!last) {
diff --git a/shared-core/nv04_instmem.c b/shared-core/nv04_instmem.c
index 56968181..804f9a75 100644
--- a/shared-core/nv04_instmem.c
+++ b/shared-core/nv04_instmem.c
@@ -33,6 +33,7 @@ static void
nv04_instmem_configure_fixed_tables(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_engine *engine = &dev_priv->Engine;
/* FIFO hash table (RAMHT)
* use 4k hash table at RAMIN+0x10000
@@ -61,8 +62,8 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev)
case NV_40:
case NV_44:
dev_priv->ramfc_offset = 0x20000;
- dev_priv->ramfc_size = nouveau_fifo_number(dev) *
- nouveau_fifo_ctx_size(dev);
+ dev_priv->ramfc_size = engine->fifo.channels *
+ nouveau_fifo_ctx_size(dev);
break;
case NV_30:
case NV_20:
@@ -72,8 +73,8 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev)
case NV_04:
default:
dev_priv->ramfc_offset = 0x11400;
- dev_priv->ramfc_size = nouveau_fifo_number(dev) *
- nouveau_fifo_ctx_size(dev);
+ dev_priv->ramfc_size = engine->fifo.channels *
+ nouveau_fifo_ctx_size(dev);
break;
}
DRM_DEBUG("RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset,
diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c
index 45d2603a..6d50b6ca 100644
--- a/shared-core/nv10_fifo.c
+++ b/shared-core/nv10_fifo.c
@@ -37,6 +37,15 @@
#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
int
+nv10_fifo_channel_id(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
+ NV10_PFIFO_CACHE1_PUSH1_CHID_MASK);
+}
+
+int
nv10_fifo_create_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
@@ -87,7 +96,8 @@ nv10_fifo_load_context(struct nouveau_channel *chan)
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t tmp;
- NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | chan->id);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
+ NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET));
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT));
diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c
index 606fb43f..d0c2285f 100644
--- a/shared-core/nv10_graph.c
+++ b/shared-core/nv10_graph.c
@@ -692,6 +692,7 @@ int nv10_graph_save_context(struct nouveau_channel *chan)
void nouveau_nv10_context_switch(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv;
+ struct nouveau_engine *engine;
struct nouveau_channel *next, *last;
int chid;
@@ -708,8 +709,10 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
DRM_DEBUG("Invalid drm_nouveau_private->fifos\n");
return;
}
+ engine = &dev_priv->Engine;
- chid = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20)&(nouveau_fifo_number(dev)-1);
+ chid = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) &
+ (engine->fifo.channels - 1);
next = dev_priv->fifos[chid];
if (!next) {
@@ -717,7 +720,8 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
return;
}
- chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+ chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) &
+ (engine->fifo.channels - 1);
last = dev_priv->fifos[chid];
if (!last) {
@@ -827,13 +831,14 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_engine *engine = &dev_priv->Engine;
struct graph_state* pgraph_ctx = chan->pgraph_ctx;
int chid;
drm_free(pgraph_ctx, sizeof(*pgraph_ctx), DRM_MEM_DRIVER);
chan->pgraph_ctx = NULL;
- chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
+ chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (engine->fifo.channels - 1);
/* This code seems to corrupt the 3D pipe, but blob seems to do similar things ????
*/
diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c
index 5b3eda09..7f9d5e31 100644
--- a/shared-core/nv40_fifo.c
+++ b/shared-core/nv40_fifo.c
@@ -135,7 +135,9 @@ nv40_fifo_load_context(struct nouveau_channel *chan)
NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, tmp);
/* Set channel active, and in DMA mode */
- NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00010000 | chan->id);
+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
+ NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
+
/* Reset DMA_CTL_AT_INFO to INVALID */
tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c
index f77de6e7..c5cde913 100644
--- a/shared-core/nv50_fifo.c
+++ b/shared-core/nv50_fifo.c
@@ -213,6 +213,15 @@ nv50_fifo_takedown(struct drm_device *dev)
}
int
+nv50_fifo_channel_id(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
+ NV50_PFIFO_CACHE1_PUSH1_CHID_MASK);
+}
+
+int
nv50_fifo_create_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 03:21:05 +0000