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Diffstat (limited to 'src/mesa/drivers/dri/r600/r700_render.c')
-rw-r--r--src/mesa/drivers/dri/r600/r700_render.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index eab27cbd84..8f14af7472 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -42,7 +42,6 @@
#include "tnl/t_vp_build.h"
#include "tnl/t_context.h"
#include "tnl/t_vertex.h"
-#include "tnl/t_pipeline.h"
#include "vbo/vbo_context.h"
#include "r600_context.h"
@@ -116,8 +115,6 @@ void r700Start3D(context_t *context)
END_BATCH();
COMMIT_BATCH();
-
- r700WaitForIdleClean(context);
}
GLboolean r700SyncSurf(context_t *context,
@@ -422,7 +419,7 @@ static void r700RunRenderPrimitiveImmediate(GLcontext * ctx, int start, int end,
}
/* start 3d, idle, cb/db flush */
-#define PRE_EMIT_STATE_BUFSZ 10 + 5 + 14
+#define PRE_EMIT_STATE_BUFSZ 5 + 5 + 18
static GLuint r700PredictRenderSize(GLcontext* ctx,
const struct _mesa_prim *prim,
@@ -935,6 +932,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx,
radeon_debug_remove_indent();
/* Flush render op cached for last several quads. */
+ /* XXX drm should handle this in fence submit */
r700WaitForIdleClean(context);
rrb = radeon_get_colorbuffer(&context->radeon);