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-rw-r--r--src/mesa/drivers/dri/radeon/radeon_bo_drm.h34
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_bo_legacy.c181
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_chipset.h137
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_cmdbuf.h32
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_common.c29
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_common_context.c133
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_common_context.h19
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_cs_legacy.c26
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_dma.c8
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_fbo.c16
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c8
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.c291
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.h2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_texture.c1
14 files changed, 776 insertions, 141 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
index c5c28ed066..655b52a669 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
@@ -34,6 +34,10 @@
#include <stdint.h>
//#include "radeon_track.h"
+#ifndef RADEON_DEBUG_BO
+#define RADEON_DEBUG_BO 1
+#endif
+
/* bo object */
#define RADEON_BO_FLAGS_MACRO_TILE 1
#define RADEON_BO_FLAGS_MICRO_TILE 2
@@ -57,12 +61,22 @@ struct radeon_bo {
/* bo functions */
struct radeon_bo_funcs {
+#ifdef RADEON_DEBUG_BO
+ struct radeon_bo *(*bo_open)(struct radeon_bo_manager *bom,
+ uint32_t handle,
+ uint32_t size,
+ uint32_t alignment,
+ uint32_t domains,
+ uint32_t flags,
+ char * szBufUsage);
+#else
struct radeon_bo *(*bo_open)(struct radeon_bo_manager *bom,
uint32_t handle,
uint32_t size,
uint32_t alignment,
uint32_t domains,
uint32_t flags);
+#endif /* RADEON_DEBUG_BO */
void (*bo_ref)(struct radeon_bo *bo);
struct radeon_bo *(*bo_unref)(struct radeon_bo *bo);
int (*bo_map)(struct radeon_bo *bo, int write);
@@ -96,13 +110,21 @@ static inline struct radeon_bo *_radeon_bo_open(struct radeon_bo_manager *bom,
uint32_t alignment,
uint32_t domains,
uint32_t flags,
+#ifdef RADEON_DEBUG_BO
+ char * szBufUsage,
+#endif /* RADEON_DEBUG_BO */
const char *file,
const char *func,
int line)
{
struct radeon_bo *bo;
+#ifdef RADEON_DEBUG_BO
+ bo = bom->funcs->bo_open(bom, handle, size, alignment, domains, flags, szBufUsage);
+#else
bo = bom->funcs->bo_open(bom, handle, size, alignment, domains, flags);
+#endif /* RADEON_DEBUG_BO */
+
#ifdef RADEON_BO_TRACK
if (bo) {
bo->track = radeon_tracker_add_track(&bom->tracker, bo->handle);
@@ -165,15 +187,13 @@ static inline int _radeon_bo_wait(struct radeon_bo *bo,
return bo->bom->funcs->bo_wait(bo);
}
-static inline int radeon_bo_is_static(struct radeon_bo *bo)
-{
- if (bo->bom->funcs->bo_is_static)
- return bo->bom->funcs->bo_is_static(bo);
- return 0;
-}
-
+#ifdef RADEON_DEBUG_BO
+#define radeon_bo_open(bom, h, s, a, d, f, u)\
+ _radeon_bo_open(bom, h, s, a, d, f, u, __FILE__, __FUNCTION__, __LINE__)
+#else
#define radeon_bo_open(bom, h, s, a, d, f)\
_radeon_bo_open(bom, h, s, a, d, f, __FILE__, __FUNCTION__, __LINE__)
+#endif /* RADEON_DEBUG_BO */
#define radeon_bo_ref(bo)\
_radeon_bo_ref(bo, __FILE__, __FUNCTION__, __LINE__)
#define radeon_bo_unref(bo)\
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
index 1fec7444cd..992eb4611b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
@@ -69,6 +69,9 @@ struct bo_legacy {
void *ptr;
struct bo_legacy *next, *prev;
struct bo_legacy *pnext, *pprev;
+#ifdef RADEON_DEBUG_BO
+ char szBufUsage[16];
+#endif /* RADEON_DEBUG_BO */
};
struct bo_manager_legacy {
@@ -168,7 +171,9 @@ static void legacy_get_current_age(struct bo_manager_legacy *boml)
unsigned char *RADEONMMIO = NULL;
int r;
- if (IS_R300_CLASS(boml->screen)) {
+ if ( IS_R300_CLASS(boml->screen)
+ || IS_R600_CLASS(boml->screen) )
+ {
gp.param = RADEON_PARAM_LAST_CLEAR;
gp.value = (int *)&boml->current_age;
r = drmCommandWriteRead(boml->base.fd, DRM_RADEON_GETPARAM,
@@ -177,7 +182,8 @@ static void legacy_get_current_age(struct bo_manager_legacy *boml)
fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r);
exit(1);
}
- } else {
+ }
+ else {
RADEONMMIO = boml->screen->mmio.map;
boml->current_age = boml->screen->scratch[3];
boml->current_age = INREG(RADEON_GUI_SCRATCH_REG3);
@@ -283,7 +289,12 @@ static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml,
uint32_t size,
uint32_t alignment,
uint32_t domains,
+#ifdef RADEON_DEBUG_BO
+ uint32_t flags,
+ char * szBufUsage)
+#else
uint32_t flags)
+#endif /* RADEON_DEBUG_BO */
{
struct bo_legacy *bo_legacy;
static int pgsize;
@@ -315,6 +326,11 @@ static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml,
if (bo_legacy->next) {
bo_legacy->next->prev = bo_legacy;
}
+
+#ifdef RADEON_DEBUG_BO
+ sprintf(bo_legacy->szBufUsage, "%s", szBufUsage);
+#endif /* RADEON_DEBUG_BO */
+
return bo_legacy;
}
@@ -413,7 +429,12 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
uint32_t size,
uint32_t alignment,
uint32_t domains,
+#ifdef RADEON_DEBUG_BO
+ uint32_t flags,
+ char * szBufUsage)
+#else
uint32_t flags)
+#endif /* RADEON_DEBUG_BO */
{
struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom;
struct bo_legacy *bo_legacy;
@@ -430,29 +451,37 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
}
return NULL;
}
-
+#ifdef RADEON_DEBUG_BO
+ bo_legacy = bo_allocate(boml, size, alignment, domains, flags, szBufUsage);
+#else
bo_legacy = bo_allocate(boml, size, alignment, domains, flags);
+#endif /* RADEON_DEBUG_BO */
bo_legacy->static_bo = 0;
r = legacy_new_handle(boml, &bo_legacy->base.handle);
if (r) {
bo_free(bo_legacy);
return NULL;
}
- if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT) {
- retry:
+ if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT)
+ {
+retry:
legacy_track_pending(boml, 0);
/* dma buffers */
r = bo_dma_alloc(&(bo_legacy->base));
- if (r) {
- if (legacy_wait_any_pending(boml) == -1) {
- bo_free(bo_legacy);
- return NULL;
- }
- goto retry;
- return NULL;
+ if (r)
+ {
+ if (legacy_wait_any_pending(boml) == -1)
+ {
+ bo_free(bo_legacy);
+ return NULL;
+ }
+ goto retry;
+ return NULL;
}
- } else {
+ }
+ else
+ {
bo_legacy->ptr = malloc(bo_legacy->base.size);
if (bo_legacy->ptr == NULL) {
bo_free(bo_legacy);
@@ -460,6 +489,7 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
}
}
radeon_bo_ref(&(bo_legacy->base));
+
return (struct radeon_bo*)bo_legacy;
}
@@ -488,7 +518,7 @@ static int bo_map(struct radeon_bo *bo, int write)
{
struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
-
+
legacy_wait_pending(bo);
bo_legacy->validated = 0;
bo_legacy->dirty = 1;
@@ -514,6 +544,7 @@ static int bo_map(struct radeon_bo *bo, int write)
volatile int *buf = (int*)boml->screen->driScreen->pFB;
p = *buf;
}
+
return 0;
}
@@ -521,10 +552,13 @@ static int bo_unmap(struct radeon_bo *bo)
{
struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
- if (--bo_legacy->map_count > 0) {
+ if (--bo_legacy->map_count > 0)
+ {
return 0;
}
+
bo->ptr = NULL;
+
return 0;
}
@@ -587,44 +621,53 @@ static int bo_vram_validate(struct radeon_bo *bo,
driUpdateTextureLRU(&bo_legacy->tobj->base);
if (bo_legacy->dirty || bo_legacy->tobj->base.dirty_images[0]) {
- /* Copy to VRAM using a blit.
- * All memory is 4K aligned. We're using 1024 pixels wide blits.
- */
- drm_radeon_texture_t tex;
- drm_radeon_tex_image_t tmp;
- int ret;
-
- tex.offset = bo_legacy->offset;
- tex.image = &tmp;
- assert(!(tex.offset & 1023));
-
- tmp.x = 0;
- tmp.y = 0;
- if (bo->size < 4096) {
- tmp.width = (bo->size + 3) / 4;
- tmp.height = 1;
- } else {
- tmp.width = 1024;
- tmp.height = (bo->size + 4095) / 4096;
- }
- tmp.data = bo_legacy->ptr;
- tex.format = RADEON_TXFORMAT_ARGB8888;
- tex.width = tmp.width;
- tex.height = tmp.height;
- tex.pitch = MAX2(tmp.width / 16, 1);
- do {
- ret = drmCommandWriteRead(bo->bom->fd,
- DRM_RADEON_TEXTURE,
- &tex,
- sizeof(drm_radeon_texture_t));
- if (ret) {
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "DRM_RADEON_TEXTURE: again!\n");
- usleep(1);
- }
- } while (ret == -EAGAIN);
- bo_legacy->dirty = 0;
- bo_legacy->tobj->base.dirty_images[0] = 0;
+ if (IS_R600_CLASS(boml->screen)) {
+ char *src = bo_legacy->ptr;
+ char *dst = (char *) boml->screen->driScreen->pFB +
+ (bo_legacy->offset - boml->fb_location);
+
+ /* FIXME: alignment, pitch, etc. */
+ memcpy(dst, src, bo->size);
+ } else {
+ /* Copy to VRAM using a blit.
+ * All memory is 4K aligned. We're using 1024 pixels wide blits.
+ */
+ drm_radeon_texture_t tex;
+ drm_radeon_tex_image_t tmp;
+ int ret;
+
+ tex.offset = bo_legacy->offset;
+ tex.image = &tmp;
+ assert(!(tex.offset & 1023));
+
+ tmp.x = 0;
+ tmp.y = 0;
+ if (bo->size < 4096) {
+ tmp.width = (bo->size + 3) / 4;
+ tmp.height = 1;
+ } else {
+ tmp.width = 1024;
+ tmp.height = (bo->size + 4095) / 4096;
+ }
+ tmp.data = bo_legacy->ptr;
+ tex.format = RADEON_TXFORMAT_ARGB8888;
+ tex.width = tmp.width;
+ tex.height = tmp.height;
+ tex.pitch = MAX2(tmp.width / 16, 1);
+ do {
+ ret = drmCommandWriteRead(bo->bom->fd,
+ DRM_RADEON_TEXTURE,
+ &tex,
+ sizeof(drm_radeon_texture_t));
+ if (ret) {
+ if (RADEON_DEBUG & DEBUG_IOCTL)
+ fprintf(stderr, "DRM_RADEON_TEXTURE: again!\n");
+ usleep(1);
+ }
+ } while (ret == -EAGAIN);
+ }
+ bo_legacy->dirty = 0;
+ bo_legacy->tobj->base.dirty_images[0] = 0;
}
return 0;
}
@@ -646,13 +689,20 @@ int radeon_bo_legacy_validate(struct radeon_bo *bo,
int retries = 0;
if (bo_legacy->map_count) {
+#ifdef RADEON_DEBUG_BO
+ fprintf(stderr, "bo(%p, %d, %s) is mapped (%d) can't valide it.\n",
+ bo, bo->size, bo_legacy->szBufUsage, bo_legacy->map_count);
+#else
fprintf(stderr, "bo(%p, %d) is mapped (%d) can't valide it.\n",
bo, bo->size, bo_legacy->map_count);
+#endif /* RADEON_DEBUG_BO */
+
return -EINVAL;
}
if (bo_legacy->static_bo || bo_legacy->validated) {
*soffset = bo_legacy->offset;
*eoffset = bo_legacy->offset + bo->size;
+
return 0;
}
if (!(bo->domains & RADEON_GEM_DOMAIN_GTT)) {
@@ -673,6 +723,7 @@ int radeon_bo_legacy_validate(struct radeon_bo *bo,
*soffset = bo_legacy->offset;
*eoffset = bo_legacy->offset + bo->size;
bo_legacy->validated = 1;
+
return 0;
}
@@ -717,11 +768,21 @@ void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom)
}
static struct bo_legacy *radeon_legacy_bo_alloc_static(struct bo_manager_legacy *bom,
- int size, uint32_t offset)
+ int size,
+#ifdef RADEON_DEBUG_BO
+ uint32_t offset,
+ char * szBufUsage)
+#else
+ uint32_t offset)
+#endif /* RADEON_DEBUG_BO */
{
struct bo_legacy *bo;
+#ifdef RADEON_DEBUG_BO
+ bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0, szBufUsage);
+#else
bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+#endif /* RADEON_DEBUG_BO */
if (bo == NULL)
return NULL;
bo->static_bo = 1;
@@ -782,7 +843,11 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc
size = 4096*4096*4;
/* allocate front */
+#ifdef RADEON_DEBUG_BO
+ bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->frontOffset, "FRONT BUF");
+#else
bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->frontOffset);
+#endif /* RADEON_DEBUG_BO */
if (!bo) {
radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom);
return NULL;
@@ -792,7 +857,11 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc
}
/* allocate back */
+#ifdef RADEON_DEBUG_BO
+ bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->backOffset, "BACK BUF");
+#else
bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->backOffset);
+#endif /* RADEON_DEBUG_BO */
if (!bo) {
radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom);
return NULL;
@@ -802,7 +871,11 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc
}
/* allocate depth */
+#ifdef RADEON_DEBUG_BO
+ bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->depthOffset, "Z BUF");
+#else
bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->depthOffset);
+#endif /* RADEON_DEBUG_BO */
if (!bo) {
radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom);
return NULL;
diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h
index f6bd1eb83f..0a6a2df35b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_chipset.h
+++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h
@@ -255,6 +255,131 @@
#define PCI_CHIP_RS740_796E 0x796E
#define PCI_CHIP_RS740_796F 0x796F
+#define PCI_CHIP_R600_9400 0x9400
+#define PCI_CHIP_R600_9401 0x9401
+#define PCI_CHIP_R600_9402 0x9402
+#define PCI_CHIP_R600_9403 0x9403
+#define PCI_CHIP_R600_9405 0x9405
+#define PCI_CHIP_R600_940A 0x940A
+#define PCI_CHIP_R600_940B 0x940B
+#define PCI_CHIP_R600_940F 0x940F
+
+#define PCI_CHIP_RV610_94C0 0x94C0
+#define PCI_CHIP_RV610_94C1 0x94C1
+#define PCI_CHIP_RV610_94C3 0x94C3
+#define PCI_CHIP_RV610_94C4 0x94C4
+#define PCI_CHIP_RV610_94C5 0x94C5
+#define PCI_CHIP_RV610_94C6 0x94C6
+#define PCI_CHIP_RV610_94C7 0x94C7
+#define PCI_CHIP_RV610_94C8 0x94C8
+#define PCI_CHIP_RV610_94C9 0x94C9
+#define PCI_CHIP_RV610_94CB 0x94CB
+#define PCI_CHIP_RV610_94CC 0x94CC
+#define PCI_CHIP_RV610_94CD 0x94CD
+
+#define PCI_CHIP_RV630_9580 0x9580
+#define PCI_CHIP_RV630_9581 0x9581
+#define PCI_CHIP_RV630_9583 0x9583
+#define PCI_CHIP_RV630_9586 0x9586
+#define PCI_CHIP_RV630_9587 0x9587
+#define PCI_CHIP_RV630_9588 0x9588
+#define PCI_CHIP_RV630_9589 0x9589
+#define PCI_CHIP_RV630_958A 0x958A
+#define PCI_CHIP_RV630_958B 0x958B
+#define PCI_CHIP_RV630_958C 0x958C
+#define PCI_CHIP_RV630_958D 0x958D
+#define PCI_CHIP_RV630_958E 0x958E
+#define PCI_CHIP_RV630_958F 0x958F
+
+#define PCI_CHIP_RV670_9500 0x9500
+#define PCI_CHIP_RV670_9501 0x9501
+#define PCI_CHIP_RV670_9504 0x9504
+#define PCI_CHIP_RV670_9505 0x9505
+#define PCI_CHIP_RV670_9506 0x9506
+#define PCI_CHIP_RV670_9507 0x9507
+#define PCI_CHIP_RV670_9508 0x9508
+#define PCI_CHIP_RV670_9509 0x9509
+#define PCI_CHIP_RV670_950F 0x950F
+#define PCI_CHIP_RV670_9511 0x9511
+#define PCI_CHIP_RV670_9515 0x9515
+#define PCI_CHIP_RV670_9517 0x9517
+#define PCI_CHIP_RV670_9519 0x9519
+
+#define PCI_CHIP_RV620_95C0 0x95C0
+#define PCI_CHIP_RV620_95C2 0x95C2
+#define PCI_CHIP_RV620_95C4 0x95C4
+#define PCI_CHIP_RV620_95C5 0x95C5
+#define PCI_CHIP_RV620_95C6 0x95C6
+#define PCI_CHIP_RV620_95C7 0x95C7
+#define PCI_CHIP_RV620_95C9 0x95C9
+#define PCI_CHIP_RV620_95CC 0x95CC
+#define PCI_CHIP_RV620_95CD 0x95CD
+#define PCI_CHIP_RV620_95CE 0x95CE
+#define PCI_CHIP_RV620_95CF 0x95CF
+
+#define PCI_CHIP_RV635_9590 0x9590
+#define PCI_CHIP_RV635_9591 0x9591
+#define PCI_CHIP_RV635_9593 0x9593
+#define PCI_CHIP_RV635_9595 0x9595
+#define PCI_CHIP_RV635_9596 0x9596
+#define PCI_CHIP_RV635_9597 0x9597
+#define PCI_CHIP_RV635_9598 0x9598
+#define PCI_CHIP_RV635_9599 0x9599
+#define PCI_CHIP_RV635_959B 0x959B
+
+#define PCI_CHIP_RS780_9610 0x9610
+#define PCI_CHIP_RS780_9611 0x9611
+#define PCI_CHIP_RS780_9612 0x9612
+#define PCI_CHIP_RS780_9613 0x9613
+#define PCI_CHIP_RS780_9614 0x9614
+#define PCI_CHIP_RS780_9615 0x9615
+#define PCI_CHIP_RS780_9616 0x9616
+
+#define PCI_CHIP_RV770_9440 0x9440
+#define PCI_CHIP_RV770_9441 0x9441
+#define PCI_CHIP_RV770_9442 0x9442
+#define PCI_CHIP_RV770_9444 0x9444
+#define PCI_CHIP_RV770_9446 0x9446
+#define PCI_CHIP_RV770_944A 0x944A
+#define PCI_CHIP_RV770_944B 0x944B
+#define PCI_CHIP_RV770_944C 0x944C
+#define PCI_CHIP_RV770_944E 0x944E
+#define PCI_CHIP_RV770_9450 0x9450
+#define PCI_CHIP_RV770_9452 0x9452
+#define PCI_CHIP_RV770_9456 0x9456
+#define PCI_CHIP_RV770_945A 0x945A
+#define PCI_CHIP_RV770_945B 0x945B
+#define PCI_CHIP_RV790_9460 0x9460
+#define PCI_CHIP_RV790_9462 0x9462
+#define PCI_CHIP_RV770_946A 0x946A
+#define PCI_CHIP_RV770_946B 0x946B
+#define PCI_CHIP_RV770_947A 0x947A
+#define PCI_CHIP_RV770_947B 0x947B
+
+#define PCI_CHIP_RV730_9487 0x9487
+#define PCI_CHIP_RV730_9489 0x9489
+#define PCI_CHIP_RV730_948F 0x948F
+#define PCI_CHIP_RV730_9490 0x9490
+#define PCI_CHIP_RV730_9491 0x9491
+#define PCI_CHIP_RV730_9498 0x9498
+#define PCI_CHIP_RV730_949C 0x949C
+#define PCI_CHIP_RV730_949E 0x949E
+#define PCI_CHIP_RV730_949F 0x949F
+
+#define PCI_CHIP_RV710_9540 0x9540
+#define PCI_CHIP_RV710_9541 0x9541
+#define PCI_CHIP_RV710_9542 0x9542
+#define PCI_CHIP_RV710_954E 0x954E
+#define PCI_CHIP_RV710_954F 0x954F
+#define PCI_CHIP_RV710_9552 0x9552
+#define PCI_CHIP_RV710_9553 0x9553
+#define PCI_CHIP_RV710_9555 0x9555
+
+#define PCI_CHIP_RV740_94A0 0x94A0
+#define PCI_CHIP_RV740_94A1 0x94A1
+#define PCI_CHIP_RV740_94B1 0x94B1
+#define PCI_CHIP_RV740_94B3 0x94B3
+#define PCI_CHIP_RV740_94B5 0x94B5
enum {
CHIP_FAMILY_R100,
@@ -282,6 +407,17 @@ enum {
CHIP_FAMILY_R580,
CHIP_FAMILY_RV560,
CHIP_FAMILY_RV570,
+ CHIP_FAMILY_R600,
+ CHIP_FAMILY_RV610,
+ CHIP_FAMILY_RV630,
+ CHIP_FAMILY_RV670,
+ CHIP_FAMILY_RV620,
+ CHIP_FAMILY_RV635,
+ CHIP_FAMILY_RS780,
+ CHIP_FAMILY_RV770,
+ CHIP_FAMILY_RV730,
+ CHIP_FAMILY_RV710,
+ CHIP_FAMILY_RV740,
CHIP_FAMILY_LAST
};
@@ -289,6 +425,7 @@ enum {
#define RADEON_CLASS_R100 (0 << 0)
#define RADEON_CLASS_R200 (1 << 0)
#define RADEON_CLASS_R300 (2 << 0)
+#define RADEON_CLASS_R600 (3 << 0)
#define RADEON_CLASS_MASK (3 << 0)
#define RADEON_CHIPSET_TCL (1 << 2) /* tcl support - any radeon */
diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
index 4b5116c474..abb023c7de 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
+++ b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
@@ -16,33 +16,12 @@ void rcommonBeginBatch(radeonContextPtr rmesa,
const char *function,
int line);
-#define RADEON_CP_PACKET3_NOP 0xC0001000
-#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
-#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
-#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
-#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
-#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
-#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
-#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
-#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
-#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
-#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
-#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
-#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
-#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
-#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
-#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
-#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
-#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
-#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
-#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
-#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
+/* +r6/r7 : code here moved */
#define CP_PACKET2 (2 << 30)
#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
#define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
-#define CP_PACKET3( pkt, n ) \
- (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
+#define CP_PACKET3(pkt, n) (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
/**
* Every function writing to the command buffer needs to declare this
@@ -125,19 +104,20 @@ void rcommonBeginBatch(radeonContextPtr rmesa,
/** Continuous register range write to command buffer; requires 1 dword,
* expects count dwords afterwards for register contents. */
#define OUT_BATCH_REGSEQ(reg, count) \
- OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)));
+ OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
/** Write a 32 bit float to the ring; requires 1 dword. */
#define OUT_BATCH_FLOAT32(f) \
- OUT_BATCH(radeonPackFloat32((f)));
+ OUT_BATCH(radeonPackFloat32((f)))
+/* +r6/r7 : code here moved */
/* Fire the buffered vertices no matter what.
*/
static INLINE void radeon_firevertices(radeonContextPtr radeon)
{
if (radeon->cmdbuf.cs->cdw || radeon->dma.flush )
- radeonFlush(radeon->glCtx);
+ radeon->glCtx->Driver.Flush(radeon->glCtx); /* +r6/r7 */
}
#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 3bf42e9bb0..dde615a4d9 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -481,6 +481,32 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
if (!n)
continue;
+ if (IS_R600_CLASS(rmesa->radeonScreen)) {
+ int cpp = rmesa->radeonScreen->cpp;
+ int src_pitch = rmesa->radeonScreen->backPitch * cpp;
+ int dst_pitch = rmesa->radeonScreen->frontPitch * cpp;
+ char *src = (char *)rmesa->radeonScreen->driScreen->pFB + rmesa->radeonScreen->backOffset;
+ char *dst = (char *)rmesa->radeonScreen->driScreen->pFB + rmesa->radeonScreen->frontOffset;
+ int j;
+ drm_clip_rect_t *pb = rmesa->sarea->boxes;
+
+ for (j = 0; j < n; j++) {
+ int x = pb[j].x1;
+ int y = pb[j].y1;
+ int w = pb[j].x2 - x;
+ int h = pb[j].y2 - y;
+
+ src += (y * src_pitch) + (x * cpp);
+ dst += (y * dst_pitch) + (x * cpp);
+
+ while (h--) {
+ memcpy(dst, src, w * cpp);
+ src += src_pitch;
+ dst += dst_pitch;
+ }
+ }
+ }
+
ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP );
if ( ret ) {
@@ -1082,7 +1108,8 @@ void radeonFinish(GLcontext * ctx)
struct gl_framebuffer *fb = ctx->DrawBuffer;
int i;
- radeonFlush(ctx);
+ if (ctx->Driver.Flush)
+ ctx->Driver.Flush(ctx); /* +r6/r7 */
if (radeon->radeonScreen->kernel_mm) {
for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 9add50b4cc..bbe7225ee6 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -95,7 +95,9 @@ static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name)
switch (name) {
case GL_VENDOR:
- if (IS_R300_CLASS(radeon->radeonScreen))
+ if (IS_R600_CLASS(radeon->radeonScreen))
+ return (GLubyte *) "Advanced Micro Devices, Inc.";
+ else if (IS_R300_CLASS(radeon->radeonScreen))
return (GLubyte *) "DRI R300 Project";
else
return (GLubyte *) "Tungsten Graphics, Inc.";
@@ -108,7 +110,9 @@ static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name)
const char* chipclass;
char hardwarename[32];
- if (IS_R300_CLASS(radeon->radeonScreen))
+ if (IS_R600_CLASS(radeon->radeonScreen))
+ chipclass = "R600";
+ else if (IS_R300_CLASS(radeon->radeonScreen))
chipclass = "R300";
else if (IS_R200_CLASS(radeon->radeonScreen))
chipclass = "R200";
@@ -123,7 +127,9 @@ static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name)
offset = driGetRendererString(buffer, hardwarename, DRIVER_DATE,
agp_mode);
- if (IS_R300_CLASS(radeon->radeonScreen)) {
+ if (IS_R600_CLASS(radeon->radeonScreen)) {
+ sprintf(&buffer[offset], " TCL");
+ } else if (IS_R300_CLASS(radeon->radeonScreen)) {
sprintf(&buffer[offset], " %sTCL",
(radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)
? "" : "NO-");
@@ -200,8 +206,11 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode");
radeon->iw.irq_seq = -1;
radeon->irqsEmitted = 0;
- radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
- radeon->radeonScreen->irq);
+ if (IS_R600_CLASS(radeon->radeonScreen))
+ radeon->do_irqs = 0;
+ else
+ radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
+ radeon->radeonScreen->irq);
radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
@@ -252,13 +261,26 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
+ /* +r6/r7 */
+ __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
+ radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
+ /* --------- */
+
if (radeon == current) {
radeon_firevertices(radeon);
_mesa_make_current(NULL, NULL, NULL);
}
assert(radeon);
- if (radeon) {
+ if (radeon)
+ {
+
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
+ if (IS_R600_CLASS(screen))
+ {
+ r600DestroyContext(driContextPriv);
+ }
+#endif
if (radeon->dma.current) {
rcommonFlushCmdBuf( radeon, __FUNCTION__ );
@@ -287,6 +309,9 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
rcommonDestroyCmdBuf(radeon);
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
+ if (!IS_R600_CLASS(screen))
+#endif
radeon_destroy_atom_list(radeon);
if (radeon->state.scissor.pClipRects) {
@@ -327,48 +352,88 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
if (!rb->bo) {
+#ifdef RADEON_DEBUG_BO
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->frontOffset,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0,
+ "Front Buf");
+#else
rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
radeon->radeonScreen->frontOffset,
0,
0,
RADEON_GEM_DOMAIN_VRAM,
0);
+#endif /* RADEON_DEBUG_BO */
}
rb->cpp = radeon->radeonScreen->cpp;
rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
}
if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
if (!rb->bo) {
+#ifdef RADEON_DEBUG_BO
rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
radeon->radeonScreen->backOffset,
0,
0,
RADEON_GEM_DOMAIN_VRAM,
+ 0,
+ "Back Buf");
+#else
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->backOffset,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
0);
+#endif /* RADEON_DEBUG_BO */
}
rb->cpp = radeon->radeonScreen->cpp;
rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
}
if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
if (!rb->bo) {
+#ifdef RADEON_DEBUG_BO
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->depthOffset,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0,
+ "Z Buf");
+#else
rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
radeon->radeonScreen->depthOffset,
0,
0,
RADEON_GEM_DOMAIN_VRAM,
0);
+#endif /* RADEON_DEBUG_BO */
}
rb->cpp = radeon->radeonScreen->cpp;
rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
}
if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
if (!rb->bo) {
+#ifdef RADEON_DEBUG_BO
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->depthOffset,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0,
+ "Stencil Buf");
+#else
rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
radeon->radeonScreen->depthOffset,
0,
0,
RADEON_GEM_DOMAIN_VRAM,
0);
+#endif /* RADEON_DEBUG_BO */
}
rb->cpp = radeon->radeonScreen->cpp;
rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
@@ -391,6 +456,16 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
if (!rb->bo) {
+#ifdef RADEON_DEBUG_BO
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->frontOffset +
+ radeon->radeonScreen->fbLocation,
+ size,
+ 4096,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0,
+ "Front Buf");
+#else
rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
radeon->radeonScreen->frontOffset +
radeon->radeonScreen->fbLocation,
@@ -398,12 +473,23 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
4096,
RADEON_GEM_DOMAIN_VRAM,
0);
+#endif /* RADEON_DEBUG_BO */
}
rb->cpp = radeon->radeonScreen->cpp;
rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
}
if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
if (!rb->bo) {
+#ifdef RADEON_DEBUG_BO
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->backOffset +
+ radeon->radeonScreen->fbLocation,
+ size,
+ 4096,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0,
+ "Back Buf");
+#else
rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
radeon->radeonScreen->backOffset +
radeon->radeonScreen->fbLocation,
@@ -411,32 +497,55 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
4096,
RADEON_GEM_DOMAIN_VRAM,
0);
+#endif /* RADEON_DEBUG_BO */
}
rb->cpp = radeon->radeonScreen->cpp;
rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
}
if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
if (!rb->bo) {
+#ifdef RADEON_DEBUG_BO
rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
radeon->radeonScreen->depthOffset +
radeon->radeonScreen->fbLocation,
size,
4096,
RADEON_GEM_DOMAIN_VRAM,
+ 0,
+ "Z Buf");
+#else
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->depthOffset +
+ radeon->radeonScreen->fbLocation,
+ size,
+ 4096,
+ RADEON_GEM_DOMAIN_VRAM,
0);
+#endif /* RADEON_DEBUG_BO */
}
rb->cpp = radeon->radeonScreen->cpp;
rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
}
if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
if (!rb->bo) {
+#ifdef RADEON_DEBUG_BO
rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
radeon->radeonScreen->depthOffset +
radeon->radeonScreen->fbLocation,
size,
4096,
RADEON_GEM_DOMAIN_VRAM,
+ 0,
+ "Stencil Buf");
+#else
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ radeon->radeonScreen->depthOffset +
+ radeon->radeonScreen->fbLocation,
+ size,
+ 4096,
+ RADEON_GEM_DOMAIN_VRAM,
0);
+#endif /* RADEON_DEBUG_BO */
}
rb->cpp = radeon->radeonScreen->cpp;
rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
@@ -619,12 +728,22 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
bo = depth_bo;
radeon_bo_ref(bo);
} else {
+#ifdef RADEON_DEBUG_BO
+ bo = radeon_bo_open(radeon->radeonScreen->bom,
+ buffers[i].name,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ buffers[i].flags,
+ regname);
+#else
bo = radeon_bo_open(radeon->radeonScreen->bom,
buffers[i].name,
0,
0,
RADEON_GEM_DOMAIN_VRAM,
buffers[i].flags);
+#endif /* RADEON_DEBUG_BO */
if (bo == NULL) {
fprintf(stderr, "failed to attach %s %d\n",
@@ -698,7 +817,6 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
radeon_make_renderbuffer_current(radeon, drfb);
}
-
if (RADEON_DEBUG & DEBUG_DRI)
fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb);
@@ -736,6 +854,7 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
if (RADEON_DEBUG & DEBUG_DRI)
fprintf(stderr, "End %s\n", __FUNCTION__);
+
return GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 07ac85fb52..e4a8da0596 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -226,6 +226,19 @@ struct radeon_tex_obj {
GLuint pp_txfilter_1; /* r300 */
+ /* r700 texture states */
+ GLuint SQ_TEX_RESOURCE0;
+ GLuint SQ_TEX_RESOURCE1;
+ GLuint SQ_TEX_RESOURCE2;
+ GLuint SQ_TEX_RESOURCE3;
+ GLuint SQ_TEX_RESOURCE4;
+ GLuint SQ_TEX_RESOURCE5;
+ GLuint SQ_TEX_RESOURCE6;
+
+ GLuint SQ_TEX_SAMPLER0;
+ GLuint SQ_TEX_SAMPLER1;
+ GLuint SQ_TEX_SAMPLER2;
+
GLboolean border_fallback;
@@ -574,4 +587,10 @@ extern int RADEON_DEBUG;
#define RADEON_DEBUG 0
#endif
+#ifndef HAVE_LIBDRM_RADEON
+#ifndef RADEON_DEBUG_BO
+#define RADEON_DEBUG_BO 1
+#endif
+#endif
+
#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
index f77e22c437..4f1065ebcf 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
@@ -216,22 +216,28 @@ static int cs_process_relocs(struct radeon_cs *cs)
csm = (struct cs_manager_legacy*)cs->csm;
relocs = (struct cs_reloc_legacy *)cs->relocs;
- restart:
- for (i = 0; i < cs->crelocs; i++) {
- for (j = 0; j < relocs[i].cindices; j++) {
+restart:
+ for (i = 0; i < cs->crelocs; i++)
+ {
+ for (j = 0; j < relocs[i].cindices; j++)
+ {
uint32_t soffset, eoffset;
r = radeon_bo_legacy_validate(relocs[i].base.bo,
&soffset, &eoffset);
- if (r == -EAGAIN)
- goto restart;
- if (r) {
+ if (r == -EAGAIN)
+ {
+ goto restart;
+ }
+ if (r)
+ {
fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
relocs[i].base.bo, soffset, eoffset);
return r;
}
cs->packets[relocs[i].indices[j]] += soffset;
- if (cs->packets[relocs[i].indices[j]] >= eoffset) {
+ if (cs->packets[relocs[i].indices[j]] >= eoffset)
+ {
/* radeon_bo_debug(relocs[i].base.bo, 12); */
fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
relocs[i].base.bo, soffset, eoffset);
@@ -272,7 +278,8 @@ static int cs_emit(struct radeon_cs *cs)
csm->ctx->vtbl.emit_cs_header(cs, csm->ctx);
/* append buffer age */
- if (IS_R300_CLASS(csm->ctx->radeonScreen)) {
+ if ( IS_R300_CLASS(csm->ctx->radeonScreen) )
+ {
age.scratch.cmd_type = R300_CMD_SCRATCH;
/* Scratch register 2 corresponds to what radeonGetAge polls */
csm->pending_age = 0;
@@ -307,7 +314,8 @@ static int cs_emit(struct radeon_cs *cs)
if (r) {
return r;
}
- if (!IS_R300_CLASS(csm->ctx->radeonScreen)) {
+ if ((!IS_R300_CLASS(csm->ctx->radeonScreen)) &&
+ (!IS_R600_CLASS(csm->ctx->radeonScreen))) { /* +r6/r7 : No irq for r6/r7 yet. */
drm_radeon_irq_emit_t emit_cmd;
emit_cmd.irq_seq = &csm->pending_age;
r = drmCommandWrite(cs->csm->fd, DRM_RADEON_IRQ_EMIT, &emit_cmd, sizeof(emit_cmd));
diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c
index 84bd1ec9d0..48114a0012 100644
--- a/src/mesa/drivers/dri/radeon/radeon_dma.c
+++ b/src/mesa/drivers/dri/radeon/radeon_dma.c
@@ -184,10 +184,16 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size)
rmesa->dma.current = 0;
}
-again_alloc:
+again_alloc:
+#ifdef RADEON_DEBUG_BO
+ rmesa->dma.current = radeon_bo_open(rmesa->radeonScreen->bom,
+ 0, size, 4, RADEON_GEM_DOMAIN_GTT,
+ 0, "dma.current");
+#else
rmesa->dma.current = radeon_bo_open(rmesa->radeonScreen->bom,
0, size, 4, RADEON_GEM_DOMAIN_GTT,
0);
+#endif /* RADEON_DEBUG_BO */
if (!rmesa->dma.current) {
rcommonFlushCmdBuf(rmesa, __FUNCTION__);
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index 6d8417cc89..f28efa33e9 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -165,7 +165,8 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
return GL_FALSE;
}
- radeonFlush(ctx);
+ if (ctx->Driver.Flush)
+ ctx->Driver.Flush(ctx); /* +r6/r7 */
if (rrb->bo)
radeon_bo_unref(rrb->bo);
@@ -184,12 +185,22 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
rrb->pitch = pitch * cpp;
rrb->cpp = cpp;
+#ifdef RADEON_DEBUG_BO
+ rrb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ 0,
+ size,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0,
+ "Radeon RBO");
+#else
rrb->bo = radeon_bo_open(radeon->radeonScreen->bom,
0,
size,
0,
RADEON_GEM_DOMAIN_VRAM,
0);
+#endif /* RADEON_DEBUG_BO */
rb->Width = width;
rb->Height = height;
return GL_TRUE;
@@ -371,7 +382,8 @@ radeon_framebuffer_renderbuffer(GLcontext * ctx,
GLenum attachment, struct gl_renderbuffer *rb)
{
- radeonFlush(ctx);
+ if (ctx->Driver.Flush)
+ ctx->Driver.Flush(ctx); /* +r6/r7 */
_mesa_framebuffer_renderbuffer(ctx, fb, attachment, rb);
radeon_draw_buffer(ctx, fb);
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 55aa4502da..f04a07fecd 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -212,10 +212,18 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *
else
calculate_miptree_layout_r100(rmesa, mt);
+#ifdef RADEON_DEBUG_BO
+ mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
+ 0, mt->totalsize, 1024,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0,
+ "MIPMAP TREE");
+#else
mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
0, mt->totalsize, 1024,
RADEON_GEM_DOMAIN_VRAM,
0);
+#endif /* RADEON_DEBUG_BO */
return mt;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 12ae4ada5d..355fa8683a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -59,6 +59,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r300_context.h"
#include "r300_fragprog.h"
#include "r300_tex.h"
+#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+#include "r600_context.h"
+#include "r700_driconf.h" /* +r6/r7 */
+#include "r600_tex.h" /* +r6/r7 */
#endif
#include "utils.h"
@@ -144,7 +148,7 @@ extern const struct dri_extension NV_vp_extension[];
extern const struct dri_extension ATI_fs_extension[];
extern const struct dri_extension point_extensions[];
-#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+#elif RADEON_COMMON && (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
/* TODO: integrate these into xmlpool.h! */
#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
@@ -398,6 +402,19 @@ static const __DRItexBufferExtension r300TexBufferExtension = {
};
#endif
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+static const __DRItexOffsetExtension r600texOffsetExtension = {
+ { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
+ r600SetTexOffset, /* +r6/r7 */
+};
+
+static const __DRItexBufferExtension r600TexBufferExtension = {
+ { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
+ r600SetTexBuffer, /* +r6/r7 */
+ r600SetTexBuffer2, /* +r6/r7 */
+};
+#endif
+
static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
{
screen->device_id = device_id;
@@ -734,6 +751,165 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
+ case PCI_CHIP_R600_9400:
+ case PCI_CHIP_R600_9401:
+ case PCI_CHIP_R600_9402:
+ case PCI_CHIP_R600_9403:
+ case PCI_CHIP_R600_9405:
+ case PCI_CHIP_R600_940A:
+ case PCI_CHIP_R600_940B:
+ case PCI_CHIP_R600_940F:
+ screen->chip_family = CHIP_FAMILY_R600;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV610_94C0:
+ case PCI_CHIP_RV610_94C1:
+ case PCI_CHIP_RV610_94C3:
+ case PCI_CHIP_RV610_94C4:
+ case PCI_CHIP_RV610_94C5:
+ case PCI_CHIP_RV610_94C6:
+ case PCI_CHIP_RV610_94C7:
+ case PCI_CHIP_RV610_94C8:
+ case PCI_CHIP_RV610_94C9:
+ case PCI_CHIP_RV610_94CB:
+ case PCI_CHIP_RV610_94CC:
+ case PCI_CHIP_RV610_94CD:
+ screen->chip_family = CHIP_FAMILY_RV610;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV630_9580:
+ case PCI_CHIP_RV630_9581:
+ case PCI_CHIP_RV630_9583:
+ case PCI_CHIP_RV630_9586:
+ case PCI_CHIP_RV630_9587:
+ case PCI_CHIP_RV630_9588:
+ case PCI_CHIP_RV630_9589:
+ case PCI_CHIP_RV630_958A:
+ case PCI_CHIP_RV630_958B:
+ case PCI_CHIP_RV630_958C:
+ case PCI_CHIP_RV630_958D:
+ case PCI_CHIP_RV630_958E:
+ case PCI_CHIP_RV630_958F:
+ screen->chip_family = CHIP_FAMILY_RV630;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV670_9500:
+ case PCI_CHIP_RV670_9501:
+ case PCI_CHIP_RV670_9504:
+ case PCI_CHIP_RV670_9505:
+ case PCI_CHIP_RV670_9506:
+ case PCI_CHIP_RV670_9507:
+ case PCI_CHIP_RV670_9508:
+ case PCI_CHIP_RV670_9509:
+ case PCI_CHIP_RV670_950F:
+ case PCI_CHIP_RV670_9511:
+ case PCI_CHIP_RV670_9515:
+ case PCI_CHIP_RV670_9517:
+ case PCI_CHIP_RV670_9519:
+ screen->chip_family = CHIP_FAMILY_RV670;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV620_95C0:
+ case PCI_CHIP_RV620_95C2:
+ case PCI_CHIP_RV620_95C4:
+ case PCI_CHIP_RV620_95C5:
+ case PCI_CHIP_RV620_95C6:
+ case PCI_CHIP_RV620_95C7:
+ case PCI_CHIP_RV620_95C9:
+ case PCI_CHIP_RV620_95CC:
+ case PCI_CHIP_RV620_95CD:
+ case PCI_CHIP_RV620_95CE:
+ case PCI_CHIP_RV620_95CF:
+ screen->chip_family = CHIP_FAMILY_RV620;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV635_9590:
+ case PCI_CHIP_RV635_9591:
+ case PCI_CHIP_RV635_9593:
+ case PCI_CHIP_RV635_9595:
+ case PCI_CHIP_RV635_9596:
+ case PCI_CHIP_RV635_9597:
+ case PCI_CHIP_RV635_9598:
+ case PCI_CHIP_RV635_9599:
+ case PCI_CHIP_RV635_959B:
+ screen->chip_family = CHIP_FAMILY_RV635;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RS780_9610:
+ case PCI_CHIP_RS780_9611:
+ case PCI_CHIP_RS780_9612:
+ case PCI_CHIP_RS780_9613:
+ case PCI_CHIP_RS780_9614:
+ case PCI_CHIP_RS780_9615:
+ case PCI_CHIP_RS780_9616:
+ screen->chip_family = CHIP_FAMILY_RS780;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV770_9440:
+ case PCI_CHIP_RV770_9441:
+ case PCI_CHIP_RV770_9442:
+ case PCI_CHIP_RV770_9444:
+ case PCI_CHIP_RV770_9446:
+ case PCI_CHIP_RV770_944A:
+ case PCI_CHIP_RV770_944B:
+ case PCI_CHIP_RV770_944C:
+ case PCI_CHIP_RV770_944E:
+ case PCI_CHIP_RV770_9450:
+ case PCI_CHIP_RV770_9452:
+ case PCI_CHIP_RV770_9456:
+ case PCI_CHIP_RV770_945A:
+ case PCI_CHIP_RV770_945B:
+ case PCI_CHIP_RV790_9460:
+ case PCI_CHIP_RV790_9462:
+ case PCI_CHIP_RV770_946A:
+ case PCI_CHIP_RV770_946B:
+ case PCI_CHIP_RV770_947A:
+ case PCI_CHIP_RV770_947B:
+ screen->chip_family = CHIP_FAMILY_RV770;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV730_9487:
+ case PCI_CHIP_RV730_9489:
+ case PCI_CHIP_RV730_948F:
+ case PCI_CHIP_RV730_9490:
+ case PCI_CHIP_RV730_9491:
+ case PCI_CHIP_RV730_9498:
+ case PCI_CHIP_RV730_949C:
+ case PCI_CHIP_RV730_949E:
+ case PCI_CHIP_RV730_949F:
+ screen->chip_family = CHIP_FAMILY_RV730;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV710_9540:
+ case PCI_CHIP_RV710_9541:
+ case PCI_CHIP_RV710_9542:
+ case PCI_CHIP_RV710_954E:
+ case PCI_CHIP_RV710_954F:
+ case PCI_CHIP_RV710_9552:
+ case PCI_CHIP_RV710_9553:
+ case PCI_CHIP_RV710_9555:
+ screen->chip_family = CHIP_FAMILY_RV710;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RV740_94A0:
+ case PCI_CHIP_RV740_94A1:
+ case PCI_CHIP_RV740_94B1:
+ case PCI_CHIP_RV740_94B3:
+ case PCI_CHIP_RV740_94B5:
+ screen->chip_family = CHIP_FAMILY_RV740;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
default:
fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
device_id);
@@ -772,7 +948,6 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
#endif
-
/* parse information in __driConfigOptions */
driParseOptionInfo (&screen->optionCache,
__driConfigOptions, __driNConfigOptions);
@@ -817,6 +992,10 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
}
+ ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
+ if (ret == -1)
+ return NULL;
+
screen->mmio.handle = dri_priv->registerHandle;
screen->mmio.size = dri_priv->registerSize;
if ( drmMap( sPriv->fd,
@@ -841,8 +1020,12 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
__driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
return NULL;
}
- screen->scratch = (__volatile__ uint32_t *)
- ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
+ if (screen->chip_family < CHIP_FAMILY_R600)
+ screen->scratch = (__volatile__ uint32_t *)
+ ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
+ else
+ screen->scratch = (__volatile__ uint32_t *)
+ ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
screen->buffers = drmMapBufs( sPriv->fd );
if ( !screen->buffers ) {
@@ -871,10 +1054,6 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
}
- ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
- if (ret == -1)
- return NULL;
-
if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
sPriv->ddx_version.minor < 2) {
fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
@@ -887,32 +1066,56 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
}
if (getenv("R300_NO_TCL"))
- screen->chip_flags &= ~RADEON_CHIPSET_TCL;
+ screen->chip_flags &= ~RADEON_CHIPSET_TCL;
if (screen->chip_family <= CHIP_FAMILY_RS200)
- screen->chip_flags |= RADEON_CLASS_R100;
+ screen->chip_flags |= RADEON_CLASS_R100;
else if (screen->chip_family <= CHIP_FAMILY_RV280)
- screen->chip_flags |= RADEON_CLASS_R200;
+ screen->chip_flags |= RADEON_CLASS_R200;
+ else if (screen->chip_family <= CHIP_FAMILY_RV570)
+ screen->chip_flags |= RADEON_CLASS_R300;
else
- screen->chip_flags |= RADEON_CLASS_R300;
+ screen->chip_flags |= RADEON_CLASS_R600;
screen->cpp = dri_priv->bpp / 8;
screen->AGPMode = dri_priv->AGPMode;
ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
- if (ret) {
- if (screen->chip_family < CHIP_FAMILY_RS600)
- screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
- else {
- FREE( screen );
- fprintf(stderr, "Unable to get fb location need newer drm\n");
- return NULL;
+
+ /* +r6/r7 */
+ if(screen->chip_family >= CHIP_FAMILY_R600)
+ {
+ if (ret)
+ {
+ FREE( screen );
+ fprintf(stderr, "Unable to get fb location need newer drm\n");
+ return NULL;
+ }
+ else
+ {
+ screen->fbLocation = (temp & 0xffff) << 24;
}
- } else {
- screen->fbLocation = (temp & 0xffff) << 16;
+ }
+ else
+ {
+ if (ret)
+ {
+ if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
+ screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
+ else
+ {
+ FREE( screen );
+ fprintf(stderr, "Unable to get fb location need newer drm\n");
+ return NULL;
+ }
+ }
+ else
+ {
+ screen->fbLocation = (temp & 0xffff) << 16;
+ }
}
- if (screen->chip_family >= CHIP_FAMILY_R300) {
+ if (IS_R300_CLASS(screen)) {
ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
if (ret) {
fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
@@ -1028,6 +1231,10 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->extensions[i++] = &r300texOffsetExtension.base;
#endif
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+ screen->extensions[i++] = &r600texOffsetExtension.base;
+#endif
+
screen->extensions[i++] = NULL;
sPriv->extensions = screen->extensions;
@@ -1095,7 +1302,19 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv)
if (ret == -1)
return NULL;
- if (screen->chip_family >= CHIP_FAMILY_R300) {
+ if (getenv("R300_NO_TCL"))
+ screen->chip_flags &= ~RADEON_CHIPSET_TCL;
+
+ if (screen->chip_family <= CHIP_FAMILY_RS200)
+ screen->chip_flags |= RADEON_CLASS_R100;
+ else if (screen->chip_family <= CHIP_FAMILY_RV280)
+ screen->chip_flags |= RADEON_CLASS_R200;
+ else if (screen->chip_family <= CHIP_FAMILY_RV570)
+ screen->chip_flags |= RADEON_CLASS_R300;
+ else
+ screen->chip_flags |= RADEON_CLASS_R600;
+
+ if (IS_R300_CLASS(screen)) {
ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
if (ret) {
fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
@@ -1136,16 +1355,6 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv)
}
- if (screen->chip_family <= CHIP_FAMILY_RS200)
- screen->chip_flags |= RADEON_CLASS_R100;
- else if (screen->chip_family <= CHIP_FAMILY_RV280)
- screen->chip_flags |= RADEON_CLASS_R200;
- else
- screen->chip_flags |= RADEON_CLASS_R300;
-
- if (getenv("R300_NO_TCL"))
- screen->chip_flags &= ~RADEON_CHIPSET_TCL;
-
i = 0;
screen->extensions[i++] = &driCopySubBufferExtension.base;
screen->extensions[i++] = &driFrameTrackingExtension.base;
@@ -1171,6 +1380,10 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv)
screen->extensions[i++] = &r300TexBufferExtension.base;
#endif
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+ screen->extensions[i++] = &r600TexBufferExtension.base;
+#endif
+
screen->extensions[i++] = NULL;
sPriv->extensions = screen->extensions;
@@ -1364,6 +1577,11 @@ static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
{
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+ if (IS_R600_CLASS(screen))
+ return r600CreateContext(glVisual, driContextPriv, sharedContextPriv);
+#endif
+
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
if (IS_R300_CLASS(screen))
return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
@@ -1407,6 +1625,11 @@ radeonInitScreen(__DRIscreenPrivate *psp)
static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
static const __DRIversion dri_expected = { 4, 0, 0 };
static const __DRIversion drm_expected = { 1, 24, 0 };
+#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
+ static const char *driver_name = "R600";
+ static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
+ static const __DRIversion dri_expected = { 4, 0, 0 };
+ static const __DRIversion drm_expected = { 1, 24, 0 };
#endif
RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
@@ -1434,7 +1657,7 @@ radeonInitScreen(__DRIscreenPrivate *psp)
driInitSingleExtension( NULL, NV_vp_extension );
driInitSingleExtension( NULL, ATI_fs_extension );
driInitExtensions( NULL, point_extensions, GL_FALSE );
-#elif defined(RADEON_COMMON_FOR_R300)
+#elif (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
driInitSingleExtension( NULL, gl_20_extension );
#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h
index fe5c7d875a..2a2f6b1b0b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -118,6 +118,8 @@ typedef struct radeon_screen {
((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R200)
#define IS_R300_CLASS(screen) \
((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R300)
+#define IS_R600_CLASS(screen) \
+ ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R600)
extern void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv);
#endif /* __RADEON_SCREEN_H__ */
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
index 7dfed2c456..ad501c454c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -965,6 +965,7 @@ int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *t
if (t->mt == image->mt) {
if (RADEON_DEBUG & DEBUG_TEXTURE)
fprintf(stderr, "OK\n");
+
continue;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-12 05:20:38 +0000