| Age | Commit message (Collapse) | Author |
|---|
|
The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's
had been improved, and pixel_w should no longer stomp on a neighbor to dst.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
This drops support for get_src_reg_imm in these, but the prospect of getting
brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
|
|
Previously, it was trying to mess around with the varying's
WM setup data to produce a result. Along with not actually working when
passed a varying, this wouldn't work if you did dFd[xy]() on a temporary.
Instead, just calculate the derivative using the neighbors in the subspan.
|
|
I ran into this lack of support when writing a shader that always discarded
the fragments.
|
|
|
|
DPH can output to any component, not just to X. This allows fpalu.c
to run without hitting the assertion in emit_dph.
|
|
This is preparation for merging of brw_wm_glsl.c and
brw_wm_emit.c, and glsl.c doesn't swizzle channel results around.
|
|
|
|
I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out,
and running intel-gen4disasm on it.
|
|
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
|
|
1. the data type of <src1> (JMPI offset) must be D
2. execution size must be 1
3. NoMask
4. instruction compression isn't allowed.
|
|
the driver used to overwrite grf0 then use implicit move by send instruction
to move contents of grf0 to mrf1. However, we must not overwrite grf0 since
it's still used later for fb write.
Instead, do the move directly do mrf1 (we could use implicit move from another
grf reg to mrf1 but since we need a mov to encode the data anyway it doesn't
seem to make sense).
I think the dp_READ/WRITE_16 functions may suffer from the same issue.
While here also remove unnecessary msg_reg_nr parameter from the dataport
functions since always message register 1 is used.
|
|
This gets two more glean glsl1 tests using the non-GLSL path.
|
|
Used to map drawables, textures and constant buffers to surface binding
table indexes.
|
|
|
|
This also cuts instructions by just using the existing bit in the payload
rather than computing it from the determinant in the SF unit and passing it
as a varying down to the WM. Something still goes wrong with getting the
backface color right, but a simpler shader appears to get the right result.
|
|
|
|
GLSL shadow() sampler calls are properly propogated down to the driver now.
The glean glsl1 shadow() tests work (except for the alpha channel).
|
|
|
|
|
|
Makefile.template
|
|
Numbers of destination depth registers corrected (destination stencil
register was sent as depth register).
|
|
|
|
|
|
The pass1 optimization stage clears out writemasks and registers, but the
instructions themselves are still being processed at this stage, and could
have resulted in them still being emitted.
|
|
|
|
|
|
|
|
|
|
|
|
Pixel Mask Copy is modified as the pixel shader thread
turns off pixels based on kill instructions.
|
|
1. spec requite result (0, 0, 0, 1) instead of (0, 0, 0, 0)
2. support shadow sampler in simd8
|
|
most of the sample working with some small modification
|
|
|
|
Mostly:
- update #includes
- update STATE_* token code
|
|
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
|
