summaryrefslogtreecommitdiff
path: root/src/mesa/drivers/dri/i965
AgeCommit message (Collapse)Author
2007-03-18i965: fix for FXT1 & S3TC texture formatXiang, Haihao
choose the right mesa texformat for FXT1 & S3TC
2007-03-14Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu
2007-03-13sync up t_vp_build.c brw_vs_tnl.c a bitRoland Scheidegger
Bring over the optimizations for fog and normalized spot dir from t_vp_build.c to brw_vs_tnl.c. Likewise, port a fix for point size calc from brw_vs_tnl.c to t_vp_build.c (use ABS(eyez) instead of -eyez). Leave the now differing point size calcs alone though, not sure what's better (it's basically MOV, ABS, MUL, DP3 vs. ABS, MAD, MAD).
2007-03-12Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu
2007-03-11fix for bug#10196Xiang, Haihao
Compute half if LOCAL_VIEWER is enabled and the light is a directional source.
2007-03-09Merge branch 'origin' into glsl-compiler-1Brian
Conflicts: src/mesa/main/context.c
2007-03-07Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu
2007-03-06Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu
2007-03-06Fix/improve framebuffer object reference counting.Brian
Use _mesa_reference_framebuffer() and _mesa_unreference_framebuffer() functions to be sure reference counting is done correctly. Additional assertions are done too. Note _mesa_dereference_framebuffer() renamed to "unreference" as that's more accurate.
2007-03-06Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu
2007-03-06fix for bug#10182Xiang, Haihao
call _mesa_dereference_framebuffer instead of _mesa_dereference_framebuffer in i810, i915, i915tex, i965 drivers.
2007-03-05fix for bug#9971Xiang, Haihao
call swsetup_Wakeup before falling back to software rendering
2007-02-25Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu
2007-02-23Update DRI drivers for new glsl compiler.Brian
Mostly: - update #includes - update STATE_* token code
2007-02-12I965: fix a failure on waiting irq.Xiang, Haihao
Wait until getting the right fence if drm/i915 resets the counter.
2007-02-02Merge branch 'vbo-0.2'Keith Whitwell
Conflicts: src/mesa/main/texcompress_s3tc.c src/mesa/tnl/t_array_api.c
2007-02-02Modify assert to reflect rebase criteriaKeith Whitwell
2007-02-02Add Intel 965GM chipset infoWang Zhenyu
2007-02-02Revert origin crestline pci id patchWang Zhenyu
2007-02-01Correct usage/meaning of max_index parameter.Keith Whitwell
2007-02-01Cope with internally-generated null inputs.Keith Whitwell
2007-01-30Use new rebase helper. Remove other rebase code.Keith Whitwell
2007-01-26Bug #9604: Fix a static buffer allocation failure.Eric Anholt
The pool that the static buffer got allocated from was sized by pitch * height, but the buffer generated from it had its size aligned to a tile boundary, so allocation failed if pitch * height wasn't aligned. However, the 2d driver ensures that the size ends at a tile boundary, so just pass the 2d driver's buffer size rather than calculating it.
2007-01-26Add _mesa_ffsll() for compatibility on OSes without ffsll(), and use it.Eric Anholt
2007-01-26Remove dead code causing a warning.Eric Anholt
2007-01-26ARB_Occlusion_query should support multiple query at same timeZou Nan hai
2007-01-24965 glxswapcontrol fixZou Nan hai
2007-01-24 965 ARB_Occlusion_query fixZou Nan hai
2007-01-181. Fix bug #155Zou Nan hai
2. I notice multiple ARB_occlusion_query should be able to overlap according to spec. 3. Declaring extern variables in a .c file is evil, fix it.
2007-01-17I965: fix bug#9625-get the correct PV for quardstripXiang, Haihao
The order of vertices in payload for quardstrip is (0, 1, 3, 2), so the PV for quardstrip is c->reg.vertex[2].
2007-01-16Merge branch 'master' of git+ssh://keithw@git.freedesktop.org/git/mesa/mesa ↵Keith Whitwell
into vbo-0.2 Conflicts: src/mesa/array_cache/sources src/mesa/drivers/dri/i965/brw_context.c src/mesa/drivers/dri/i965/brw_draw.c src/mesa/drivers/dri/i965/brw_fallback.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/i965/brw_vs_tnl.c src/mesa/drivers/dri/mach64/mach64_context.c src/mesa/main/extensions.c src/mesa/main/getstring.c src/mesa/tnl/sources src/mesa/tnl/t_save_api.c src/mesa/tnl/t_save_playback.c src/mesa/tnl/t_vtx_api.c src/mesa/tnl/t_vtx_exec.c src/mesa/vbo/vbo_attrib.h src/mesa/vbo/vbo_exec_api.c src/mesa/vbo/vbo_save_api.c src/mesa/vbo/vbo_save_draw.c
2007-01-06Merge branch 'master' into crestlineKeith Packard
2007-01-06Various warning fixes for i965 driver.Keith Packard
vertex/fragment programs provided as const. bmSetFenceLock should return bmSetFence value.
2007-01-06Initialize GL_ARB_occlusion_query only if DRM support is present.Keith Packard
DRM versions before 1.8 do not include the necessary ioctls to support GL_ARB_occlusion_query, don't enable it on these versions.
2007-01-06Merge branch 'master' into crestlineWang Zhenyu
Conflicts: src/mesa/drivers/dri/i965/brw_tex_layout.c Michel Dänzer replaced the copy of the 945 mipmap layout code with that from the 945 driver directly.
2007-01-06i965: xdemos/glxthreads get: Assertion `block->fenced' failed (9201)Zou Nan hai
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2007-01-06i965: Take clip rects into account when computing max primZou Nan hai
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2007-01-06i965: ARB_occlusion_query supportWang Zhenyu
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2007-01-06i965: Avoid branch instructions while in single program flow mode.Eric Anholt
There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2007-01-06i965: Connect INTEL_DEBUG=sync up to cmd/batch ioctls.Eric Anholt
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-12-30Use the tiled flag in the sarea to determine region tiling.Haihao Xiang
This fixes mis-rendering if back/depth fail to get set up as tiled. While it probably won't ever be the case now that the pitch limits are loosened, this is still the right thing to do.
2006-12-26Support linear format in i965.Haihao Xiang
Fix bug #117 #118
2006-12-14Share code to lay out >= 945 style 2D mipmaps between i915tex and i965 drivers.Michel Dänzer
Use the i965 version as it has some fixes over the i915tex version.
2006-12-13Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu
2006-12-13 Fix bug #93, i965 driver not thread safe.Zou Nan hai
I am not confident of it is 100% thread safe now. bufmgr_fake.c need a total rewrite later (cherry picked from 606632ca27558ee1335be2f4a5906f2baa240a6a commit)
2006-12-13 fix bug #99.Zou Nan hai
prim_count overflow when there is more than 1 cliprect (cherry picked from 84b958d66fe7d3fe03ed12b493e3f3197f656531 commit)
2006-12-13ARB_occlusion_query supportZou Nan hai
2006-12-13if (tex width < 4), mipmap calculation will be out of rangeZou Nan hai
2006-12-10Avoid branch instructions while in single program flow mode.Eric Anholt
There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary.
2006-12-10Connect INTEL_DEBUG=sync up to cmd/batch ioctls.Eric Anholt
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 14:49:33 +0000