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path: root/src/mesa/drivers/dri/i965
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2009-12-11Merge branch 'mesa_7_7_branch'Brian Paul
Conflicts: src/gallium/state_trackers/xorg/xorg_xv.c src/mesa/drivers/dri/intel/intel_span.c
2009-12-10intel: Remove ARGB internal_format == GL_RGB hacksIan Romanick
Now that XRGB is supported, we don't need to hack around cases of an RGBA format buffer with an internal format of GL_RGB.
2009-12-10i965: Fix handling of drawing to MESA_FORMAT_XRGB8888Ian Romanick
It turns out that 965 and friends cannot actually render to an xRGB surfaces. Instead, the surface has to be RGBA with writes to alpha disabled and the blend function modified to always use 1.0 for destination alpha.
2009-12-10intel: Axe intel_renderbuffer::texformatIan Romanick
Since the texformat branch merge, the value of intel_renderbuffer::texformat is just a copy of gl_renderbuffer::Format.
2009-12-10intel: Attempt to fix up after "Update vertex texture code."Eric Anholt
The MaxCombinedTextureImageUnits is the total number of samplers that can be bound between vertex, geometry, and fragment, not 0. This should report the correct value on 965 now. Other DRI drivers may also need updating if their MaxVertexTextureImageUnits != 0 (for example, if using the sw vertex pipeline). It's not clear to me if there's going to be a valid value for this limit other than MaxTextureImageUnits + MaxVertexTextureImageUnits (+ MaxGeometryTextureImageUnits eventually). If not, then we should probably just move this into the core at Get time. Bug #25518 (wine regression). Fixes piglit vp-combined-image-units.
2009-12-01mesa: Update vertex texture code after gallium changes.Michal Krol
2009-11-23Merge commit 'origin/mesa_7_7_branch'Maciej Cencora
2009-11-21i965: Fix several memory leaks on exit.Eric Anholt
Bug #25194.
2009-11-19intel: Remove non-GEM support.Eric Anholt
This really isn't supported at this point. GEM's been in the kernel for a year, and the fake bufmgr never really worked.
2009-11-19intel: Consistently use no_batch_wrap in intel_context struct.Eric Anholt
2009-11-19i965: Pack brw_wm_fragment_program better.Eric Anholt
2009-11-19mesa: Remove gratuitous padding in prog_dst_register.Eric Anholt
The padding was there to indicate the amount of space left from the number of expected bytes in the struct minus allocated bits. But uint bitfields get packed so that they don't cross uint boundaries, and we ended up allocating an extra dword to hold the pad field!
2009-11-19i965: Pack the brw_wm_prog_key better.Eric Anholt
2009-11-17Merge branch 'outputswritten64'Ian Romanick
Add a GLbitfield64 type and several macros to operate on 64-bit fields. The OutputsWritten field of gl_program is changed to use that type. This results in a fair amount of fallout in drivers that use programs. No changes are strictly necessary at this point as all bits used are below the 32-bit boundary. Fairly soon several bits will be added for clip distances written by a vertex shader. This will cause several bits used for varyings to be pushed above the 32-bit boundary. This will affect any drivers that support GLSL. At this point, only the i965 driver has been modified to support this eventuality. I did this as a "squash" merge. There were several places through the outputswritten64 branch where things were broken. I foresee this causing difficulties later for bisecting. The history is still available in the branch. Conflicts: src/mesa/drivers/dri/i965/brw_wm.h
2009-11-16i965: Use MESA_FORMAT_AL1616 when appropriateIan Romanick
2009-11-13i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
This should fix TXB on G45 and older in the GLSL case.
2009-11-13i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c.Eric Anholt
New comments should explain some of the confusion about how this message works.
2009-11-13i965: Clean up emit_tex a bit.Eric Anholt
2009-11-13Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt
2009-11-13i965: Flag BRW_NEW_CONTEXT on some context state.Eric Anholt
Fixing this is a prereq for avoiding flagging all state at new batch time. Eliminating that still causes problems, though (notably glean logicOp fails on my GM965).
2009-11-13i965: Remove an unused cache_item field.Eric Anholt
2009-11-13i965: Remove long dead structures for ffvertex_prog.c.Eric Anholt
2009-11-13i965: Use bo_map instead of subdata to upload the bits of constant buffer.Eric Anholt
Saves CPU time, resulting in a 2.5% FPS win on ETQW.
2009-11-13i965: Validate the number of URB entries selected for the VS.Eric Anholt
2009-11-13i965: Clean up Ironlake sampler type definitions.Eric Anholt
They're the same regardless of execution width for 8, 4x2, and 16.
2009-11-13i965: Avoid moving the current value back into the accumulator for MAD.Eric Anholt
This is a 2.9% (+/-.3%) performance win for my GL demo, which hits MAD sequences for matrix transforms.
2009-11-12i965: Fix Ironlake shadow comparisons.Eric Anholt
The cube map array index arg is always present.
2009-11-12i965: Fix VBO last-valid-offset setup on Ironlake.Eric Anholt
Instead of doing math based on the (broken for VBO && offset != 0) input->count number, just use the BO size. Fixes assertion failure in ETQW.
2009-11-11i965: fix EXT_provoking_vertex supportRoland Scheidegger
This didn't work for quad/quadstrips at all, and for all other primitive types it only worked when they were unclipped. Fix up the former in gs stage (could probably do without these changes and instead set QuadsFollowProvokingVertexConvention to false), and the rest in clip stage.
2009-11-10i965: Fix VS constant buffer value loading.Eric Anholt
Previously, we'd load linearly from ParameterValues[0] for the constants, though ParameterValues[1] may not equal ParameterValues[0] + 4. Additionally, the STATE_VAL type paramters didn't get updated. Fixes piglit vp-constant-array-huge.vpfp and ET:QW object locations. Bug #23226.
2009-11-10i965: Unalias src/dst registers for SGE and friends.Eric Anholt
Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/ Bug #22228 (cherry picked from commit 56ab92bad8f1d05bc22b8a8471d5aeb663f220de)
2009-11-10i965: Allow use of PROGRAM_LOCAL constants in ARB_vp.Eric Anholt
Fixes piglit arl.vp. (cherry picked from commit d52d78b4bcd6d4c0578f972c0b8ebac09e632196)
2009-11-10Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt
2009-11-10i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile.Eric Anholt
For an app that's blowing out the state cache, like sauerbraten, the memset of the giant arrays ended up taking 11% of the CPU even when only a "few" of the entries got used. With this, the WM program compile drops back down to 1% of CPU time. Bug #24981 (bisected to BRW_WM_MAX_INSN increase).
2009-11-10i965: Add a note explaining the data cache domain.Eric Anholt
2009-11-10i965: Unalias src/dst registers for SGE and friends.Eric Anholt
Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/ Bug #22228
2009-11-10i965: Allow use of PROGRAM_LOCAL constants in ARB_vp.Eric Anholt
Fixes piglit arl.vp.
2009-11-06i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt
No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size.
2009-11-06i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
2009-11-06i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
This should fix issues with antialiased lines in GLSL.
2009-11-06i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst.
2009-11-06i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt
2009-11-06i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt
2009-11-06i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt
This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
2009-11-06i965: Collect GLSL src/dst regs up in generic code.Eric Anholt
This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced.
2009-11-06i965: Always pass the size argument to brw_cache_data.Eric Anholt
This keeps the individual state files from having to export their structures for brw_state_cache initialization.