Age | Commit message (Collapse) | Author | |
---|---|---|---|
2010-01-19 | r600: align to r300 changes in the blit code | Maciej Cencora | |
Pitch here means aligned width, not aligned width * bpp. | |||
2010-01-19 | r300/r600: move some bo offsets checking to blit code | Maciej Cencora | |
In preperation for texcopy code sharing. | |||
2010-01-19 | r600: prepare for some code sharing | Maciej Cencora | |
2010-01-19 | r300: check if blitting for given format is supported earlier | Maciej Cencora | |
Prevents failing assertions at later stage. | |||
2010-01-19 | r300: use nearest texture filtering for accelerated blits | Maciej Cencora | |
2010-01-19 | r300: fix Y coord flipping in accelerated blits | Maciej Cencora | |
2010-01-19 | radeon: use mesa provided _mesa_tex_target_to_face function | Maciej Cencora | |
2010-01-19 | r300: prepare for texcopy code sharing | Maciej Cencora | |
2010-01-19 | radeon: add blit function to vtbl | Maciej Cencora | |
2010-01-19 | intel: Remove dead note_fence vtbl hook. | Eric Anholt | |
2010-01-19 | i965: Improve the hashing of brw_state_cache keys to include the cache_id. | Eric Anholt | |
No measurable difference on cairoperf. | |||
2010-01-19 | i965: Remove obsolete comment about the state atoms. | Eric Anholt | |
2010-01-19 | i965: Upload as many VS constants as possible through the push constants. | Eric Anholt | |
The pull constants require sending out to an overworked shared unit and waiting for a response, while push constants are nicely loaded in for us at thread dispatch time. By putting things we access in every VS invocation there, ETQW performance improved by 2.5% +/- 1.6% (n=6). | |||
2010-01-19 | i965: Allow for variable-sized auxdata in the state cache. | Eric Anholt | |
Everything has been constant-sized until now, but constant buffer handling changes will make us want some additional variable sized array. | |||
2010-01-19 | intel: Use the new DRI2 flush invalidate entrypoint to signal frame done. | Eric Anholt | |
Previously for frame throttling we would wait on the first batch after a swap before emitting another swap, because we had no hook after a swap was emitted. This meant that if an app managed to squeeze everything it for a frame had into one batch, it would lock-step with the GPU. With the swapbuffers changes, we now have the entrypoint we want. This takes the WoW intro screen from 25% GPU idle and visibly jerky to 4-5% GPU idle and rather smooth. Other apps such as OpenArena have run into this problem as well. | |||
2010-01-19 | r100/r200/r600: fix typo in 2b1d5ea4f0250a6a7fa312ced0a7af85e909381b | Alex Deucher | |
2010-01-19 | r100/r200/r600: check if blitting for given format is supported earlier | Alex Deucher | |
based on Maciej's r300 patch. | |||
2010-01-19 | r100/r200: add blit support for ARGB4444 | Alex Deucher | |
2010-01-18 | r60: Add relocs for CB_TILE/FRAG | Alex Deucher | |
as per 46dc6fd3ed5ef96cda53641a97bc68c3bc104a9f | |||
2010-01-18 | r100: add blit support | Alex Deucher | |
Only enabled with KMS. | |||
2010-01-18 | r200: add blit support | Alex Deucher | |
Only enabled with KMS. | |||
2010-01-18 | i965: Clean up constbuf handling by splitting reladdr/non-reladdr loads. | Eric Anholt | |
The codepaths in the function were almost entirely different. | |||
2010-01-18 | i965: Only set up the stack register if it's going to get used. | Eric Anholt | |
2010-01-18 | i965: Fix loads of non-relative-addr constants after a reladdr load. | Eric Anholt | |
Fixes piglit vp-arl-constant-array-huge-overwritten. | |||
2010-01-18 | r600: fix some warnings | Alex Deucher | |
2010-01-18 | r600: Update default state size to account for the new relocation | Jerome Glisse | |
the new relocation for CB_COLOR0_FRAG & CB_COLOR0_TILE add 4 dwords to the default command stream. Increase the prediction default size to take this into account | |||
2010-01-18 | r6xx/r7xx: emit relocation for FRAG & TILE buffer | Jerome Glisse | |
FRAG & TILE buffer are unused but still they need to be associated with a valid relocation so that userspace can't try to abuse them to overwritte GART and then try to write anywhere in system memory. | |||
2010-01-18 | r600: fix shadow_ambient shader | Andre Maasikas | |
rtype enums are different, DST_REG_OUTPUT got SRC_REG_CONSTANT in some shaders and produced invalid output/hang as TEX output is temp register always set out src to SRC_REG_TEMPORARY | |||
2010-01-17 | radeon_compiler: include main/compiler.h for compiler portability macros | Alan Coopersmith | |
Signed-off-by: Alan Coopersmith <alan.coopersmith@sun.com> Reviewed-by: Corbin Simpson <MostAwesomeDude@gmail.com> | |||
2010-01-16 | r600: remove stray END_BATCH in blit code | Alex Deucher | |
2010-01-15 | r600: improve blit support | Alex Deucher | |
- fill in more src/dst formats - disable depth copies for now - set proper data formats in render target regs - fill in additional default state The swizzles on some of the less used mesa formats are probably wrong. | |||
2010-01-15 | r600: add initial blit support | Andre Maasikas | |
2010-01-15 | r600: add r600_blit.c | Alex Deucher | |
Unfinished. | |||
2010-01-11 | Merge branch 'master' of ssh://people.freedesktop.org/~jbarnes/mesa | Jesse Barnes | |
Conflicts due to DRI1 removal: src/mesa/drivers/dri/intel/intel_context.c src/mesa/drivers/dri/intel/intel_screen.c | |||
2010-01-11 | radeon: fix prediction for r100 inline vert/elt emits. | Dave Airlie | |
On r100 we emit the indices inline so we need to account for that in the emission size. | |||
2010-01-11 | radeon: fix bug in realloc code. | Dave Airlie | |
This bug was fixed in libdrm ages ago, port to non-kms | |||
2010-01-09 | r300: minor accelerated blit fixes | Maciej Cencora | |
2010-01-09 | r300: fallback on depth buffer blits | Maciej Cencora | |
Depth buffer accelerated blits aren't implemented yet. | |||
2010-01-08 | intel/DRI2: add DRI2flushExtension support with invalidate hook | Kristian Høgsberg | |
Needed to support the SwapBuffers code properly. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> | |||
2010-01-08 | DRI2/GLX: add INTEL_swap_event support | Jesse Barnes | |
Add event support for the GLX swap buffers event, along with DRI2 protocol support for generating GLX swap buffers events in the direct rendered case. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> | |||
2010-01-08 | DRI2: add SwapBuffers support | Jesse Barnes | |
Support the new DRI2 protocol request, DRI2SwapBuffers, in both direct and indirect rendering context. This request allows the display server to optimize back->front swaps (e.g. through page flipping) and allows us to more easily support other GLX features like swap interval and the OML sync extension in DRI2. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> | |||
2010-01-08 | Merge branch 'mesa_7_7_branch' | Brian Paul | |
Conflicts: src/mesa/drivers/dri/i965/brw_wm_emit.c | |||
2010-01-08 | r300: Move initial declaration outside for loop. | Vinson Lee | |
2010-01-07 | intel: Remove leftover symlinks from DRI1 removal. | Eric Anholt | |
2010-01-07 | i810: use ColorMask[0] | Brian Paul | |
2010-01-06 | meta: remove F suffix from _mesa_Ortho() params | Brian Paul | |
_mesa_Ortho() takes GLdoubles. | |||
2010-01-06 | meta: move destination vertex/projection setup out of _mesa_meta_GenerateMipmap | Brian Paul | |
Based on a patch submitted by Pierre Willenbrock <pierre@pirsoft.de> | |||
2010-01-06 | meta: set viewport and projection matrix in _mesa_meta_GenerateMipmap | Brian Paul | |
This fixes mipmap levels being clipped to the last viewport. Based on a patch submitted by Pierre Willenbrock <pierre@pirsoft.de> | |||
2010-01-06 | r600: adjust after radeon mipmap changes in 7118db8700 | Andre Maasikas | |
R600_OUT_BATCH_RELOC doesn't really use offset so set it in TEX_RESOURCE2 + typo fix | |||
2010-01-06 | r300/compiler: add full viewport transformation support in WPOS codegen | Marek Olšák | |