| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-08-12 | i965: Handle scalar result swizzling in shared GLSL/non-GLSL code. | Eric Anholt | |
| This is preparation for merging of brw_wm_glsl.c and brw_wm_emit.c, and glsl.c doesn't swizzle channel results around. | |||
| 2009-08-12 | i965: Flag ARL-using programs as requiring brw_wm_glsl.c | Eric Anholt | |
| This doesn't fix the glean testcase, but I guess it provides hope. | |||
| 2009-08-12 | i965: Remove some unused WM opcode args. | Eric Anholt | |
| 2009-08-12 | i965: Avoid re-uploading the index buffer when we don't need to. | Eric Anholt | |
| No performance difference proven at 95% confidence with my GLSL demo (n=10). | |||
| 2009-08-12 | r600: fix warning | Alex Deucher | |
| 2009-08-12 | r600: state cleanups | Alex Deucher | |
| 2009-08-12 | r600: clean up Create/DestroyContext | Alex Deucher | |
| 2009-08-12 | r200: Prevent TexGenMatrix from leaking when destroying r200 context. | Pauli Nieminen | |
| Signed-off-by: Pauli Nieminen <suokkos@gmail.com> | |||
| 2009-08-12 | vbo: Avoid extra validation of DrawElements. | Eric Anholt | |
| This saves mapping the index buffer to get a bounds on the indices that drivers just drop on the floor in the VBO case (cache win), saves a bonus walk of the indices in the CheckArrayBounds case, and other miscellaneous validation. On intel it's a particularly a large win (50-100% in my app) because even though we let the indices stay in both CPU and GPU caches, we still end up waiting for the GPU to be done with the buffer before reading from it. Drivers that want the min/max_index fields must now check index_bounds_valid and use vbo_get_minmax_index before using them. | |||
| 2009-08-12 | radeon: Minor warnings cleanup. | Eric Anholt | |
| 2009-08-12 | i965: Use _MaxElement instead of index-calculated min/max for VBO bounds. | Eric Anholt | |
| 2009-08-12 | radeon: Add protection against recursive DRM locking. | Pauli Nieminen | |
| Reference counting protects DRM lock call from recursive locking that would cause hang. Code also adds optional debugging output for recursive call that is compiled only if NDEBUG is not defined. This code is not 100% thread safe because mesa doesn't include increment and test atomic operation. There is built-in gcc functions but they are only available from gcc 4.2. | |||
| 2009-08-12 | r600: A shader is bound that exports Z as a float into Red channel | Cooper Yuan | |
| 2009-08-11 | mesa: handle glDrawPixels images which are larger than max rect texture size | Brian Paul | |
| 2009-08-11 | mesa: added _mesa_meta_draw_pixels() | Brian Paul | |
| 2009-08-11 | mesa: added META_FOG and optimize some meta_begin/end() code | Brian Paul | |
| 2009-08-11 | r600: use the drm ioctls for swap and texture upload | Alex Deucher | |
| NOTE: THIS REQUIRES AN UPDATED DRM! | |||
| 2009-08-11 | mesa/glapi: regenerated files from gl_API.xml | Brian Paul | |
| 2009-08-11 | r600: update num of interp if posizition is used | Cooper Yuan | |
| 2009-08-10 | intel: use new _mesa_meta_copy_pixels() function | Brian Paul | |
| glCopyPixels() no longer hits a software fallback when zooming, blending, etc. | |||
| 2009-08-10 | mesa: save/restore texture matrix in meta code | Brian Paul | |
| Also, save/restore viewport and texture state in _mesa_meta_copy_pixels() | |||
| 2009-08-10 | mesa: for meta blit, check max texture size, use glCopyTexSubImage2D() when ↵ | Brian Paul | |
| possible | |||
| 2009-08-10 | mesa: initial meta implementation of glCopyPixels() | Brian Paul | |
| 2009-08-10 | mesa: remove debug flush call | Brian Paul | |
| 2009-08-10 | intel: add missing \n to fprintf() | Brian Paul | |
| 2009-08-10 | intel: use new _mesa_meta_blit_framebuffer() function | Brian Paul | |
| The previous version of framebuffer blit was a quick hack. The new meta version works pretty well. | |||
| 2009-08-10 | mesa: new driver meta-ops module | Brian Paul | |
| Implement glClear() in terms of quad rendering, implement glBlitFramebuffer() in terms of glCopyTexImage2D + textured quad, etc. There have been several places in the drivers where we've implemented meta rendering similar to this. This is an effort to do it in a more portable and more efficient form. The _mesa_meta_begin/end() functions act like glPush/PopAttrib() but are lighter-weight. Plus, _mesa_meta_begin() resets GL state back to default values (texturing off, identity vertex transform, etc) so the meta drawing functions don't have to worry about it. For now only _mesa_mesa_blit_framebuffer() and _mesa_meta_clear() are implemented. glDrawPixels() and glCopyPixels() would be the next candidates. | |||
| 2009-08-10 | radeon_fbo: switch short to byte for 565 | Dave Airlie | |
| 2009-08-10 | radeon: fix cut-n-paste in alphabits in fbo code | Dave Airlie | |
| 2009-08-09 | r600: looks like a typo | Dave Airlie | |
| 2009-08-09 | r600: load per-pixel position into PS in order to use fragment.position. | Cooper Yuan | |
| This patch can fix /progs/fp/tri-depth, tri-depth2, tri-depthwrite, tri-depthwrite2 and point-position. | |||
| 2009-08-07 | Revert "i965: Disable texture tiling by default." | Eric Anholt | |
| This reverts commit b8e638d4895d2d342306bb6443a455f73903ce20. Now that the known hangs and misrendering issues are fixed, I'm ready to start encouraging it by default again. | |||
| 2009-08-07 | intel: Align region height as required for tiled regions. | Eric Anholt | |
| Otherwise, we would address beyond the end of our buffers. Fixes reliable GPU segfault with texture_tiling=true and oglconform shadow.c. Bug #22406. | |||
| 2009-08-07 | i965: Add a note justifying domain choice for the SF VP. | Eric Anholt | |
| 2009-08-07 | intel: Add some more safety asserts in the blit code. | Eric Anholt | |
| 2009-08-07 | i965: Replace the subroutine-skipping jump in VS with a NOP if it's a NOP. | Eric Anholt | |
| This showed a 1.9% (+/-.3%, n=3) improvement in OA performance with high geometry settings. | |||
| 2009-08-07 | radeon: correct fix for tiling with the legacy build | Alex Deucher | |
| 2009-08-07 | intel: Fix googleearth by avoiding GL_VIEWPORT_BIT in meta clear push/pop | Eric Anholt | |
| I have no idea why this fixes things, but being more efficient sounds good anyway. Fixes regression in 99d07d0f91ddd37926d08f4e7f10d55cac28d9a7 where most of the lit half of the world was not drawn. | |||
| 2009-08-07 | radeon: fix the build with older drm headers | Alex Deucher | |
| 2009-08-07 | dri: Fix problems with unitialized values in dri screen object. | Pauli Nieminen | |
| This fixes crash in r200 KMS driver when pSAREA was set to 1 randomly because of memory wasn't cleared. Signed-off-by: Pauli Nieminen <suokkos@gmail.com> | |||
| 2009-08-07 | i965: minor context comments | Brian Paul | |
| 2009-08-07 | intel: minor context comments | Brian Paul | |
| 2009-08-07 | intel: move blit call out of assert() | Brian Paul | |
| 2009-08-07 | intel: fix typo: s/softare/software/ | Brian Paul | |
| 2009-08-07 | radeon: enable tiling fallbacks in 3D driver. | Dave Airlie | |
| Only really got good testing on r500 so far, need to enable in DDX and play some more. | |||
| 2009-08-07 | radeon span: add r200 depth/stencil span read/writing | Dave Airlie | |
| this should only really affect DRI2 since we mostly have a surface in DRI1. I don't think this is perfect yet, but it is a better start than nothing. | |||
| 2009-08-07 | r200: fix scissor emission for r200 under kms | Dave Airlie | |
| 2009-08-06 | mesa: Ignores | Jakob Bornecrantz | |
| Got tired of seeing these files in git status all the time | |||
| 2009-08-05 | i965: Fix source depth reg setting for FSes reading and writing to depth. | Eric Anholt | |
| For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603. | |||
| 2009-08-05 | Merge branch 'mesa_7_5_branch' | Brian Paul | |
| Conflicts: src/mesa/main/state.c | |||
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index : Mesa | |
| My Mesa repository | Thomas White |
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