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Conflicts:
src/mesa/drivers/dri/radeon/radeon_fbo.c
src/mesa/drivers/dri/s3v/s3v_tex.c
src/mesa/drivers/dri/s3v/s3v_xmesa.c
src/mesa/drivers/dri/trident/trident_context.c
src/mesa/main/debug.c
src/mesa/main/mipmap.c
src/mesa/main/texformat.c
src/mesa/main/texgetimage.c
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Based on initial patch from Stephan Schmid <stephan_2303@gmx.de>.
Basic idea is to dump the zpass count at the start and end of the query
and subtract to get the total number of visible fragments. HW writes
alternating qwords for up to 4 DBs. On the first pass, we start at
buffer address + 0; on the second pass, we start at buffer address + 8
(bytes). The resulting buffer at the end of the query looks like:
qw[0]: db0 start
qw[1]: db0 end
...
qw[6]: db3 start
qw[7]: db3 end
The MSB of each qword is the valid bit and the lower 63 bits are
the zpass count for that DB.
OQ on RV740 is disabled at the moment as it only seems to report
results for half of its DBs. This needs further investigation.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Brian Paul <brianp@vmware.com>
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Conflicts:
src/mesa/shader/lex.yy.c
src/mesa/shader/program_lexer.l
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Signed-off-by: Brian Paul <brianp@vmware.com>
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Bug #24435
(cherry picked from commit d56125a298106d81e10674f1c4b3b43b51a5139d)
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This fixes the second part of bug 23552.
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Use src->draw_offset intead of zero. Zero usually worked, except when
the src renderbuffer is actually a texture mipmap level higher than zero.
Fixes progs/test/blitfb.c test.
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Bug #24734.
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This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c.
It turns out the i965 driver uses the intel->Fallback field as a boolean,
not as a bitmask. The intelFallback() function is a no-op in the i965
driver. It would have been nice if there were some comments about this.
I'll fix that next...
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Need to push texture state and polygon state too.
Fixes rendering glitches seen in progs/demos/engine when changing
the rendering mode (wireframe, texture modes).
This makes bitmap rendering a little slower, unfortunately.
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Use src->draw_offset intead of zero. Zero usually worked, except when
the src renderbuffer is actually a texture mipmap level higher than zero.
Fixes progs/test/blitfb.c test.
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Bug #24734.
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This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c.
It turns out the i965 driver uses the intel->Fallback field as a boolean,
not as a bitmask. The intelFallback() function is a no-op in the i965
driver. It would have been nice if there were some comments about this.
I'll fix that next...
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Need to push texture state and polygon state too.
Fixes rendering glitches seen in progs/demos/engine when changing
the rendering mode (wireframe, texture modes).
This makes bitmap rendering a little slower, unfortunately.
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Call the ctx->Driver.ChooseTextureFormat() function from core Mesa's
_mesa_[Copy]TexImage functions instead of in the driver functions.
One less thing for drivers to do.
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And fix incorrect first parameter.
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Use _mesa_format_image_size() instead.
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It always just called _mesa_compressed_texture_size() anyway.
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Replace calls to ctx->Driver.CompressedTextureSize with calls to
_mesa_format_image_size. The former always called the later.
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Conflicts:
src/mesa/drivers/dri/intel/intel_fbo.c
src/mesa/drivers/dri/intel/intel_mipmap_tree.c
src/mesa/drivers/dri/intel/intel_mipmap_tree.h
src/mesa/drivers/dri/intel/intel_tex_copy.c
src/mesa/drivers/dri/intel/intel_tex_image.c
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By just using offsets, we confused the hardware's tiling calculations,
resulting in failures in miptree validation and blit clears.
Fixes piglit fbo-clearmipmap.
Bug #23552. (automatic mipmap generation)
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Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
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This enables the remap table in core. driInitExtensions is adapted to
use the remap table. All uses of extension_helper.h are replaced by
remap_helper.h. The chicken-egg problem of the DRI drivers is also
solved.
It is now also possible to pass NULL extensions to driInitExtensions.
It will cause driInitExtensions to map all known functions. This
functionality is used by software drivers and EGL_i915.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
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Stride is set already in r700SetVertexFormat and there it works
correctly for 0 also
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at this point
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Make it more consistent with other radeon drivers.
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Now pass a specific MESA_FORMAT_x token to indicate the renderbuffer's
format. This is better than passing a GLenum and having to guess the
specific format.
I'm unable to test all the drivers, but any issues should be easy to fix.
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Per the GLX spec, when changing rendering contexts, the old context
should first be flushed.
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Setting intel->Fallback = 1 clobbered any fallback state that was already
set. Not sure where this hack originated (the git history is a little
convoluted). Define and use a new BRW_FALLBACK_DRAW bit instead. This
shouldn't break anything and could potentially fix some bugs (but no
specific ones are known).
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