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authorTony Lindgren <tony@atomide.com>2009-11-11 15:21:24 -0800
committerTony Lindgren <tony@atomide.com>2009-11-11 15:21:24 -0800
commit8171d88089ad63fc442b2bf32af7c18653adc5cb (patch)
treedfde2fd974b8d15d1a1a5a2c13d57d5fe9dd8e76
parent4d0226042c05588be47b06bc1dbe7a09c9c540a4 (diff)
parentcf22854cee10e16e28b1dde136c37e82b7d503ee (diff)
Merge branch 'pm-upstream/pm-cpuidle' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into 7xx-iosplit-plat-merge
-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c318
-rw-r--r--arch/arm/mach-omap2/pm.h4
-rw-r--r--arch/arm/mach-omap2/pm34xx.c55
4 files changed, 329 insertions, 50 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8cb16777661..1d54ad349bf 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -31,7 +31,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o
-obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
+obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
endif
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
new file mode 100644
index 00000000000..a26d6a08ae3
--- /dev/null
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -0,0 +1,318 @@
+/*
+ * linux/arch/arm/mach-omap2/cpuidle34xx.c
+ *
+ * OMAP3 CPU IDLE Routines
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Karthik Dasu <karthik-dp@ti.com>
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * Based on pm.c for omap2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/sched.h>
+#include <linux/cpuidle.h>
+
+#include <plat/prcm.h>
+#include <plat/irqs.h>
+#include <plat/powerdomain.h>
+#include <plat/clockdomain.h>
+#include <plat/control.h>
+#include <plat/serial.h>
+
+#include "pm.h"
+
+#ifdef CONFIG_CPU_IDLE
+
+#define OMAP3_MAX_STATES 7
+#define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
+#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
+#define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
+#define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
+#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
+#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
+#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
+
+struct omap3_processor_cx {
+ u8 valid;
+ u8 type;
+ u32 sleep_latency;
+ u32 wakeup_latency;
+ u32 mpu_state;
+ u32 core_state;
+ u32 threshold;
+ u32 flags;
+};
+
+struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
+struct omap3_processor_cx current_cx_state;
+struct powerdomain *mpu_pd, *core_pd;
+
+static int omap3_idle_bm_check(void)
+{
+ if (!omap3_can_sleep())
+ return 1;
+ return 0;
+}
+
+static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
+ struct clockdomain *clkdm)
+{
+ omap2_clkdm_allow_idle(clkdm);
+ return 0;
+}
+
+static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
+ struct clockdomain *clkdm)
+{
+ omap2_clkdm_deny_idle(clkdm);
+ return 0;
+}
+
+/**
+ * omap3_enter_idle - Programs OMAP3 to enter the specified state
+ * @dev: cpuidle device
+ * @state: The target state to be programmed
+ *
+ * Called from the CPUidle framework to program the device to the
+ * specified target state selected by the governor.
+ */
+static int omap3_enter_idle(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
+ struct timespec ts_preidle, ts_postidle, ts_idle;
+ u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
+
+ current_cx_state = *cx;
+
+ /* Used to keep track of the total time in idle */
+ getnstimeofday(&ts_preidle);
+
+ local_irq_disable();
+ local_fiq_disable();
+
+ if (!enable_off_mode) {
+ if (mpu_state < PWRDM_POWER_RET)
+ mpu_state = PWRDM_POWER_RET;
+ if (core_state < PWRDM_POWER_RET)
+ core_state = PWRDM_POWER_RET;
+ }
+
+ pwrdm_set_next_pwrst(mpu_pd, mpu_state);
+ pwrdm_set_next_pwrst(core_pd, core_state);
+
+ if (omap_irq_pending() || need_resched())
+ goto return_sleep_time;
+
+ if (cx->type == OMAP3_STATE_C1) {
+ pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
+ pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
+ }
+
+ /* Execute ARM wfi */
+ omap_sram_idle();
+
+ if (cx->type == OMAP3_STATE_C1) {
+ pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
+ pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
+ }
+
+return_sleep_time:
+ getnstimeofday(&ts_postidle);
+ ts_idle = timespec_sub(ts_postidle, ts_preidle);
+
+ local_irq_enable();
+ local_fiq_enable();
+
+ return (u32)timespec_to_ns(&ts_idle)/1000;
+}
+
+/**
+ * omap3_enter_idle_bm - Checks for any bus activity
+ * @dev: cpuidle device
+ * @state: The target state to be programmed
+ *
+ * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
+ * function checks for any pending activity and then programs the
+ * device to the specified or a safer state.
+ */
+static int omap3_enter_idle_bm(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ struct cpuidle_state *new_state = state;
+
+ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
+ BUG_ON(!dev->safe_state);
+ new_state = dev->safe_state;
+ }
+
+ dev->last_state = new_state;
+ return omap3_enter_idle(dev, new_state);
+}
+
+DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
+
+/* omap3_init_power_states - Initialises the OMAP3 specific C states.
+ *
+ * Below is the desciption of each C state.
+ * C1 . MPU WFI + Core active
+ * C2 . MPU WFI + Core inactive
+ * C3 . MPU CSWR + Core inactive
+ * C4 . MPU OFF + Core inactive
+ * C5 . MPU CSWR + Core CSWR
+ * C6 . MPU OFF + Core CSWR
+ * C7 . MPU OFF + Core OFF
+ */
+void omap_init_power_states(void)
+{
+ /* C1 . MPU WFI + Core active */
+ omap3_power_states[OMAP3_STATE_C1].valid = 1;
+ omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
+ omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2;
+ omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2;
+ omap3_power_states[OMAP3_STATE_C1].threshold = 5;
+ omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
+ omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
+ omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
+
+ /* C2 . MPU WFI + Core inactive */
+ omap3_power_states[OMAP3_STATE_C2].valid = 1;
+ omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
+ omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10;
+ omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10;
+ omap3_power_states[OMAP3_STATE_C2].threshold = 30;
+ omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
+ omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
+ omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
+
+ /* C3 . MPU CSWR + Core inactive */
+ omap3_power_states[OMAP3_STATE_C3].valid = 1;
+ omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
+ omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50;
+ omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50;
+ omap3_power_states[OMAP3_STATE_C3].threshold = 300;
+ omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
+ omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
+ omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_CHECK_BM;
+
+ /* C4 . MPU OFF + Core inactive */
+ omap3_power_states[OMAP3_STATE_C4].valid = 1;
+ omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
+ omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500;
+ omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800;
+ omap3_power_states[OMAP3_STATE_C4].threshold = 4000;
+ omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
+ omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
+ omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_CHECK_BM;
+
+ /* C5 . MPU CSWR + Core CSWR*/
+ omap3_power_states[OMAP3_STATE_C5].valid = 1;
+ omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
+ omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500;
+ omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500;
+ omap3_power_states[OMAP3_STATE_C5].threshold = 12000;
+ omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
+ omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
+ omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_CHECK_BM;
+
+ /* C6 . MPU OFF + Core CSWR */
+ omap3_power_states[OMAP3_STATE_C6].valid = 1;
+ omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
+ omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000;
+ omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500;
+ omap3_power_states[OMAP3_STATE_C6].threshold = 15000;
+ omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
+ omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
+ omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_CHECK_BM;
+
+ /* C7 . MPU OFF + Core OFF */
+ omap3_power_states[OMAP3_STATE_C7].valid = 1;
+ omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
+ omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000;
+ omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000;
+ omap3_power_states[OMAP3_STATE_C7].threshold = 300000;
+ omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
+ omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
+ omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_CHECK_BM;
+}
+
+struct cpuidle_driver omap3_idle_driver = {
+ .name = "omap3_idle",
+ .owner = THIS_MODULE,
+};
+
+/**
+ * omap3_idle_init - Init routine for OMAP3 idle
+ *
+ * Registers the OMAP3 specific cpuidle driver with the cpuidle
+ * framework with the valid set of states.
+ */
+int __init omap3_idle_init(void)
+{
+ int i, count = 0;
+ struct omap3_processor_cx *cx;
+ struct cpuidle_state *state;
+ struct cpuidle_device *dev;
+
+ mpu_pd = pwrdm_lookup("mpu_pwrdm");
+ core_pd = pwrdm_lookup("core_pwrdm");
+
+ omap_init_power_states();
+ cpuidle_register_driver(&omap3_idle_driver);
+
+ dev = &per_cpu(omap3_idle_dev, smp_processor_id());
+
+ for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
+ cx = &omap3_power_states[i];
+ state = &dev->states[count];
+
+ if (!cx->valid)
+ continue;
+ cpuidle_set_statedata(state, cx);
+ state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
+ state->target_residency = cx->threshold;
+ state->flags = cx->flags;
+ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
+ omap3_enter_idle_bm : omap3_enter_idle;
+ if (cx->type == OMAP3_STATE_C1)
+ dev->safe_state = state;
+ sprintf(state->name, "C%d", count+1);
+ count++;
+ }
+
+ if (!count)
+ return -EINVAL;
+ dev->state_count = count;
+
+ if (cpuidle_register_device(dev)) {
+ printk(KERN_ERR "%s: CPUidle register device failed\n",
+ __func__);
+ return -EIO;
+ }
+
+ return 0;
+}
+#else
+int __init omap3_idle_init(void)
+{
+ return 0;
+}
+#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 7eb769f4ef3..0bf345db714 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -18,6 +18,10 @@ extern u32 sleep_while_idle;
extern void *omap3_secure_ram_storage;
extern void omap3_pm_off_mode_enable(int);
+extern void omap_sram_idle(void);
+extern int omap3_can_sleep(void);
+extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
+extern int omap3_idle_init(void);
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 01b95eaae75..81ed252a0f8 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -76,8 +76,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm;
static struct powerdomain *cam_pwrdm;
-static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
-
static inline void omap3_per_save_context(void)
{
omap_gpio_save_context();
@@ -318,7 +316,7 @@ static void restore_table_entry(void)
restore_control_register(control_reg_value);
}
-static void omap_sram_idle(void)
+void omap_sram_idle(void)
{
/* Variable to tell what needs to be saved and restored
* in omap_sram_idle*/
@@ -361,7 +359,7 @@ static void omap_sram_idle(void)
/* NEON control */
if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
- set_pwrdm_state(neon_pwrdm, mpu_next_state);
+ pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
/* PER */
per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
@@ -463,61 +461,19 @@ static void omap_sram_idle(void)
omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
}
-/*
- * Check if functional clocks are enabled before entering
- * sleep. This function could be behind CONFIG_PM_DEBUG
- * when all drivers are configuring their sysconfig registers
- * properly and using their clocks properly.
- */
-static int omap3_fclks_active(void)
-{
- u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
- fck_cam = 0, fck_per = 0, fck_usbhost = 0;
-
- fck_core1 = cm_read_mod_reg(CORE_MOD,
- CM_FCLKEN1);
- if (omap_rev() > OMAP3430_REV_ES1_0) {
- fck_core3 = cm_read_mod_reg(CORE_MOD,
- OMAP3430ES2_CM_FCLKEN3);
- fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
- CM_FCLKEN);
- fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
- CM_FCLKEN);
- } else
- fck_sgx = cm_read_mod_reg(GFX_MOD,
- OMAP3430ES2_CM_FCLKEN3);
- fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
- CM_FCLKEN);
- fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
- CM_FCLKEN);
- fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
- CM_FCLKEN);
-
- /* Ignore UART clocks. These are handled by UART core (serial.c) */
- fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
- fck_per &= ~OMAP3430_EN_UART3;
-
- if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
- fck_cam | fck_per | fck_usbhost)
- return 1;
- return 0;
-}
-
-static int omap3_can_sleep(void)
+int omap3_can_sleep(void)
{
if (!sleep_while_idle)
return 0;
if (!omap_uart_can_sleep())
return 0;
- if (omap3_fclks_active())
- return 0;
return 1;
}
/* This sets pwrdm state (other than mpu & core. Currently only ON &
* RET are supported. Function is assuming that clkdm doesn't have
* hw_sup mode enabled. */
-static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
{
u32 cur_state;
int sleep_switch = 0;
@@ -567,7 +523,7 @@ static void omap3_pm_idle(void)
if (!omap3_can_sleep())
goto out;
- if (omap_irq_pending())
+ if (omap_irq_pending() || need_resched())
goto out;
omap_sram_idle();
@@ -1102,6 +1058,7 @@ static int __init omap3_pm_init(void)
#endif /* CONFIG_SUSPEND */
pm_idle = omap3_pm_idle;
+ omap3_idle_init();
pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
/*