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authorMike Frysinger <michael.frysinger@analog.com>2007-10-30 12:03:47 +0800
committerBryan Wu <bryan.wu@analog.com>2007-10-30 12:03:47 +0800
commit41241c17eb11df08efa81727f9c01225cd0f56b3 (patch)
tree34dc780b020176c0524820e745a8373b0adf41d0
parent36208059c18cd5e8c89fc9037cb1a79e62733882 (diff)
Blackfin arch: Add missing definitions for BF561
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index bf7dc4e0006..7945e8a3a84 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -55,6 +55,9 @@
/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
#define SWRST SICA_SWRST
#define SYSCR SICA_SYSCR
+#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
+#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
+#define RESET_SOFTWARE (SWRST_OCCURRED)
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define SICA_SWRST 0xFFC00100 /* Software Reset register */