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authorArnd Bergmann <abergman@de.ibm.com>2006-03-23 00:00:07 +0100
committerPaul Mackerras <paulus@samba.org>2006-03-27 14:48:20 +1100
commit5536408c21cdde38bfdbb59a6fd4fcbf1232699f (patch)
tree70ef920f6bc97383d1363926f19499167d0d2249
parentd0e57c68373f8ded8c50245fd082e606f9f63221 (diff)
[PATCH] powerpc: work around a cell interrupt HW bug
Apparently we have found a bug in the CPU that causes external interrupts to sometimes get disabled indefinitely. This adds a workaround for the problem. Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--arch/powerpc/platforms/cell/interrupt.c19
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c
index 9d41e07b0c9..e3fffdfcc67 100644
--- a/arch/powerpc/platforms/cell/interrupt.c
+++ b/arch/powerpc/platforms/cell/interrupt.c
@@ -63,7 +63,24 @@ static DEFINE_PER_CPU(struct iic, iic);
void iic_local_enable(void)
{
- out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
+ struct iic *iic = &__get_cpu_var(iic);
+ u64 tmp;
+
+ /*
+ * There seems to be a bug that is present in DD2.x CPUs
+ * and still only partially fixed in DD3.1.
+ * This bug causes a value written to the priority register
+ * not to make it there, resulting in a system hang unless we
+ * write it again.
+ * Masking with 0xf0 is done because the Cell BE does not
+ * implement the lower four bits of the interrupt priority,
+ * they always read back as zeroes, although future CPUs
+ * might implement different bits.
+ */
+ do {
+ out_be64(&iic->regs->prio, 0xff);
+ tmp = in_be64(&iic->regs->prio);
+ } while ((tmp & 0xf0) != 0xf0);
}
void iic_local_disable(void)