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authorDavid Howells <dhowells@redhat.com>2006-03-31 16:00:29 +0100
committerLinus Torvalds <torvalds@g5.osdl.org>2006-03-31 12:27:01 -0800
commit108b42b4b966462444265806e3d7260a632ad630 (patch)
tree8565bb700a0a4bb6456f1955a9c2ec69e4df8927 /Documentation/cachetlb.txt
parent428622986858aebddc32d022af65e88b9d2ea8bb (diff)
[PATCH] Document Linux's memory barriers [try #7]
The attached patch documents the Linux kernel's memory barriers. I've updated it from the comments I've been given. The per-arch notes sections are gone because it's clear that there are so many exceptions, that it's not worth having them. I've added a list of references to other documents. I've tried to get rid of the concept of memory accesses appearing on the bus; what matters is apparent behaviour with respect to other observers in the system. Interrupts barrier effects are now considered to be non-existent. They may be there, but you may not rely on them. I've added a couple of definition sections at the top of the document: one to specify the minimum execution model that may be assumed, the other to specify what this document refers to by the term "memory". I've made greater mention of the use of mmiowb(). I've adjusted the way in which caches are described, and described the fun that can be had with cache coherence maintenance being unordered and data dependency not being necessarily implicit. I've described (smp_)read_barrier_depends(). I've rearranged the order of the sections, so that memory barriers are discussed in abstract first, and then described the memory barrier facilities available on Linux, before going on to more real-world discussions and examples. I've added information about the lack of memory barriering effects with atomic ops and bitops. I've added information about control dependencies. I've added more diagrams to illustrate caching interactions between CPUs. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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