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| author | Simon Arlott <simon@arlott.org> | 2007-05-02 19:27:05 +0200 |
|---|---|---|
| committer | Andi Kleen <andi@basil.nowhere.org> | 2007-05-02 19:27:05 +0200 |
| commit | 0949be35095b53dbaa72db700cb5074c5c249629 (patch) | |
| tree | 4dcca21a4e726dae5dd7afcaaebff2a5dd154031 /Documentation/memory-barriers.txt | |
| parent | f5e8861583a591020176c90c10c6a130fed4f3ec (diff) | |
[PATCH] i386: Add an option for the VIA C7 which sets appropriate L1 cache
The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has
a cache line length of 64 according to
http://www.digit-life.com/articles2/cpu/rmma-via-c7.html. This patch sets
gcc to -march=686 and select s the correct cache shift.
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Andi Kleen <ak@suse.de>
Cc: Andi Kleen <ak@suse.de>
Cc: Dave Jones <davej@codemonkey.org.uk>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Diffstat (limited to 'Documentation/memory-barriers.txt')
0 files changed, 0 insertions, 0 deletions