diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 14:32:24 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 14:32:24 -0700 |
| commit | a348a7e6fdbcd2d5192a09719a479bb238fde727 (patch) | |
| tree | 5ff94185f4e5a810777469d7fe7832a8ec2d3430 /arch/arm/mach-davinci/include/mach/nand.h | |
| parent | 808347f6a31792079e345ec865e9cfcb6e8ae6b2 (diff) | |
| parent | 28d0325ce6e0a52f53d8af687e6427fee59004d3 (diff) | |
Merge commit 'v2.6.31-rc1' into dmaengine
Diffstat (limited to 'arch/arm/mach-davinci/include/mach/nand.h')
| -rw-r--r-- | arch/arm/mach-davinci/include/mach/nand.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index aa482841270..b520c4b5678 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h @@ -68,10 +68,14 @@ struct davinci_nand_pdata { /* platform_data */ /* none == NAND_ECC_NONE (strongly *not* advised!!) * soft == NAND_ECC_SOFT - * 1-bit == NAND_ECC_HW - * 4-bit == NAND_ECC_HW_SYNDROME (not on all chips) + * else == NAND_ECC_HW, according to ecc_bits + * + * All DaVinci-family chips support 1-bit hardware ECC. + * Newer ones also support 4-bit ECC, but are awkward + * using it with large page chips. */ nand_ecc_modes_t ecc_mode; + u8 ecc_bits; /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ unsigned options; |