diff options
| author | Eric Miao <eric.miao@marvell.com> | 2009-01-20 11:04:16 +0800 |
|---|---|---|
| committer | Eric Miao <eric.miao@marvell.com> | 2009-03-09 21:22:40 +0800 |
| commit | 5bf3df3f00f507119a26ba0780aa8799e741615c (patch) | |
| tree | 3abb57be183566f7da8b8f718c6fdbbdcf9f993d /arch/arm/mach-pxa/include/mach/regs-ost.h | |
| parent | b74d1969083a8869659ad2b23138fc8a5ca97c53 (diff) | |
[ARM] pxa: separate definitions from pxa-regs.h and remove it finally
The remaining registers are separated into:
- <mach/regs-ost.h>
- <mach/regs-rtc.h>
- <mach/regs-intc.h>
and then we can remove pxa-regs.h completely. Instead of #include this
file, let's:
1. include the specific <mach/regs-*.h> with care (if that's absolutely
necessary)
2. define the registers in the driver, make cleanly defined API to expose
the register access to external with sufficient reason
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Diffstat (limited to 'arch/arm/mach-pxa/include/mach/regs-ost.h')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/regs-ost.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h new file mode 100644 index 00000000000..a3e5f86ef67 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ost.h @@ -0,0 +1,34 @@ +#ifndef __ASM_MACH_REGS_OST_H +#define __ASM_MACH_REGS_OST_H + +#include <mach/hardware.h> + +/* + * OS Timer & Match Registers + */ + +#define OSMR0 __REG(0x40A00000) /* */ +#define OSMR1 __REG(0x40A00004) /* */ +#define OSMR2 __REG(0x40A00008) /* */ +#define OSMR3 __REG(0x40A0000C) /* */ +#define OSMR4 __REG(0x40A00080) /* */ +#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ +#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ +#define OMCR4 __REG(0x40A000C0) /* */ +#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ +#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ +#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ + +#define OSSR_M3 (1 << 3) /* Match status channel 3 */ +#define OSSR_M2 (1 << 2) /* Match status channel 2 */ +#define OSSR_M1 (1 << 1) /* Match status channel 1 */ +#define OSSR_M0 (1 << 0) /* Match status channel 0 */ + +#define OWER_WME (1 << 0) /* Watchdog Match Enable */ + +#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ +#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ +#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ +#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ + +#endif /* __ASM_MACH_REGS_OST_H */ |