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authorBen Dooks <ben-linux@org.rmk.(none)>2005-05-12 19:27:13 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-05-12 19:27:13 +0100
commit4ad3a443c9238c8df68f4519049c3c8d80fe62c2 (patch)
treeeb39723468aa2b9269cfb3440239315940ff69c8 /arch/arm/mach-s3c2410/clock.c
parent9dabf9da18018b99a51334c2ef168019389ed5bf (diff)
[PATCH] ARM: 2677/1: S3C2440 - UPLL frequency doubled
Patch from Ben Dooks S3C2440 UPLL is the same as the S3C2410 UPLL, it is only the MPLL which has an extra multiplication factor of 2 in the multiplier. Signed-off-by: Ben Dooks Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410/clock.c')
-rw-r--r--arch/arm/mach-s3c2410/clock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index e23f534d4e1..8d986b8401c 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -478,7 +478,7 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
{
unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
- s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate) * 2;
+ s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate);
printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n",
print_mhz(s3c2440_clk_upll.rate));