diff options
| author | Ben Dooks <ben-linux@fluff.org> | 2008-08-08 21:10:12 +0100 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2008-08-08 21:10:12 +0100 |
| commit | af7a535688a758d15f06a98833e6a143b29af9de (patch) | |
| tree | bac5ab210bbbbe276f0e44ed84194d7c8bb16aae /arch/arm/mach-s3c2410/include/mach/regs-power.h | |
| parent | 0c17e4ceedd35c78b1c7413dbd16279a350be6bc (diff) | |
| parent | c41107c2d4fd31924533f4dbc4c3428acc2b5894 (diff) | |
Merge http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm into for-rmk
Diffstat (limited to 'arch/arm/mach-s3c2410/include/mach/regs-power.h')
| -rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-power.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-power.h b/arch/arm/mach-s3c2410/include/mach/regs-power.h new file mode 100644 index 00000000000..2d36353f57d --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-power.h @@ -0,0 +1,40 @@ +/* arch/arm/mach-s3c2410/include/mach/regs-power.h + * + * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C24XX power control register definitions +*/ + +#ifndef __ASM_ARM_REGS_PWR +#define __ASM_ARM_REGS_PWR __FILE__ + +#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR) + +#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) +#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) + +#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70) +#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74) +#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78) +#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C) + +#define S3C2412_PWRCFG_BATF_IRQ (1<<0) +#define S3C2412_PWRCFG_BATF_IGNORE (2<<0) +#define S3C2412_PWRCFG_BATF_SLEEP (3<<0) +#define S3C2412_PWRCFG_BATF_MASK (3<<0) + +#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6) +#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6) +#define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6) +#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6) +#define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6) + +#define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8) +#define S3C2412_PWRCFG_NAND_NORST (1<<9) + +#endif /* __ASM_ARM_REGS_PWR */ |