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| author | Paul Mundt <lethal@linux-sh.org> | 2009-12-21 11:59:55 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-12-21 11:59:55 +0900 |
| commit | 76e7461a21dfe13565b2a323b53c8cc963541126 (patch) | |
| tree | 8e399c71b38bb80c00d8a82310021b55ab6e8e33 /arch/arm/mm/proc-arm1020.S | |
| parent | d0b873fc73b793277c8a0824ce986b5bfeaef157 (diff) | |
| parent | dd59f6c76b265ed2ff18b497d6105a9511b1feb1 (diff) | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/arm/mm/proc-arm1020.S')
| -rw-r--r-- | arch/arm/mm/proc-arm1020.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index d9fb4b98c49..8012e24282b 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -231,17 +231,18 @@ ENTRY(arm1020_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_page(void *page) + * flush_kern_dcache_area(void *addr, size_t size) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - page - page aligned address + * - addr - kernel address + * - size - region size */ -ENTRY(arm1020_flush_kern_dcache_page) +ENTRY(arm1020_flush_kern_dcache_area) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE - add r1, r0, #PAGE_SZ + add r1, r0, r1 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry mcr p15, 0, ip, c7, c10, 4 @ drain WB add r0, r0, #CACHE_DLINESIZE @@ -335,7 +336,7 @@ ENTRY(arm1020_cache_fns) .long arm1020_flush_user_cache_range .long arm1020_coherent_kern_range .long arm1020_coherent_user_range - .long arm1020_flush_kern_dcache_page + .long arm1020_flush_kern_dcache_area .long arm1020_dma_inv_range .long arm1020_dma_clean_range .long arm1020_dma_flush_range |