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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-28 16:20:49 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-28 16:20:49 -0700 |
| commit | 27d68a36c4f1ca2fc6be82620843493462c08c51 (patch) | |
| tree | a06b451e19c25a77595c918ca81bbb30f0ec9ebf /arch/arm/mm/proc-arm1022.S | |
| parent | 76a22271fd14e3fe7660f8646db12f0780fa4fd2 (diff) | |
| parent | 583e7f5d36547f0d84caf71d43b71f0530a47766 (diff) | |
Merge branch 'nommu' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'nommu' of master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] nommu: backtrace code must not reference a discarded section
[ARM] nommu: Initial uCLinux support for MMU-based CPUs
[ARM] nommu: prevent Xscale-based machines being selected
[ARM] nommu: export flush_dcache_page()
[ARM] nommu: remove fault-armv, mmap and mm-armv files from nommu build
[ARM] Remove TABLE_SIZE, and several unused function prototypes
[ARM] nommu: Provide a simple flush_dcache_page implementation
[ARM] nommu: add arch/arm/Kconfig-nommu to Kconfig files
[ARM] nommu: add stubs for ioremap and friends
[ARM] nommu: avoid selecting TLB and CPU specific copy code
[ARM] nommu: uaccess tweaks
[ARM] nommu: adjust headers for !MMU ARM systems
[ARM] nommu: we need the TLS register emulation for nommu mode
Diffstat (limited to 'arch/arm/mm/proc-arm1022.S')
| -rw-r--r-- | arch/arm/mm/proc-arm1022.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index f778545d57a..b0ccff4fadd 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -3,6 +3,7 @@ * * Copyright (C) 2000 ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd. + * hacked for non-paged-MM by Hyok S. Choi, 2003. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -90,7 +91,9 @@ ENTRY(cpu_arm1022_reset) mov ip, #0 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches mcr p15, 0, ip, c7, c10, 4 @ drain WB +#ifdef CONFIG_MMU mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs +#endif mrc p15, 0, ip, c1, c0, 0 @ ctrl register bic ip, ip, #0x000f @ ............wcam bic ip, ip, #0x1100 @ ...i...s........ @@ -333,6 +336,7 @@ ENTRY(cpu_arm1022_dcache_clean_area) */ .align 5 ENTRY(cpu_arm1022_switch_mm) +#ifdef CONFIG_MMU #ifndef CONFIG_CPU_DCACHE_DISABLE mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries @@ -349,6 +353,7 @@ ENTRY(cpu_arm1022_switch_mm) mcr p15, 0, r1, c7, c10, 4 @ drain WB mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs +#endif mov pc, lr /* @@ -358,6 +363,7 @@ ENTRY(cpu_arm1022_switch_mm) */ .align 5 ENTRY(cpu_arm1022_set_pte) +#ifdef CONFIG_MMU str r1, [r0], #-2048 @ linux version eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY @@ -385,6 +391,7 @@ ENTRY(cpu_arm1022_set_pte) #ifndef CONFIG_CPU_DCACHE_DISABLE mcr p15, 0, r0, c7, c10, 1 @ clean D entry #endif +#endif /* CONFIG_MMU */ mov pc, lr __INIT @@ -394,7 +401,9 @@ __arm1022_setup: mov r0, #0 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 +#ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 +#endif mrc p15, 0, r0, c1, c0 @ get control register v4 ldr r5, arm1022_cr1_clear bic r0, r0, r5 |